ARM: mediatek: add UART dts for mt8127 and mt8135

This add dts support for mt8127 and mt8135 SOC UART

Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index a325404c714cc1fc07d25c73b85ce380eed91499..aaa786233d934e9885e0551f89fd8c27ae994cf5 100644 (file)
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -64,6 +64,12 @@
                        clock-frequency = <32000>;
                        #clock-cells = <0>;
                };
+
+               uart_clk: dummy26m {
+                       compatible = "fixed-clock";
+                       clock-frequency = <26000000>;
+                       #clock-cells = <0>;
+                };
        };
 
        soc {
@@ -100,5 +106,37 @@
                              <0 0x10214000 0 0x2000>,
                              <0 0x10216000 0 0x2000>;
                };
+
+               uart0: serial@11006000 {
+                       compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
+                       reg = <0 0x11002000 0 0x400>;
+                       interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart1: serial@11007000 {
+                       compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
+                       reg = <0 0x11003000 0 0x400>;
+                       interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart2: serial@11008000 {
+                       compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
+                       reg = <0 0x11004000 0 0x400>;
+                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart3: serial@11009000 {
+                       compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
+                       reg = <0 0x11005000 0 0x400>;
+                       interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
        };
 };

diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 2762fd57f739ed67eef91e24294772db36d89f85..a161e99ffcc432031d858f90df4078d3b3725e9c 100644 (file)
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -86,6 +86,13 @@
                        clock-frequency = <32000>;
                        #clock-cells = <0>;
                };
+
+               uart_clk: dummy26m {
+                       compatible = "fixed-clock";
+                       clock-frequency = <26000000>;
+                       #clock-cells = <0>;
+               };
+
        };
 
        soc {
@@ -122,5 +129,38 @@
                              <0 0x10214000 0 0x2000>,
                              <0 0x10216000 0 0x2000>;
                };
+
+               uart0: serial@11006000 {
+                       compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
+                       reg = <0 0x11006000 0 0x400>;
+                       interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart1: serial@11007000 {
+                       compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
+                       reg = <0 0x11007000 0 0x400>;
+                       interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart2: serial@11008000 {
+                       compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
+                       reg = <0 0x11008000 0 0x400>;
+                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart3: serial@11009000 {
+                       compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
+                       reg = <0 0x11009000 0 0x400>;
+                       interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
        };
 };