]> git.karo-electronics.de Git - linux-beck.git/commitdiff
ARM: dts: r8a7794: Add SYSC PM Domains
authorGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 20 Jan 2015 13:44:58 +0000 (14:44 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Wed, 27 Apr 2016 04:15:34 +0000 (14:15 +1000)
Add a device node for the System Controller.
Hook up the Cortex-A7 CPU cores and the Cortex-A7 L2 cache/SCU to their
respective PM Domains.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7794.dtsi

index b0bce43779f14b0d0975713dbc108619fc5d484b..70eff80a813ec85a772f0d1cad85442378e43a86 100644 (file)
@@ -12,6 +12,7 @@
 #include <dt-bindings/clock/r8a7794-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7794-sysc.h>
 
 / {
        compatible = "renesas,r8a7794";
@@ -42,6 +43,7 @@
                        compatible = "arm,cortex-a7";
                        reg = <0>;
                        clock-frequency = <1000000000>;
+                       power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
                        next-level-cache = <&L2_CA7>;
                };
 
                        compatible = "arm,cortex-a7";
                        reg = <1>;
                        clock-frequency = <1000000000>;
+                       power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
                        next-level-cache = <&L2_CA7>;
                };
        };
 
        L2_CA7: cache-controller@1 {
                compatible = "cache";
+               power-domains = <&sysc R8A7794_PD_CA7_SCU>;
                cache-unified;
                cache-level = <2>;
        };
                };
        };
 
+       sysc: system-controller@e6180000 {
+               compatible = "renesas,r8a7794-sysc";
+               reg = <0 0xe6180000 0 0x0200>;
+               #power-domain-cells = <1>;
+       };
+
        ipmmu_sy0: mmu@e6280000 {
                compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
                reg = <0 0xe6280000 0 0x1000>;