Ensure that our temporary page table entry is flushed from the TLB
before we resume normal operations. This ensures that userspace
won't trip over the stale TLB entry.
Tested-by: Kevin Hilman <khilman@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
#define __ASM_ARM_SUSPEND_H
#include <asm/memory.h>
+#include <asm/tlbflush.h>
extern void cpu_resume(void);
extern void __cpu_suspend(int, long, unsigned long,
void (*)(unsigned long));
__cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
+ flush_tlb_all();
}
#endif