ENGR00227241 mx6sl: clk: sdhc can not work at lp idle mode

issue:
Once entering low power idle mode, pll2_400 will be bypass which will change
the clk rate of sdhc root clk. so far, there's no mechanism to inform sdhc
for changing of root clk in current driver structure.

fix:
Revert "ENGR00226096 mx6sl: remove high set point for usdhc"

This reverts commit 97aee96a34ca63da0d1d602a19b3a444352e5803.

Acked-by: Robby CAI <r63905@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>

diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index 748bb13edcb605d31f439ad9adf324f2c32d0d41..6de15622eede49e537658aff0329406ea6c479dc 100755 (executable)
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -2098,6 +2098,7 @@ static struct clk usdhc1_clk = {
        .round_rate = _clk_usdhc_round_rate,
        .set_rate = _clk_usdhc1_set_rate,
        .get_rate = _clk_usdhc1_get_rate,
+       .flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
@@ -2155,6 +2156,7 @@ static struct clk usdhc2_clk = {
        .round_rate = _clk_usdhc_round_rate,
        .set_rate = _clk_usdhc2_set_rate,
        .get_rate = _clk_usdhc2_get_rate,
+       .flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
@@ -2213,6 +2215,7 @@ static struct clk usdhc3_clk = {
        .round_rate = _clk_usdhc_round_rate,
        .set_rate = _clk_usdhc3_set_rate,
        .get_rate = _clk_usdhc3_get_rate,
+       .flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
@@ -2271,6 +2274,7 @@ static struct clk usdhc4_clk = {
        .round_rate = _clk_usdhc_round_rate,
        .set_rate = _clk_usdhc4_set_rate,
        .get_rate = _clk_usdhc4_get_rate,
+       .flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static unsigned long _clk_ssi_round_rate(struct clk *clk,