drm/i915/skl: Block disable call for pw1 if dmc firmware is present.

Another interesting criteria to work dmc as expected is pw1 to be
enabled by driver and dmc will shut it off in its execution
sequence. If already disabled by driver dmc will get confuse and
behave differently than expected found during pc10 entry issue
for skl.

So berfore we disable power-well 1, added check if dmc firmware is
present and driver will not disable power well 1, but for any reason
if firmware is not present of failed to load we can shut off the
power well 1 which will save some power.

As skl is currently fully dependent on dmc to go in lowest possible
power state (dc6) but the same is not applicable for bxt. Display
engine can enter into dc9 without dmc, hence unblocking disable call.

v1: Initial version.

v2: Rebased as per current patch series.

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Reviewed-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 85c35fdfac659cedf055f2746011e6fff6ed31a3..4a815bb6cfcaf42b3252e2d286f6ce7f0c57dd45 100644 (file)
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -656,9 +656,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
                }
        } else {
                if (enable_requested) {
-                       I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
-                       POSTING_READ(HSW_PWR_WELL_DRIVER);
-                       DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
+                       if (IS_SKYLAKE(dev) &&
+                               (power_well->data == SKL_DISP_PW_1) &&
+                               (intel_csr_load_status_get(dev_priv) == FW_LOADED))
+                               DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n");
+                       else {
+                               I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
+                               POSTING_READ(HSW_PWR_WELL_DRIVER);
+                               DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
+                       }
 
                        if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
                                power_well->data == SKL_DISP_PW_2) {