arm64: dts: Add L2 cache node to msm8916

The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the
dtsi file so that the cache hierarchy can be probed.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index ba8184d0f948c1408b296c9684e495e490087276..42573a7d4a94d4f76a83fc86fa688e17ea527a51 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -61,24 +61,33 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x1>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU2: cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x2>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU3: cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x3>;
+                       next-level-cache = <&L2_0>;
+               };
+
+               L2_0: l2-cache {
+                     compatible = "cache";
+                     cache-level = <2>;
                };
        };