Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index bde6d1e9630a876a5141f54748e3b48825771f2d..bb87740baa6a41fc2fe80ae73290bdbeecd59b85 100644 (file)
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -52,7 +52,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
                        if (*reg == id) {
                                fdt_setprop_string(blob, off, "status", "okay");
                        } else {
-                               u32 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
+                               u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
                                val = cpu_to_fdt32(val);
                                fdt_setprop_string(blob, off, "status",
                                                                "disabled");

diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index d90d39767b6451217ed98c9f9acb6f64c3eea45b..699441b46a48c97b87247b5d28201d1ff6b5e9e8 100644 (file)
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -65,6 +65,9 @@ void get_sys_info (sys_info_t * sysInfo)
 int get_clocks (void)
 {
        sys_info_t sys_info;
+#ifdef CONFIG_MPC8544
+       volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR;
+#endif
 #if defined(CONFIG_CPM2)
        volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
        uint sccr, dfbrg;
@@ -78,8 +81,34 @@ int get_clocks (void)
        gd->cpu_clk = sys_info.freqProcessor;
        gd->bus_clk = sys_info.freqSystemBus;
        gd->mem_clk = sys_info.freqDDRBus;
+
+       /*
+        * The base clock for I2C depends on the actual SOC.  Unfortunately,
+        * there is no pattern that can be used to determine the frequency, so
+        * the only choice is to look up the actual SOC number and use the value
+        * for that SOC. This information is taken from application note
+        * AN2919.
+        */
+#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+       defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
        gd->i2c1_clk = sys_info.freqSystemBus;
-       gd->i2c2_clk = sys_info.freqSystemBus;
+#elif defined(CONFIG_MPC8544)
+       /*
+        * On the 8544, the I2C clock is the same as the SEC clock.  This can be
+        * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
+        * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
+        * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
+        * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
+        */
+       if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
+               gd->i2c1_clk = sys_info.freqSystemBus / 3;
+       else
+               gd->i2c1_clk = sys_info.freqSystemBus / 2;
+#else
+       /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
+       gd->i2c1_clk = sys_info.freqSystemBus / 2;
+#endif
+       gd->i2c2_clk = gd->i2c1_clk;
 
 #if defined(CONFIG_CPM2)
        gd->vco_out = 2*sys_info.freqSystemBus;

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 01cb2d74fa06fb92050cbf4a656ec5b60577334b..dc6e278ff4300e6c91772c033808d80d65bfafd9 100644 (file)
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1570,7 +1570,9 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_RIO_CTLS      0x00000008
 #define MPC85xx_PORDEVSR_RIO_DEV_ID    0x00000007
        uint    pordbgmsr;      /* 0xe0010 - POR debug mode status register */
-       char    res1[12];
+       uint    pordevsr2;      /* 0xe0014 - POR I/O device status regsiter 2 */
+#define MPC85xx_PORDEVSR2_SEC_CFG      0x00000020
+       char    res1[8];
        uint    gpporcr;        /* 0xe0020 - General-purpose POR configuration register */
        char    res2[12];
        uint    gpiocr;         /* 0xe0030 - GPIO control register */