* 26-27: ri Ring Index
* 28-31: reserved
*/
-
struct pkt_stat_desc {
u32 word0;
u32 word1;
* 13: TCP checksum assist
* 14: UDP checksum assist
*/
-
#define TXDESC_FLAG_LASTPKT 0x0001
#define TXDESC_FLAG_FIRSTPKT 0x0002
#define TXDESC_FLAG_INTPROC 0x0004
/* Tx Statistics. */
u32 tx_underflows;
-
u32 tx_collisions;
u32 tx_excessive_collisions;
u32 tx_first_collisions;
/* Rx Statistics. */
u32 rx_overflows;
-
u32 rx_length_errs;
u32 rx_align_errs;
u32 rx_crc_errs;
* Subsequent operations need only to check that bits 1:0 are equal
* to 1 prior to starting a single byte read/write
*/
-
for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
/* Read registers grouped in DWORD1 */
if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®))
* All inputs are disabled during this write cycle and the EEPROM will
* not respond to any access until the internal write is complete.
*/
-
err = eeprom_wait_ready(pdev, NULL);
if (err < 0)
return err;
/* A single byte read is similar to the single byte write, with the
* exception of the data flow:
*/
-
err = eeprom_wait_ready(pdev, NULL);
if (err < 0)
return err;
spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
/* Wait for outstanding Receive packets */
-
et131x_disable_txrx(adapter->netdev);
/* Gate off JAGCore 3 clock domains */
* rings. Also, FBR1 remains a constant size - when it's size doubles
* the number of entries halves. FBR0 increases in size, however.
*/
-
if (adapter->registry_jumbo_packet < 2048) {
rx_ring->fbr[0]->buffsize = 256;
rx_ring->fbr[0]->num_entries = 512;
/* Check the net_device flags and set the device independent flags
* accordingly
*/
-
if (netdev->flags & IFF_PROMISC)
adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
else
/* Init the device with the new settings */
et131x_adapter_setup(adapter);
-
et131x_enable_txrx(netdev);
return result;