clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8ch

SPDIF_8CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index dab759b2d18c41d92fd2676aec0099a55931004d..caf0b944d813d75cd61c76715496d9698ee4601c 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -353,7 +353,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
        COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(32), 0,
                        RK3368_CLKGATE_CON(6), 5, GFLAGS),
-       COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0,
+       COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(31), 8, 2, MFLAGS,
                        RK3368_CLKGATE_CON(6), 6, GFLAGS),
        COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,