r8169: use correct barrier between cacheable and non-cacheable memory

commit 4c020a961a812ffae9846b917304cea504c3a733 upstream.

r8169 needs certain writes to be visible to other CPUs or the NIC before
touching the hardware, but was using smp_wmb() which is only required to
order cacheable memory access. Switch to wmb() which is required to
order both cacheable and non-cacheable memory.

Noticed by Catalin Marinas and Paul Mackerras.

Signed-off-by: David Dillow <dave@thedillows.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index ab753234e35a4f2036a89c4dbcfeff35d32687b1..9d3dd3ce8e9cd473f752bf4f2097ec8b2dc102fe 100644 (file)
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -4316,7 +4316,7 @@ static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 
        tp->cur_tx += frags + 1;
 
-       smp_wmb();
+       wmb();
 
        RTL_W8(TxPoll, NPQ);    /* set polling bit */
 
@@ -4676,7 +4676,7 @@ static int rtl8169_poll(struct napi_struct *napi, int budget)
                 * until it does.
                 */
                tp->intr_mask = 0xffff;
-               smp_wmb();
+               wmb();
                RTL_W16(IntrMask, tp->intr_event);
        }