#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/imx1-clock.h>
+#include <asm/irq.h>
#include "clk.h"
-#include "common.h"
-#include "hardware.h"
+
+#define MX1_CCM_BASE_ADDR 0x0021b000
+#define MX1_TIM1_BASE_ADDR 0x00220000
+#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/imx21-clock.h>
+#include <asm/irq.h>
#include "clk.h"
-#include "common.h"
-#include "hardware.h"
+
+#define MX21_CCM_BASE_ADDR 0x10027000
+#define MX21_GPT1_BASE_ADDR 0x10003000
+#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
static void __iomem *ccm __initdata;
#include <linux/of_irq.h>
#include "clk.h"
-#include "common.h"
-#include "hardware.h"
#define CCM_MPCTL 0x00
#define CCM_UPCTL 0x04
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/imx27-clock.h>
+#include <soc/imx/revision.h>
+#include <asm/irq.h>
#include "clk.h"
-#include "common.h"
-#include "hardware.h"
+
+#define MX27_CCM_BASE_ADDR 0x10027000
+#define MX27_GPT1_BASE_ADDR 0x10003000
+#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
static void __iomem *ccm __initdata;
#include <linux/io.h>
#include <linux/err.h>
#include <linux/of.h>
+#include <soc/imx/revision.h>
+#include <asm/irq.h>
#include "clk.h"
-#include "common.h"
-#include "crmregs-imx3.h"
-#include "hardware.h"
-#include "mx31.h"
+
+#define MX31_CCM_BASE_ADDR 0x53f80000
+#define MX31_GPT1_BASE_ADDR 0x53f90000
+#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
+
+#define MXC_CCM_CCMR 0x00
+#define MXC_CCM_PDR0 0x04
+#define MXC_CCM_PDR1 0x08
+#define MXC_CCM_MPCTL 0x10
+#define MXC_CCM_UPCTL 0x14
+#define MXC_CCM_SRPCTL 0x18
+#define MXC_CCM_CGR0 0x20
+#define MXC_CCM_CGR1 0x24
+#define MXC_CCM_CGR2 0x28
+#define MXC_CCM_PMCR0 0x5c
static const char *mcu_main_sel[] = { "spll", "mpll", };
static const char *per_sel[] = { "per_div", "ipg", };
#include <linux/clkdev.h>
#include <linux/of.h>
#include <linux/err.h>
+#include <soc/imx/revision.h>
+#include <asm/irq.h>
-#include "crmregs-imx3.h"
#include "clk.h"
-#include "common.h"
-#include "hardware.h"
+
+#define MX35_CCM_BASE_ADDR 0x53f80000
+#define MX35_GPT1_BASE_ADDR 0x53f90000
+#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
+
+#define MXC_CCM_PDR0 0x04
+#define MX35_CCM_PDR2 0x0c
+#define MX35_CCM_PDR3 0x10
+#define MX35_CCM_PDR4 0x14
+#define MX35_CCM_MPCTL 0x1c
+#define MX35_CCM_PPCTL 0x20
+#define MX35_CCM_CGR0 0x2c
+#define MX35_CCM_CGR1 0x30
+#define MX35_CCM_CGR2 0x34
+#define MX35_CCM_CGR3 0x38
struct arm_ahb_div {
unsigned char arm, ahb, sel;
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <soc/imx/revision.h>
#include <dt-bindings/clock/imx5-clock.h>
#include "clk.h"
-#include "common.h"
-#include "hardware.h"
#define MX51_DPLL1_BASE 0x83f80000
#define MX51_DPLL2_BASE 0x83f84000
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <soc/imx/revision.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
#include "clk.h"
-#include "common.h"
-#include "hardware.h"
static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
#include <dt-bindings/clock/imx6sl-clock.h>
#include "clk.h"
-#include "common.h"
#define CCSR 0xc
#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
#include <linux/types.h>
#include "clk.h"
-#include "common.h"
#define CCDR 0x4
#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16)
#include <linux/err.h>
#include "clk.h"
-#include "common.h"
-#include "hardware.h"
/**
* pll v1
extern spinlock_t imx_ccm_lock;
+/*
+ * This is a stop-gap solution for clock drivers like imx1/imx21 which call
+ * mxc_timer_init() to initialize timer for non-DT boot. It can be removed
+ * when these legacy non-DT support is converted or dropped.
+ */
+void mxc_timer_init(unsigned long pbase, int irq);
+
void imx_check_clocks(struct clk *clks[], unsigned int count);
extern void imx_cscmr1_fixup(u32 *val);