drm/mediatek: modify the factor to make the pll_rate set in the 1G-2G range

Currently, the code sets the "pll" to the desired multiple
of the pixel clock manully(4*3m 8*3,etc).  The valid range
of the pll is 1G-2G, however, when the pixel clock is bigger
than 167MHz,  the "pll" will be set to a invalid value( > 2G),
then the "pll" will be 2GHz, thus the pixel clock will be in
correct. Change the factor to make the "pll" be set in the
(1G, 2G) range.

Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 0186e500d2a544d8c90769428c7673bec1cd68c0..90fb831ef031b9794df4f1ef95609204bedce93a 100644 (file)
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -432,11 +432,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
        unsigned long pll_rate;
        unsigned int factor;
 
+       /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
        pix_rate = 1000UL * mode->clock;
-       if (mode->clock <= 74000)
+       if (mode->clock <= 27000)
+               factor = 16 * 3;
+       else if (mode->clock <= 84000)
                factor = 8 * 3;
-       else
+       else if (mode->clock <= 167000)
                factor = 4 * 3;
+       else
+               factor = 2 * 3;
        pll_rate = pix_rate * factor;
 
        dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",