drm/i915: Warn when DPIO read returns 0xffffffff

DPIO reads from groups/broadcast register offsets for PCS and
TX return all 1's. If that result gets used for something
we'll probably end up doing something wrong. So warn when that
happens.

FIXME there might be some registers where all 1's is a valid value,
so ideally we should check the register offset instead...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: copypaste the FIXME comment into the code.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 0954f132726ea0ae15593364ef976168fc2c909f..b1a5514e695a71d95b3a6b76522a1a119a41a4bd 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -182,6 +182,14 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
 
        vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
                        DPIO_OPCODE_REG_READ, reg, &val);
+
+       /*
+        * FIXME: There might be some registers where all 1's is a valid value,
+        * so ideally we should check the register offset instead...
+        */
+       WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n",
+            pipe_name(pipe), reg, val);
+
        return val;
 }