sky2: Added support for Optima EEE

This patch adds support for the Optima EEE chipset.

Signed-off-by: Mirko Lindner <mlindner@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c
index 28a54451a3e5060344c91af03cc1d51d557bae59..f1163b2aa2847449620c466f2ba5a66d713d597d 100644 (file)
--- a/drivers/net/ethernet/marvell/sky2.c
+++ b/drivers/net/ethernet/marvell/sky2.c
@@ -141,6 +141,7 @@ static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
+       { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
        { 0 }
 };
 
@@ -3349,6 +3350,17 @@ static void sky2_reset(struct sky2_hw *hw)
                        sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
                                         reg);
 
+               if (hw->chip_id == CHIP_ID_YUKON_PRM &&
+                       hw->chip_rev == CHIP_REV_YU_PRM_A0) {
+                       /* change PHY Interrupt polarity to low active */
+                       reg = sky2_read16(hw, GPHY_CTRL);
+                       sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
+
+                       /* adapt HW for low active PHY Interrupt */
+                       reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
+                       sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
+               }
+
                sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 
                /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
@@ -4871,7 +4883,7 @@ static const char *sky2_name(u8 chipid, char *buf, int sz)
                "UL 2",         /* 0xba */
                "Unknown",      /* 0xbb */
                "Optima",       /* 0xbc */
-               "Optima Prime", /* 0xbd */
+               "OptimaEEE",    /* 0xbd */
                "Optima 2",     /* 0xbe */
        };
 

diff --git a/drivers/net/ethernet/marvell/sky2.h b/drivers/net/ethernet/marvell/sky2.h
index 3c896ce80b71ec1facc6f04f666ab80711c5dfe3..615ac63ea8603a802896d2bd810d4c2ac874204c 100644 (file)
--- a/drivers/net/ethernet/marvell/sky2.h
+++ b/drivers/net/ethernet/marvell/sky2.h
@@ -23,6 +23,7 @@ enum {
        PSM_CONFIG_REG3  = 0x164,
        PSM_CONFIG_REG4  = 0x168,
 
+       PCI_LDO_CTRL    = 0xbc,
 };
 
 /* Yukon-2 */
@@ -586,6 +587,10 @@ enum yukon_supr_rev {
        CHIP_REV_YU_SU_B1    = 3,
 };
 
+enum yukon_prm_rev {
+       CHIP_REV_YU_PRM_Z1   = 1,
+       CHIP_REV_YU_PRM_A0   = 2,
+};
 
 /*     B2_Y2_CLK_GATE   8 bit  Clock Gating (Yukon-2 only) */
 enum {