ENGR00163052: CPUFREQ does not report correct frequency

When DVFS_CORE is enabled, the following command reports incorrect frequency:
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq

Fix this by ensuring the CPUFREQ does not change the frequency
when DVFS_CORE is active. And DVFS-CORE informs CPUFREQ of the
change done to CPU frequency.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index bb2a6c8c99003f770b56123b6b70f86c45db7b7a..5efe833347034f5a7564dc0a6511b7d458376e89 100755 (executable)
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -32,8 +32,6 @@
 #define CLK32_FREQ     32768
 #define NANOSECOND     (1000 * 1000 * 1000)
 
-int cpufreq_trig_needed;
-
 static int cpu_freq_khz_min;
 static int cpu_freq_khz_max;
 
@@ -122,12 +120,10 @@ static int mxc_set_target(struct cpufreq_policy *policy,
        if (policy->cpu > num_cpus)
                return 0;
 
-#ifdef CONFIG_ARCH_MX5
        if (dvfs_core_is_active) {
                printk(KERN_DEBUG"DVFS-CORE is active, cannot change frequency using CPUFREQ\n");
                return ret;
        }
-#endif
 
        cpufreq_frequency_table_target(policy, imx_freq_table,
                        target_freq, relation, &index);

diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c
index 006530416edd8fe54c82fbf89c48ad7959978026..183a6dd4b0bf83e5434ba80c5829fa11d8c73a8f 100755 (executable)
--- a/arch/arm/plat-mxc/dvfs_core.c
+++ b/arch/arm/plat-mxc/dvfs_core.c
@@ -84,6 +84,7 @@
 #define CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER                0x4
 #define CCM_CDHIPR_ARM_PODF_BUSY               0x10000
 
+int cpufreq_trig_needed;
 int dvfs_core_is_active;
 static struct mxc_dvfs_platform_data *dvfs_data;
 static struct device *dvfs_dev;
@@ -98,7 +99,6 @@ static int maxf;
 static int minf;
 
 extern void setup_pll(void);
-extern int cpufreq_trig_needed;
 extern int (*set_cpu_voltage)(u32 cpu_volt);
 
 struct timeval core_prev_intr;
@@ -485,12 +485,12 @@ static int start_dvfs(void)
        reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
        /* FSVAIM=0 */
        reg = (reg & ~MXC_DVFSCNTR_FSVAIM);
+
        /* Set MAXF, MINF */
-       if (!cpu_is_mx6q()) {
-               reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK
-                                       | MXC_DVFSCNTR_MINF_MASK));
-               reg |= 1 << MXC_DVFSCNTR_MAXF_OFFSET;
-       }
+       reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK
+                               | MXC_DVFSCNTR_MINF_MASK));
+       reg |= 1 << MXC_DVFSCNTR_MAXF_OFFSET;
+
        /* Select ARM domain */
        reg |= MXC_DVFSCNTR_DVFIS;
        /* Enable DVFS frequency adjustment interrupt */
@@ -526,7 +526,6 @@ static int start_dvfs(void)
        spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
 
        printk(KERN_DEBUG "DVFS is started\n");
-
        return 0;
 }
 
@@ -666,6 +665,11 @@ END:
                loops_per_jiffy =
                        dvfs_cpu_jiffies(old_loops_per_jiffy,
                                curr_cpu/1000, clk_get_rate(cpu_clk) / 1000);
+#endif
+#if defined (CONFIG_CPU_FREQ)
+               /* Fix CPU frequency for CPUFREQ. */
+               for (cpu = 0; cpu < num_online_cpus(); cpu++)
+                       cpufreq_get(cpu);
 #endif
                cpufreq_trig_needed = 0;
        }
@@ -734,6 +738,11 @@ void stop_dvfs(void)
                                curr_cpu/1000, clk_get_rate(cpu_clk) / 1000);
 #endif
 
+#if defined (CONFIG_CPU_FREQ)
+                       /* Fix CPU frequency for CPUFREQ. */
+                       for (cpu = 0; cpu < num_online_cpus(); cpu++)
+                               cpufreq_get(cpu);
+#endif
                }
                spin_lock_irqsave(&mxc_dvfs_core_lock, flags);