]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
arm64: dts: mt8173: move clock from phy node into port nodes
authorchunfeng.yun@mediatek.com <chunfeng.yun@mediatek.com>
Fri, 31 Mar 2017 07:35:34 +0000 (15:35 +0800)
committerMatthias Brugger <matthias.bgg@gmail.com>
Mon, 15 May 2017 08:47:16 +0000 (10:47 +0200)
there is a reference clock for each port, HighSpeed port is 48M,
and SuperSpeed port is usually 26M. it is flexible to move it
into port node, then unused clock can be disabled.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
arch/arm64/boot/dts/mediatek/mt8173.dtsi

index 1dc4629512359ace7a5ddf8e91dbcb971644473f..1c9e0d54b89fc42131f5d2b5a1aefda9b97173e5 100644 (file)
                u3phy: usb-phy@11290000 {
                        compatible = "mediatek,mt8173-u3phy";
                        reg = <0 0x11290000 0 0x800>;
-                       clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
-                       clock-names = "u3phya_ref";
                        #address-cells = <2>;
                        #size-cells = <2>;
                        ranges;
 
                        u2port0: usb-phy@11290800 {
                                reg = <0 0x11290800 0 0x100>;
+                               clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+                               clock-names = "ref";
                                #phy-cells = <1>;
                                status = "okay";
                        };
 
                        u3port0: usb-phy@11290900 {
                                reg = <0 0x11290900 0 0x700>;
+                               clocks = <&clk26m>;
+                               clock-names = "ref";
                                #phy-cells = <1>;
                                status = "okay";
                        };
 
                        u2port1: usb-phy@11291000 {
                                reg = <0 0x11291000 0 0x100>;
+                               clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+                               clock-names = "ref";
                                #phy-cells = <1>;
                                status = "okay";
                        };