drm/i915: Add more registers to the whitelist for mesa

These are additional registers needed for performance monitoring and
ARB_draw_indirect extensions in mesa.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76719
Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
[danvet: Squash in fixup from Brad requested by Ken.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 29184d6c002730d55438ae6d3b348b43a4d24b6c..9bac0979a2944ff79c64bde8c7f2feb0b11c541a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -408,10 +408,20 @@ static const u32 gen7_render_regs[] = {
        REG64(PS_INVOCATION_COUNT),
        REG64(PS_DEPTH_COUNT),
        OACONTROL, /* Only allowed for LRI and SRM. See below. */
+       GEN7_3DPRIM_END_OFFSET,
+       GEN7_3DPRIM_START_VERTEX,
+       GEN7_3DPRIM_VERTEX_COUNT,
+       GEN7_3DPRIM_INSTANCE_COUNT,
+       GEN7_3DPRIM_START_INSTANCE,
+       GEN7_3DPRIM_BASE_VERTEX,
        REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
        REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
        REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
        REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
+       REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
+       REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
+       REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
+       REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
        GEN7_SO_WRITE_OFFSET(0),
        GEN7_SO_WRITE_OFFSET(1),
        GEN7_SO_WRITE_OFFSET(2),

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 01c05af1bae7f83fbe29de0790530c7af004d6a3..46ea2332e45c576b1a250fc9887fa13d8ec1f2b9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -428,6 +428,15 @@
 /* There are the 4 64-bit counter registers, one for each stream output */
 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
 
+#define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)
+
+#define GEN7_3DPRIM_END_OFFSET          0x2420
+#define GEN7_3DPRIM_START_VERTEX        0x2430
+#define GEN7_3DPRIM_VERTEX_COUNT        0x2434
+#define GEN7_3DPRIM_INSTANCE_COUNT      0x2438
+#define GEN7_3DPRIM_START_INSTANCE      0x243C
+#define GEN7_3DPRIM_BASE_VERTEX         0x2440
+
 #define OACONTROL 0x2360
 
 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068