drm/i915: possibly invalidate TLB before context switch

From http://intellinuxgraphics.org/documentation/SNB/IHD_OS_Vol1_Part3.pdf

[DevSNB] If Flush TLB invalidation Mode is enabled it's the driver's
responsibility to invalidate the TLBs at least once after the previous
context switch after any GTT mappings changed (including new GTT
entries).  This can be done by a pipelined PIPE_CONTROL with TLB inv bit
set immediately before MI_SET_CONTEXT.

On GEN7 the invalidation mode is explicitly set, but this appears to be
lacking for GEN6. Since I don't know the history on this, I've decided
to dynamically read the value at ring init time, and use that value
throughout.

v2: better comment (daniel)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index d49d5fc0a592ff61c43dd9e9d99d319dc5fd5876..fb1e1d22572cb33eb7766b1911a090902ca8451f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -324,6 +324,17 @@ mi_set_context(struct intel_ring_buffer *ring,
 {
        int ret;
 
+       /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
+        * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
+        * explicitly, so we rely on the value at ring init, stored in
+        * itlb_before_ctx_switch.
+        */
+       if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
+               ret = ring->flush(ring, 0, 0);
+               if (ret)
+                       return ret;
+       }
+
        ret = intel_ring_begin(ring, 6);
        if (ret)
                return ret;

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a041492fdd4629f8e4ad01d882473121c6ac6824..7a16f16371e63a9eae2120f70fae45192d855130 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -423,6 +423,13 @@ static int init_render_ring(struct intel_ring_buffer *ring)
                 */
                I915_WRITE(CACHE_MODE_0,
                           _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
+
+               /* This is not explicitly set for GEN6, so read the register.
+                * see intel_ring_mi_set_context() for why we care.
+                * TODO: consider explicitly setting the bit for GEN5
+                */
+               ring->itlb_before_ctx_switch =
+                       !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
        }
 
        if (INTEL_INFO(dev)->gen >= 6)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index b7884b90474abab49fac76c670797e697f450b65..594c9c4ad39640467414e7d4374b9790ee9cb440 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -116,6 +116,10 @@ struct  intel_ring_buffer {
 
        wait_queue_head_t irq_queue;
 
+       /**
+        * Do an explicit TLB flush before MI_SET_CONTEXT
+        */
+       bool itlb_before_ctx_switch;
        struct i915_hw_context *default_context;
        struct drm_i915_gem_object *last_context_obj;