]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
dt: bindings: fpga: add xilinx slave-serial binding description
authorAnatolij Gustschin <agust@denx.de>
Fri, 24 Mar 2017 00:34:25 +0000 (19:34 -0500)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 8 Apr 2017 15:45:28 +0000 (17:45 +0200)
Add dt binding documentation details for Xilinx FPGA configuration
over slave serial interface.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Moritz Fischer <mdf@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
new file mode 100644 (file)
index 0000000..9766f74
--- /dev/null
@@ -0,0 +1,44 @@
+Xilinx Slave Serial SPI FPGA Manager
+
+Xilinx Spartan-6 FPGAs support a method of loading the bitstream over
+what is referred to as "slave serial" interface.
+The slave serial link is not technically SPI, and might require extra
+circuits in order to play nicely with other SPI slaves on the same bus.
+
+See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
+
+Required properties:
+- compatible: should contain "xlnx,fpga-slave-serial"
+- reg: spi chip select of the FPGA
+- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
+- done-gpios: config status pin (referred to as DONE in the manual)
+
+Example for full FPGA configuration:
+
+       fpga-region0 {
+               compatible = "fpga-region";
+               fpga-mgr = <&fpga_mgr_spi>;
+               #address-cells = <0x1>;
+               #size-cells = <0x1>;
+       };
+
+       spi1: spi@10680 {
+               compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
+               pinctrl-0 = <&spi0_pins>;
+               pinctrl-names = "default";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               cell-index = <1>;
+               interrupts = <92>;
+               clocks = <&coreclk 0>;
+               status = "okay";
+
+               fpga_mgr_spi: fpga-mgr@0 {
+                       compatible = "xlnx,fpga-slave-serial";
+                       spi-max-frequency = <60000000>;
+                       spi-cpha;
+                       reg = <0>;
+                       done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+                       prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+               };
+       };