drm/i915: clear FPGA_DBG_RM_NOCLAIM when capturing error state

In the error state function we read the registers without checking if
the power well is on, so after doing this we have to clear the
FPGA_DBG_RM_NOCLAIM bit to prevent the next I915_WRITE from detecting
it and printing an error message.

The first version of this patch was checking for the power well state
and then avoiding reading registers that were off, but the reviewers
requested to just read the registers any way and then later clear the
FPGA_DBG_RM_NOCLAIM bit.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 260545cc50493b380983071532a1ebffb734d05f..544d766f6ef3c6bc09bd49f15d02700ac243ee68 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9842,6 +9842,13 @@ intel_display_capture_error_state(struct drm_device *dev)
                error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
        }
 
+       /* In the code above we read the registers without checking if the power
+        * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
+        * prevent the next I915_WRITE from detecting it and printing an error
+        * message. */
+       if (HAS_POWER_WELL(dev))
+               I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+
        return error;
 }