int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
+u32 intel_rc6_residency(struct drm_i915_private *dev_priv,
+ i915_reg_t reg);
#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
static u32 calc_residency(struct drm_i915_private *dev_priv,
i915_reg_t reg)
{
- u64 raw_time; /* 32b value may overflow during fixed point math */
- u64 units = 128ULL, div = 100000ULL;
- u32 ret;
-
- if (!intel_enable_rc6())
- return 0;
-
- intel_runtime_pm_get(dev_priv);
-
- /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- units = 1;
- div = dev_priv->czclk_freq;
-
- if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
- units <<= 8;
- } else if (IS_GEN9_LP(dev_priv)) {
- units = 1;
- div = 1200; /* 833.33ns */
- }
-
- raw_time = I915_READ(reg) * units;
- ret = DIV_ROUND_UP_ULL(raw_time, div);
-
- intel_runtime_pm_put(dev_priv);
- return ret;
+ return intel_rc6_residency(dev_priv, reg);
}
static ssize_t
dev_priv->pm.suspended = false;
atomic_set(&dev_priv->pm.wakeref_count, 0);
}
+
+u32 intel_rc6_residency(struct drm_i915_private *dev_priv,
+ i915_reg_t reg)
+{
+ u64 raw_time; /* 32b value may overflow during fixed point math */
+ u64 units = 128ULL, div = 100000ULL;
+ u32 ret;
+
+ if (!intel_enable_rc6())
+ return 0;
+
+ intel_runtime_pm_get(dev_priv);
+
+ /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ units = 1;
+ div = dev_priv->czclk_freq;
+
+ if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
+ units <<= 8;
+ } else if (IS_GEN9_LP(dev_priv)) {
+ units = 1;
+ div = 1200; /* 833.33ns */
+ }
+
+ raw_time = I915_READ(reg) * units;
+ ret = DIV_ROUND_UP_ULL(raw_time, div);
+
+ intel_runtime_pm_put(dev_priv);
+ return ret;
+}