#include <mach/ipu-v3.h>
#include <mach/mxc_hdmi.h>
#include <mach/mxc_asrc.h>
+#include <mach/mipi_dsi.h>
#include <asm/irq.h>
#include <asm/setup.h>
static struct clk *sata_clk;
static int mma8451_position = 3;
static int mag3110_position;
+static int disable_ldb;
extern char *gp_reg_id;
extern int epdc_enabled;
.clk_map_ver = 2,
};
+static void mx6_reset_mipi_dsi(void)
+{
+ gpio_set_value(SABRESD_DISP_PWR_EN, 1);
+ gpio_set_value(SABRESD_DISP_RST_B, 1);
+ udelay(10);
+ gpio_set_value(SABRESD_DISP_RST_B, 0);
+ udelay(50);
+ gpio_set_value(SABRESD_DISP_RST_B, 1);
+
+ /*
+ * it needs to delay 120ms minimum for reset complete
+ */
+ msleep(120);
+}
+
+static struct mipi_dsi_platform_data mipi_dsi_pdata = {
+ .ipu_id = 0,
+ .disp_id = 1,
+ .lcd_panel = "TRULY-WVGA",
+ .reset = mx6_reset_mipi_dsi,
+};
+
static struct ipuv3_fb_platform_data sabresd_fb_data[] = {
{ /*fb0*/
.disp_dev = "ldb",
.pcie_dis = SABRESD_PCIE_DIS_B,
};
+static int __init early_disable_ldb(char *p)
+{
+ /*mipi dsi need pll3_pfd_540M as 540MHz, ldb will change to 454Mhz*/
+ disable_ldb = 1;
+ return 0;
+}
+
+early_param("disable_ldb", early_disable_ldb);
/*!
* Board specific initialization.
*/
ldb_data.sec_ipu_id = 0;
ldb_data.sec_disp_id = 1;
hdmi_core_data.disp_id = 1;
+ mipi_dsi_pdata.ipu_id = 0;
+ mipi_dsi_pdata.disp_id = 1;
}
imx6q_add_mxc_hdmi_core(&hdmi_core_data);
imx6q_add_ipuv3fb(i, &sabresd_fb_data[i]);
imx6q_add_vdoa();
+ imx6q_add_mipi_dsi(&mipi_dsi_pdata);
imx6q_add_lcdif(&lcdif_data);
- imx6q_add_ldb(&ldb_data);
+ if (!disable_ldb)
+ imx6q_add_ldb(&ldb_data);
imx6q_add_v4l2_output(0);
imx6q_add_v4l2_capture(0);
imx6q_add_mipi_csi2(&mipi_csi2_pdata);