ENGR00181194 IPUv3:Correct pixel clock definition and register

MX6Q has 2 IPUs, each IPU has 2 DIs, so there are totally 4
different pixel clocks. This patch adds maximal pixel clock
number from 2 to 4. Also, the patch fixes potential build
warning caused by the overflow on ipu_lookups structure in case
MXC_IPU_MAX_NUM is 1.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>

diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
index 61687ad1411cfc9f03a4670e7380ce953ada9cf6..88265952414c7e43366a8c18418beced6ecf3a38 100644 (file)
--- a/drivers/mxc/ipu3/ipu_common.c
+++ b/drivers/mxc/ipu3/ipu_common.c
@@ -149,8 +149,8 @@ static int __devinit ipu_clk_setup_enable(struct ipu_soc *ipu,
        }
        dev_dbg(ipu->dev, "ipu_clk = %lu\n", clk_get_rate(ipu->ipu_clk));
 
-       ipu->pixel_clk[0] = ipu_pixel_clk[0];
-       ipu->pixel_clk[1] = ipu_pixel_clk[1];
+       ipu->pixel_clk[0] = ipu_pixel_clk[pdev->id][0];
+       ipu->pixel_clk[1] = ipu_pixel_clk[pdev->id][1];
 
        ipu_lookups[pdev->id][0].clk = &ipu->pixel_clk[0];
        ipu_lookups[pdev->id][1].clk = &ipu->pixel_clk[1];

diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c
index d2fa65dd774ee5138ed82591d38618d2cc0ad43e..4a774396ee992ce83f262a748f12f8f86f23645c 100644 (file)
--- a/drivers/mxc/ipu3/ipu_disp.c
+++ b/drivers/mxc/ipu3/ipu_disp.c
@@ -174,44 +174,68 @@ static int _ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
 #else
 #define __INIT_CLK_DEBUG(n)
 #endif
-struct clk ipu_pixel_clk[] = {
+struct clk ipu_pixel_clk[MXC_IPU_MAX_NUM][MXC_DI_NUM_PER_IPU] = {
        {
-               __INIT_CLK_DEBUG(pixel_clk_0)
-                       .id = 0,
-               .get_rate = _ipu_pixel_clk_get_rate,
-               .set_rate = _ipu_pixel_clk_set_rate,
-               .round_rate = _ipu_pixel_clk_round_rate,
-               .set_parent = _ipu_pixel_clk_set_parent,
-               .enable = _ipu_pixel_clk_enable,
-               .disable = _ipu_pixel_clk_disable,
+               {
+                __INIT_CLK_DEBUG(ipu1_pixel_clk_0)
+                .id = 0,
+                .get_rate = _ipu_pixel_clk_get_rate,
+                .set_rate = _ipu_pixel_clk_set_rate,
+                .round_rate = _ipu_pixel_clk_round_rate,
+                .set_parent = _ipu_pixel_clk_set_parent,
+                .enable = _ipu_pixel_clk_enable,
+                .disable = _ipu_pixel_clk_disable,
+               },
+               {
+                __INIT_CLK_DEBUG(ipu1_pixel_clk_1)
+                .id = 1,
+                .get_rate = _ipu_pixel_clk_get_rate,
+                .set_rate = _ipu_pixel_clk_set_rate,
+                .round_rate = _ipu_pixel_clk_round_rate,
+                .set_parent = _ipu_pixel_clk_set_parent,
+                .enable = _ipu_pixel_clk_enable,
+                .disable = _ipu_pixel_clk_disable,
+               },
        },
        {
-               __INIT_CLK_DEBUG(pixel_clk_1)
-                       .id = 1,
-               .get_rate = _ipu_pixel_clk_get_rate,
-               .set_rate = _ipu_pixel_clk_set_rate,
-               .round_rate = _ipu_pixel_clk_round_rate,
-               .set_parent = _ipu_pixel_clk_set_parent,
-               .enable = _ipu_pixel_clk_enable,
-               .disable = _ipu_pixel_clk_disable,
+               {
+                __INIT_CLK_DEBUG(ipu2_pixel_clk_0)
+                .id = 0,
+                .get_rate = _ipu_pixel_clk_get_rate,
+                .set_rate = _ipu_pixel_clk_set_rate,
+                .round_rate = _ipu_pixel_clk_round_rate,
+                .set_parent = _ipu_pixel_clk_set_parent,
+                .enable = _ipu_pixel_clk_enable,
+                .disable = _ipu_pixel_clk_disable,
+               },
+               {
+                __INIT_CLK_DEBUG(ipu2_pixel_clk_1)
+                .id = 1,
+                .get_rate = _ipu_pixel_clk_get_rate,
+                .set_rate = _ipu_pixel_clk_set_rate,
+                .round_rate = _ipu_pixel_clk_round_rate,
+                .set_parent = _ipu_pixel_clk_set_parent,
+                .enable = _ipu_pixel_clk_enable,
+                .disable = _ipu_pixel_clk_disable,
+               },
        },
 };
 
-struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][2] = {
+struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][MXC_DI_NUM_PER_IPU] = {
        {
                {
-                       .con_id = "pixel_clk_0",
+                       .con_id = "ipu1_pixel_clk_0",
                },
                {
-                       .con_id = "pixel_clk_1",
+                       .con_id = "ipu1_pixel_clk_1",
                },
        },
        {
                {
-                       .con_id = "pixel_clk_0",
+                       .con_id = "ipu2_pixel_clk_0",
                },
                {
-                       .con_id = "pixel_clk_1",
+                       .con_id = "ipu2_pixel_clk_1",
                },
        },
 };

diff --git a/drivers/mxc/ipu3/ipu_prv.h b/drivers/mxc/ipu3/ipu_prv.h
index 526a2c0a36f00988bb2c365dc74db50ff71b10ff..aed8db839c66f414e0ffcbb6795cb8a95b3e1fe6 100644 (file)
--- a/drivers/mxc/ipu3/ipu_prv.h
+++ b/drivers/mxc/ipu3/ipu_prv.h
@@ -20,16 +20,13 @@
 #include <linux/interrupt.h>
 #include <linux/fsl_devices.h>
 
-#ifdef CONFIG_MXC_IPU_V3H
-#define MXC_IPU_MAX_NUM        2
-#else
-#define MXC_IPU_MAX_NUM        1
-#endif
+#define MXC_IPU_MAX_NUM                2
+#define MXC_DI_NUM_PER_IPU     2
 
 /* Globals */
 extern int dmfc_type_setup;
-extern struct clk ipu_pixel_clk[];
-extern struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][2];
+extern struct clk ipu_pixel_clk[MXC_IPU_MAX_NUM][MXC_DI_NUM_PER_IPU];
+extern struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][MXC_DI_NUM_PER_IPU];
 
 #define IDMA_CHAN_INVALID      0xFF
 #define HIGH_RESOLUTION_WIDTH  1024