]> git.karo-electronics.de Git - linux-beck.git/commitdiff
ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes
authorEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Fri, 26 Jul 2013 13:18:00 +0000 (10:18 -0300)
committerJason Cooper <jason@lakedaemon.net>
Tue, 6 Aug 2013 14:11:27 +0000 (14:11 +0000)
Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the
hardware.

Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to correspond
to each MBus window.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
arch/arm/boot/dts/armada-370-mirabox.dts
arch/arm/boot/dts/armada-370-xp.dtsi
arch/arm/boot/dts/armada-370.dtsi
arch/arm/boot/dts/armada-xp-db.dts
arch/arm/boot/dts/armada-xp-gp.dts
arch/arm/boot/dts/armada-xp-mv78230.dtsi
arch/arm/boot/dts/armada-xp-mv78260.dtsi
arch/arm/boot/dts/armada-xp-mv78460.dtsi
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts

index 19341d26f7a34d4b06854223a0821345f91ede18..2471d9da767bfad77a4419c20d17407473e704fb 100644 (file)
                ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
                          MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
 
+               pcie-controller {
+                       status = "okay";
+
+                       /* Internal mini-PCIe connector */
+                       pcie@1,0 {
+                               /* Port 0, Lane 0 */
+                               status = "okay";
+                       };
+
+                       /* Connected on the PCB to a USB 3.0 XHCI controller */
+                       pcie@2,0 {
+                               /* Port 1, Lane 0 */
+                               status = "okay";
+                       };
+               };
+
                internal-regs {
                        serial@12000 {
                                clock-frequency = <200000000>;
                                        reg = <0x25>;
                                };
                        };
-
-                       pcie-controller {
-                               status = "okay";
-
-                               /* Internal mini-PCIe connector */
-                               pcie@1,0 {
-                                       /* Port 0, Lane 0 */
-                                       status = "okay";
-                               };
-
-                               /* Connected on the PCB to a USB 3.0 XHCI controller */
-                               pcie@2,0 {
-                                       /* Port 1, Lane 0 */
-                                       status = "okay";
-                               };
-                       };
                };
        };
 };
index 073dd203a819bc8f428a5fdd121ed33ff8ea1281..e984ce6bb33f0742e61c4815dabf50175e27a9e8 100644 (file)
@@ -44,6 +44,8 @@
                #size-cells = <1>;
                controller = <&mbusc>;
                interrupt-parent = <&mpic>;
+               pcie-mem-aperture = <0xe0000000 0x8000000>;
+               pcie-io-aperture  = <0xe8000000 0x100000>;
 
                devbus-bootcs {
                        compatible = "marvell,mvebu-devbus";
index bd21d497c13fb323ddc1db989a671bcd284997e3..648e5303446e6f49dc813e229450288e470fafae 100644 (file)
                        reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
                };
 
+               pcie-controller {
+                       compatible = "marvell,armada-370-pcie";
+                       status = "disabled";
+                       device_type = "pci";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       bus-range = <0x00 0xff>;
+
+                       ranges =
+                              <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                               0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+                               0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                               0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
+                               0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
+                               0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
+
+                       pcie@1,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                               reg = <0x0800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 58>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 5>;
+                               status = "disabled";
+                       };
+
+                       pcie@2,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
+                               reg = <0x1000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 62>;
+                               marvell,pcie-port = <1>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 9>;
+                               status = "disabled";
+                       };
+               };
+
                internal-regs {
                        system-controller@18200 {
                                compatible = "marvell,armada-370-xp-system-controller";
                                        0x18304 0x4>;
                                status = "okay";
                        };
-
-                       pcie-controller {
-                               compatible = "marvell,armada-370-pcie";
-                               status = "disabled";
-                               device_type = "pci";
-
-                               #address-cells = <3>;
-                               #size-cells = <2>;
-
-                               bus-range = <0x00 0xff>;
-
-                               ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
-                                       0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
-                                       0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                       0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                               pcie@1,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-                                       reg = <0x0800 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 58>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 5>;
-                                       status = "disabled";
-                               };
-
-                               pcie@2,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
-                                       reg = <0x1000 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 62>;
-                                       marvell,pcie-port = <1>;
-                                       marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 9>;
-                                       status = "disabled";
-                               };
-                       };
                };
        };
 };
index 76ae1a95111bf287b37df39671ac1e0928ff8d63..bcf6d79a57ec55febf5f037affdee94e901f3628 100644 (file)
                        };
                };
 
+               pcie-controller {
+                       status = "okay";
+
+                       /*
+                        * All 6 slots are physically present as
+                        * standard PCIe slots on the board.
+                        */
+                       pcie@1,0 {
+                               /* Port 0, Lane 0 */
+                               status = "okay";
+                       };
+                       pcie@2,0 {
+                               /* Port 0, Lane 1 */
+                               status = "okay";
+                       };
+                       pcie@3,0 {
+                               /* Port 0, Lane 2 */
+                               status = "okay";
+                       };
+                       pcie@4,0 {
+                               /* Port 0, Lane 3 */
+                               status = "okay";
+                       };
+                       pcie@9,0 {
+                               /* Port 2, Lane 0 */
+                               status = "okay";
+                       };
+                       pcie@10,0 {
+                               /* Port 3, Lane 0 */
+                               status = "okay";
+                       };
+               };
+
                internal-regs {
                        serial@12000 {
                                clock-frequency = <250000000>;
                                        spi-max-frequency = <20000000>;
                                };
                        };
-
-                       pcie-controller {
-                               status = "okay";
-
-                               /*
-                                * All 6 slots are physically present as
-                                * standard PCIe slots on the board.
-                                */
-                               pcie@1,0 {
-                                       /* Port 0, Lane 0 */
-                                       status = "okay";
-                               };
-                               pcie@2,0 {
-                                       /* Port 0, Lane 1 */
-                                       status = "okay";
-                               };
-                               pcie@3,0 {
-                                       /* Port 0, Lane 2 */
-                                       status = "okay";
-                               };
-                               pcie@4,0 {
-                                       /* Port 0, Lane 3 */
-                                       status = "okay";
-                               };
-                               pcie@9,0 {
-                                       /* Port 2, Lane 0 */
-                                       status = "okay";
-                               };
-                               pcie@10,0 {
-                                       /* Port 3, Lane 0 */
-                                       status = "okay";
-                               };
-                       };
-
                };
        };
 };
index 8c0de201c65b670d48c6f1de753528f71773877a..2298e4a910e230748dda13cb70cab55713932a10 100644 (file)
                        };
                };
 
+               pcie-controller {
+                       status = "okay";
+
+                       /*
+                        * The 3 slots are physically present as
+                        * standard PCIe slots on the board.
+                        */
+                       pcie@1,0 {
+                               /* Port 0, Lane 0 */
+                               status = "okay";
+                       };
+                       pcie@9,0 {
+                               /* Port 2, Lane 0 */
+                               status = "okay";
+                       };
+                       pcie@10,0 {
+                               /* Port 3, Lane 0 */
+                               status = "okay";
+                       };
+               };
+
                internal-regs {
                        serial@12000 {
                                clock-frequency = <250000000>;
                                        spi-max-frequency = <108000000>;
                                };
                        };
-
-                       pcie-controller {
-                               status = "okay";
-
-                               /*
-                                * The 3 slots are physically present as
-                                * standard PCIe slots on the board.
-                                */
-                               pcie@1,0 {
-                                       /* Port 0, Lane 0 */
-                                       status = "okay";
-                               };
-                               pcie@9,0 {
-                                       /* Port 2, Lane 0 */
-                                       status = "okay";
-                               };
-                               pcie@10,0 {
-                                       /* Port 3, Lane 0 */
-                                       status = "okay";
-                               };
-                       };
                };
        };
 };
index f8eaa383e07fbdc6904711d72699bc2df6eb0190..f093e3974d6a16839a612a3c9fd003619b3b6600 100644 (file)
        };
 
        soc {
+               /*
+                * MV78230 has 2 PCIe units Gen2.0: One unit can be
+                * configured as x4 or quad x1 lanes. One unit is
+                * x4/x1.
+                */
+               pcie-controller {
+                       compatible = "marvell,armada-xp-pcie";
+                       status = "disabled";
+                       device_type = "pci";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       bus-range = <0x00 0xff>;
+
+                       ranges =
+                              <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                               0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                               0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                               0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                               0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                               0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+                               0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
+                               0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
+                               0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
+                               0x82000000 0x3 0       MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
+                               0x81000000 0x3 0       MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
+                               0x82000000 0x4 0       MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
+                               0x81000000 0x4 0       MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
+                               0x82000000 0x9 0       MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
+                               0x81000000 0x9 0       MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */>;
+
+                       pcie@1,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                               reg = <0x0800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                         0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 58>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 5>;
+                               status = "disabled";
+                       };
+
+                       pcie@2,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+                               reg = <0x1000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                         0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 59>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <1>;
+                               clocks = <&gateclk 6>;
+                               status = "disabled";
+                       };
+
+                       pcie@3,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+                               reg = <0x1800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                         0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 60>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <2>;
+                               clocks = <&gateclk 7>;
+                               status = "disabled";
+                       };
+
+                       pcie@4,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+                               reg = <0x2000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                                         0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 61>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <3>;
+                               clocks = <&gateclk 8>;
+                               status = "disabled";
+                       };
+
+                       pcie@9,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+                               reg = <0x4800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
+                                         0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 99>;
+                               marvell,pcie-port = <2>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 26>;
+                               status = "disabled";
+                       };
+               };
+
                internal-regs {
                        pinctrl {
                                compatible = "marvell,mv78230-pinctrl";
                                #interrupts-cells = <2>;
                                interrupts = <87>, <88>, <89>;
                        };
-
-                       /*
-                        * MV78230 has 2 PCIe units Gen2.0: One unit can be
-                        * configured as x4 or quad x1 lanes. One unit is
-                        * x4/x1.
-                        */
-                       pcie-controller {
-                               compatible = "marvell,armada-xp-pcie";
-                               status = "disabled";
-                               device_type = "pci";
-
-#address-cells = <3>;
-#size-cells = <2>;
-
-                               bus-range = <0x00 0xff>;
-
-                               ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
-                                       0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
-                                       0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
-                                       0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
-                                       0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
-                                       0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                       0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                               pcie@1,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-                                       reg = <0x0800 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 58>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 5>;
-                                       status = "disabled";
-                               };
-
-                               pcie@2,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-                                       reg = <0x1000 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 59>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <1>;
-                                       clocks = <&gateclk 6>;
-                                       status = "disabled";
-                               };
-
-                               pcie@3,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
-                                       reg = <0x1800 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 60>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <2>;
-                                       clocks = <&gateclk 7>;
-                                       status = "disabled";
-                               };
-
-                               pcie@4,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
-                                       reg = <0x2000 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 61>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <3>;
-                                       clocks = <&gateclk 8>;
-                                       status = "disabled";
-                               };
-
-                               pcie@9,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-                                       reg = <0x4800 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 99>;
-                                       marvell,pcie-port = <2>;
-                                       marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 26>;
-                                       status = "disabled";
-                               };
-                       };
                };
        };
 };
index 985373a045610a5be21460f0067f537bd51e3bca..6dc3921df9b39098fa788dc1a3b274b678393746 100644 (file)
        };
 
        soc {
+               /*
+                * MV78260 has 3 PCIe units Gen2.0: Two units can be
+                * configured as x4 or quad x1 lanes. One unit is
+                * x4/x1.
+                */
+               pcie-controller {
+                       compatible = "marvell,armada-xp-pcie";
+                       status = "disabled";
+                       device_type = "pci";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       bus-range = <0x00 0xff>;
+
+                       ranges =
+                              <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                               0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                               0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                               0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                               0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                               0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
+                               0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
+                               0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+                               0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
+                               0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
+                               0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
+                               0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
+                               0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
+                               0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
+                               0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
+                               0x82000000 0x9 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
+                               0x81000000 0x9 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
+                               0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
+                               0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
+
+                       pcie@1,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                               reg = <0x0800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                         0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 58>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 5>;
+                               status = "disabled";
+                       };
+
+                       pcie@2,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+                               reg = <0x1000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 59>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <1>;
+                               clocks = <&gateclk 6>;
+                               status = "disabled";
+                       };
+
+                       pcie@3,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+                               reg = <0x1800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                         0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 60>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <2>;
+                               clocks = <&gateclk 7>;
+                               status = "disabled";
+                       };
+
+                       pcie@4,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+                               reg = <0x2000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                                         0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 61>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <3>;
+                               clocks = <&gateclk 8>;
+                               status = "disabled";
+                       };
+
+                       pcie@9,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+                               reg = <0x4800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
+                                         0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 99>;
+                               marvell,pcie-port = <2>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 26>;
+                               status = "disabled";
+                       };
+
+                       pcie@10,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
+                               reg = <0x5000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
+                                         0x81000000 0 0 0x81000000 0xa 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 103>;
+                               marvell,pcie-port = <3>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 27>;
+                               status = "disabled";
+                       };
+               };
+
                internal-regs {
                        pinctrl {
                                compatible = "marvell,mv78260-pinctrl";
                                clocks = <&gateclk 1>;
                                status = "disabled";
                        };
-
-                       /*
-                        * MV78260 has 3 PCIe units Gen2.0: Two units can be
-                        * configured as x4 or quad x1 lanes. One unit is
-                        * x4/x1.
-                        */
-                       pcie-controller {
-                               compatible = "marvell,armada-xp-pcie";
-                               status = "disabled";
-                               device_type = "pci";
-
-                               #address-cells = <3>;
-                               #size-cells = <2>;
-
-                               bus-range = <0x00 0xff>;
-
-                               ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
-                                       0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
-                                       0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
-                                       0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
-                                       0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
-                                       0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
-                                       0x82000000 0 0x82000 0x82000 0 0x00002000   /* Port 3.0 registers */
-                                       0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                       0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                               pcie@1,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-                                       reg = <0x0800 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 58>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 5>;
-                                       status = "disabled";
-                               };
-
-                               pcie@2,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-                                       reg = <0x1000 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 59>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <1>;
-                                       clocks = <&gateclk 6>;
-                                       status = "disabled";
-                               };
-
-                               pcie@3,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
-                                       reg = <0x1800 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 60>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <2>;
-                                       clocks = <&gateclk 7>;
-                                       status = "disabled";
-                               };
-
-                               pcie@4,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
-                                       reg = <0x2000 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 61>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <3>;
-                                       clocks = <&gateclk 8>;
-                                       status = "disabled";
-                               };
-
-                               pcie@9,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-                                       reg = <0x4800 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 99>;
-                                       marvell,pcie-port = <2>;
-                                       marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 26>;
-                                       status = "disabled";
-                               };
-
-                               pcie@10,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
-                                       reg = <0x5000 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 103>;
-                                       marvell,pcie-port = <3>;
-                                       marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 27>;
-                                       status = "disabled";
-                               };
-                       };
                };
        };
 };
index f8bf25a20a71fee7e4d1804899698665b851745b..a6661e3aea2362721a81e98efd2a502046ef5c7f 100644 (file)
        };
 
        soc {
+               /*
+                * MV78460 has 4 PCIe units Gen2.0: Two units can be
+                * configured as x4 or quad x1 lanes. Two units are
+                * x4/x1.
+                */
+               pcie-controller {
+                       compatible = "marvell,armada-xp-pcie";
+                       status = "disabled";
+                       device_type = "pci";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       bus-range = <0x00 0xff>;
+
+                       ranges =
+                              <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                               0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                               0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                               0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                               0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                               0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
+                               0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
+                               0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
+                               0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
+                               0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
+                               0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+                               0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
+                               0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
+                               0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
+                               0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
+                               0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
+                               0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
+                               0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
+
+                               0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
+                               0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
+                               0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
+                               0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
+                               0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
+                               0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
+                               0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
+                               0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */
+
+                               0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
+                               0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */
+
+                               0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
+                               0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
+
+                       pcie@1,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                               reg = <0x0800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                         0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 58>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 5>;
+                               status = "disabled";
+                       };
+
+                       pcie@2,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
+                               reg = <0x1000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                         0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 59>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <1>;
+                               clocks = <&gateclk 6>;
+                               status = "disabled";
+                       };
+
+                       pcie@3,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
+                               reg = <0x1800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                         0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 60>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <2>;
+                               clocks = <&gateclk 7>;
+                               status = "disabled";
+                       };
+
+                       pcie@4,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
+                               reg = <0x2000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                                         0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 61>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <3>;
+                               clocks = <&gateclk 8>;
+                               status = "disabled";
+                       };
+
+                       pcie@5,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
+                               reg = <0x2800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
+                                         0x81000000 0 0 0x81000000 0x5 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 62>;
+                               marvell,pcie-port = <1>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 9>;
+                               status = "disabled";
+                       };
+
+                       pcie@6,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
+                               reg = <0x3000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
+                                         0x81000000 0 0 0x81000000 0x6 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 63>;
+                               marvell,pcie-port = <1>;
+                               marvell,pcie-lane = <1>;
+                               clocks = <&gateclk 10>;
+                               status = "disabled";
+                       };
+
+                       pcie@7,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
+                               reg = <0x3800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
+                                         0x81000000 0 0 0x81000000 0x7 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 64>;
+                               marvell,pcie-port = <1>;
+                               marvell,pcie-lane = <2>;
+                               clocks = <&gateclk 11>;
+                               status = "disabled";
+                       };
+
+                       pcie@8,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
+                               reg = <0x4000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
+                                         0x81000000 0 0 0x81000000 0x8 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 65>;
+                               marvell,pcie-port = <1>;
+                               marvell,pcie-lane = <3>;
+                               clocks = <&gateclk 12>;
+                               status = "disabled";
+                       };
+
+                       pcie@9,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
+                               reg = <0x4800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
+                                         0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 99>;
+                               marvell,pcie-port = <2>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 26>;
+                               status = "disabled";
+                       };
+
+                       pcie@10,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
+                               reg = <0x5000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
+                                         0x81000000 0 0 0x81000000 0xa 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 103>;
+                               marvell,pcie-port = <3>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 27>;
+                               status = "disabled";
+                       };
+               };
+
                internal-regs {
                        pinctrl {
                                compatible = "marvell,mv78460-pinctrl";
                                clocks = <&gateclk 1>;
                                status = "disabled";
                        };
-
-                       /*
-                        * MV78460 has 4 PCIe units Gen2.0: Two units can be
-                        * configured as x4 or quad x1 lanes. Two units are
-                        * x4/x1.
-                        */
-                       pcie-controller {
-                               compatible = "marvell,armada-xp-pcie";
-                               status = "disabled";
-                               device_type = "pci";
-
-                               #address-cells = <3>;
-                               #size-cells = <2>;
-
-                               bus-range = <0x00 0xff>;
-
-                               ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
-                                       0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
-                                       0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
-                                       0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
-                                       0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
-                                       0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
-                                       0x82000000 0 0x82000 0x82000 0 0x00002000   /* Port 3.0 registers */
-                                       0x82000000 0 0x84000 0x84000 0 0x00002000   /* Port 1.1 registers */
-                                       0x82000000 0 0x88000 0x88000 0 0x00002000   /* Port 1.2 registers */
-                                       0x82000000 0 0x8c000 0x8c000 0 0x00002000   /* Port 1.3 registers */
-                                       0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                       0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                               pcie@1,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-                                       reg = <0x0800 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 58>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 5>;
-                                       status = "disabled";
-                               };
-
-                               pcie@2,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
-                                       reg = <0x1000 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 59>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <1>;
-                                       clocks = <&gateclk 6>;
-                                       status = "disabled";
-                               };
-
-                               pcie@3,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
-                                       reg = <0x1800 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 60>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <2>;
-                                       clocks = <&gateclk 7>;
-                                       status = "disabled";
-                               };
-
-                               pcie@4,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
-                                       reg = <0x2000 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 61>;
-                                       marvell,pcie-port = <0>;
-                                       marvell,pcie-lane = <3>;
-                                       clocks = <&gateclk 8>;
-                                       status = "disabled";
-                               };
-
-                               pcie@5,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
-                                       reg = <0x2800 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 62>;
-                                       marvell,pcie-port = <1>;
-                                       marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 9>;
-                                       status = "disabled";
-                               };
-
-                               pcie@6,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
-                                       reg = <0x3000 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 63>;
-                                       marvell,pcie-port = <1>;
-                                       marvell,pcie-lane = <1>;
-                                       clocks = <&gateclk 10>;
-                                       status = "disabled";
-                               };
-
-                               pcie@7,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
-                                       reg = <0x3800 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 64>;
-                                       marvell,pcie-port = <1>;
-                                       marvell,pcie-lane = <2>;
-                                       clocks = <&gateclk 11>;
-                                       status = "disabled";
-                               };
-
-                               pcie@8,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
-                                       reg = <0x4000 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 65>;
-                                       marvell,pcie-port = <1>;
-                                       marvell,pcie-lane = <3>;
-                                       clocks = <&gateclk 12>;
-                                       status = "disabled";
-                               };
-                               pcie@9,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
-                                       reg = <0x4800 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 99>;
-                                       marvell,pcie-port = <2>;
-                                       marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 26>;
-                                       status = "disabled";
-                               };
-
-                               pcie@10,0 {
-                                       device_type = "pci";
-                                       assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
-                                       reg = <0x5000 0 0 0 0>;
-                                       #address-cells = <3>;
-                                       #size-cells = <2>;
-                                       #interrupt-cells = <1>;
-                                       ranges;
-                                       interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 103>;
-                                       marvell,pcie-port = <3>;
-                                       marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 27>;
-                                       status = "disabled";
-                               };
-                       };
                };
        };
 };
index 2b60ee08ef9f56cb0d1ee3ced8dcf92690573990..5695afcc04bf1a7fa7fa13024acd8bb794464ed5 100644 (file)
                        };
                };
 
+               pcie-controller {
+                       status = "okay";
+                       /* Internal mini-PCIe connector */
+                       pcie@1,0 {
+                               /* Port 0, Lane 0 */
+                               status = "okay";
+                       };
+               };
+
                internal-regs {
                        serial@12000 {
                                clock-frequency = <250000000>;
                        usb@51000 {
                                status = "okay";
                        };
-
-                       pcie-controller {
-                               status = "okay";
-                               /* Internal mini-PCIe connector */
-                               pcie@1,0 {
-                                       /* Port 0, Lane 0 */
-                                       status = "okay";
-                               };
-                       };
                };
        };
 };