PCI: designware: Ensure ATU is enabled before IO/conf space accesses

Read back the ATU CR2 register to ensure ATU programming is effective
before any subsequent I/O or config space accesses.

Without this, PCI device enumeration is unreliable.

[bhelgaas: changelog, comment]
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 540f077c37eae7b59b983c31fa6ddce51d8bda6e..7353371b3f1505da5040d452b1f3ea56d2319397 100644 (file)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -154,6 +154,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
 static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
                int type, u64 cpu_addr, u64 pci_addr, u32 size)
 {
+       u32 val;
+
        dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
                          PCIE_ATU_VIEWPORT);
        dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
@@ -164,6 +166,12 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
        dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
        dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
        dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+
+       /*
+        * Make sure ATU enable takes effect before any subsequent config
+        * and I/O accesses.
+        */
+       dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
 }
 
 static struct irq_chip dw_msi_irq_chip = {