ARM: imx: add always-on clock array for i.mx6sl to maintain correct usecount

IPG, ARM and MMDC's clock should be enabled during kernel boot up,
so we need to maintain their usecount, otherwise, they may be
disabled unexpectedly if their children's clock are turned off, and
caused their parent PLLs also get disabled, which is incorrect.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 6617ac85068092b3ed0cd17fa9c62511bdb1b9c8..b71570df366cfe319160d3c78985b5388590db29 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -66,6 +66,10 @@ static struct clk_div_table video_div_table[] = {
 static struct clk *clks[IMX6SL_CLK_END];
 static struct clk_onecell_data clk_data;
 
+static const u32 clks_init_on[] __initconst = {
+       IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,
+};
+
 /*
  * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
  *           during WAIT mode entry process could cause cache memory
@@ -291,6 +295,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
                pr_warn("%s: failed to set AHB clock rate %d!\n",
                        __func__, ret);
 
+       /*
+        * Make sure those always on clocks are enabled to maintain the correct
+        * usecount and enabling/disabling of parent PLLs.
+        */
+       for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+               clk_prepare_enable(clks[clks_init_on[i]]);
+
        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);