clk: tegra: pll: Add dyn_ramp callback

Add a callback to the pll_params for custom dynamic ramping
functions which can be specified per PLL.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 1decca98008f508939eba1f32e80a1dd3fcfab0d..8901004025e75ee232e81d11fa86d32d86c669fc 100644 (file)
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -669,6 +669,13 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 
        _get_pll_mnp(pll, &old_cfg);
 
+       if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
+                       (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
+               ret = pll->params->dyn_ramp(pll, cfg);
+               if (!ret)
+                       return 0;
+       }
+
        if (state)
                _clk_pll_disable(hw);
 

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index c78d9d088a6d1c0ae731f14e5ddcfc90f1d60ac5..8dac213fa672138a87ad3d7d52db6fd6f46b798c 100644 (file)
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -213,6 +213,8 @@ struct tegra_clk_pll;
  *                             is already enabled, it will be done the first
  *                             time the rate is changed while the PLL is
  *                             disabled.
+ * @dyn_ramp:                  Callback which can be used to define a custom
+ *                             dynamic ramp function for a given PLL.
  *
  * Flags:
  * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
@@ -284,6 +286,8 @@ struct tegra_clk_pll_params {
        unsigned long   (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
                                unsigned long parent_rate);
        void    (*set_defaults)(struct tegra_clk_pll *pll);
+       int     (*dyn_ramp)(struct tegra_clk_pll *pll,
+                       struct tegra_clk_pll_freq_table *cfg);
 };
 
 #define TEGRA_PLL_USE_LOCK BIT(0)