#define APCI3120_RD_STATUS 0x02
#define APCI3120_RD_FIFO 0x00
-/* nWrMode_Select */
-#define APCI3120_ENABLE_SCAN 0x8
-#define APCI3120_ENABLE_EOS_INT 0x2
-
-#define APCI3120_ENABLE_EOC_INT 0x1
-
/* status register bits */
#define APCI3120_EOC 0x8000
#define APCI3120_EOS 0x2000
#define APCI3120_WATCHDOG 2
#define APCI3120_TIMER_DISABLE 0
#define APCI3120_TIMER_ENABLE 1
-#define APCI3120_ENABLE_TIMER_INT 0x04
#define APCI3120_WRITE_MODE_SELECT 0x0e
#define APCI3120_RD_STATUS 0x02
apci3120_timer_set_mode(dev, 0, APCI3120_TIMER_MODE4);
if (devpriv->b_EocEosInterrupt == APCI3120_ENABLE) {
- devpriv->mode |= APCI3120_ENABLE_EOC_INT;
+ devpriv->mode |= APCI3120_MODE_EOC_IRQ_ENA;
inw(dev->iobase + 0);
}
apci3120_timer_write(dev, 0, divisor);
/* Set the scan bit */
- devpriv->mode |= APCI3120_ENABLE_SCAN;
+ devpriv->mode |= APCI3120_MODE_SCAN_ENA;
outb(devpriv->mode,
dev->iobase + APCI3120_WRITE_MODE_SELECT);
/* If Interrupt function is loaded */
if (devpriv->b_EocEosInterrupt == APCI3120_ENABLE) {
- devpriv->mode |= APCI3120_ENABLE_EOS_INT;
+ devpriv->mode |= APCI3120_MODE_EOS_IRQ_ENA;
inw(dev->iobase + 0);
}
devpriv->b_InterruptMode = APCI3120_EOS_MODE;
devpriv->b_EocEosInterrupt = APCI3120_ENABLE;
- devpriv->mode |= APCI3120_ENABLE_EOS_INT;
+ devpriv->mode |= APCI3120_MODE_EOS_IRQ_ENA;
outb(devpriv->mode, dev->iobase + APCI3120_WRITE_MODE_SELECT);
if (cmd->stop_src == TRIG_COUNT) {
/* select EOS clock input for timer 2 */
devpriv->mode |= APCI3120_TIMER2_SELECT_EOS;
/* Enable timer2 interrupt */
- devpriv->mode |= APCI3120_ENABLE_TIMER_INT;
+ devpriv->mode |= APCI3120_MODE_TIMER2_IRQ_ENA;
outb(devpriv->mode,
dev->iobase + APCI3120_WRITE_MODE_SELECT);
devpriv->b_Timer2Mode = APCI3120_COUNTER;
send_sig(SIGIO, devpriv->tsk_Current, 0); /* send signal to the sample */
} else {
/* Disable EOC Interrupt */
- devpriv->mode &= ~APCI3120_ENABLE_EOC_INT;
+ devpriv->mode &= ~APCI3120_MODE_EOC_IRQ_ENA;
outb(devpriv->mode,
dev->iobase + APCI3120_WRITE_MODE_SELECT);
}
if (devpriv->ai_running) {
ui_Check = 0;
apci3120_interrupt_handle_eos(dev);
- devpriv->mode |= APCI3120_ENABLE_EOS_INT;
+ devpriv->mode |= APCI3120_MODE_EOS_IRQ_ENA;
outb(devpriv->mode,
dev->iobase + APCI3120_WRITE_MODE_SELECT);
} else {
}
} else {
- devpriv->mode &= ~APCI3120_ENABLE_EOS_INT;
+ devpriv->mode &= ~APCI3120_MODE_EOS_IRQ_ENA;
outb(devpriv->mode,
dev->iobase + APCI3120_WRITE_MODE_SELECT);
devpriv->b_EocEosInterrupt = APCI3120_DISABLE; /* Default settings */
switch (devpriv->b_Timer2Mode) {
case APCI3120_COUNTER:
- devpriv->mode &= ~APCI3120_ENABLE_EOS_INT;
+ devpriv->mode &= ~APCI3120_MODE_EOS_IRQ_ENA;
outb(devpriv->mode,
dev->iobase + APCI3120_WRITE_MODE_SELECT);
default:
/* disable Timer Interrupt */
- devpriv->mode &= ~APCI3120_ENABLE_TIMER_INT;
+ devpriv->mode &= ~APCI3120_MODE_TIMER2_IRQ_ENA;
outb(devpriv->mode,
dev->iobase + APCI3120_WRITE_MODE_SELECT);
}
apci3120_timer_enable(dev, 2, false);
/* Disable TIMER Interrupt */
- devpriv->mode &= ~APCI3120_ENABLE_TIMER_INT &
+ devpriv->mode &= ~APCI3120_MODE_TIMER2_IRQ_ENA &
~APCI3120_ENABLE_TIMER_COUNTER;
/* Disable Eoc and Eos Interrupts */
- devpriv->mode &= ~APCI3120_ENABLE_EOC_INT & ~APCI3120_ENABLE_EOS_INT;
+ devpriv->mode &= ~APCI3120_MODE_EOC_IRQ_ENA &
+ ~APCI3120_MODE_EOS_IRQ_ENA;
outb(devpriv->mode, dev->iobase + APCI3120_WRITE_MODE_SELECT);
if (data[0] == APCI3120_TIMER) { /* initialize timer */
/* enable disable interrupt */
if ((devpriv->b_Timer2Interrupt) == APCI3120_ENABLE) {
- devpriv->mode |= APCI3120_ENABLE_TIMER_INT;
+ devpriv->mode |= APCI3120_MODE_TIMER2_IRQ_ENA;
/* save the task structure to pass info to user */
devpriv->tsk_Current = current;
} else {
- devpriv->mode &= ~APCI3120_ENABLE_TIMER_INT;
+ devpriv->mode &= ~APCI3120_MODE_TIMER2_IRQ_ENA;
}
outb(devpriv->mode, dev->iobase + APCI3120_WRITE_MODE_SELECT);
devpriv->mode &= ~APCI3120_ENABLE_WATCHDOG;
}
/* Disable timer interrupt */
- devpriv->mode &= ~APCI3120_ENABLE_TIMER_INT;
+ devpriv->mode &= ~APCI3120_MODE_TIMER2_IRQ_ENA;
outb(devpriv->mode, dev->iobase + APCI3120_WRITE_MODE_SELECT);
apci3120_timer_enable(dev, 2, false);