Merge remote-tracking branch 'pinctrl/for-next'

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
new file mode 100644 (file)
index 0000000..1183f1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
@@ -0,0 +1,984 @@
+* Freescale IMX35 IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx35-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up for this pin. Please refer to imx35 datasheet for the valid pad
+  config settings.
+
+CONFIG bits definition:
+PAD_CTL_DRIVE_VOLAGAGE_18      (1 << 13)
+PAD_CTL_DRIVE_VOLAGAGE_33      (0 << 13)
+PAD_CTL_HYS                    (1 << 8)
+PAD_CTL_PKE                    (1 << 7)
+PAD_CTL_PUE                    (1 << 6)
+PAD_CTL_PUS_100K_DOWN          (0 << 4)
+PAD_CTL_PUS_47K_UP             (1 << 4)
+PAD_CTL_PUS_100K_UP            (2 << 4)
+PAD_CTL_PUS_22K_UP             (3 << 4)
+PAD_CTL_ODE_CMOS               (0 << 3)
+PAD_CTL_ODE_OPENDRAIN          (1 << 3)
+PAD_CTL_DSE_NOMINAL            (0 << 1)
+PAD_CTL_DSE_HIGH               (1 << 1)
+PAD_CTL_DSE_MAX                        (2 << 1)
+PAD_CTL_SRE_FAST               (1 << 0)
+PAD_CTL_SRE_SLOW               (0 << 0)
+
+See below for available PIN_FUNC_ID for imx35:
+0 MX35_PAD_CAPTURE__GPT_CAPIN1
+1 MX35_PAD_CAPTURE__GPT_CMPOUT2
+2 MX35_PAD_CAPTURE__CSPI2_SS1
+3 MX35_PAD_CAPTURE__EPIT1_EPITO
+4 MX35_PAD_CAPTURE__CCM_CLK32K
+5 MX35_PAD_CAPTURE__GPIO1_4
+6 MX35_PAD_COMPARE__GPT_CMPOUT1
+7 MX35_PAD_COMPARE__GPT_CAPIN2
+8 MX35_PAD_COMPARE__GPT_CMPOUT3
+9 MX35_PAD_COMPARE__EPIT2_EPITO
+10 MX35_PAD_COMPARE__GPIO1_5
+11 MX35_PAD_COMPARE__SDMA_EXTDMA_2
+12 MX35_PAD_WDOG_RST__WDOG_WDOG_B
+13 MX35_PAD_WDOG_RST__IPU_FLASH_STROBE
+14 MX35_PAD_WDOG_RST__GPIO1_6
+15 MX35_PAD_GPIO1_0__GPIO1_0
+16 MX35_PAD_GPIO1_0__CCM_PMIC_RDY
+17 MX35_PAD_GPIO1_0__OWIRE_LINE
+18 MX35_PAD_GPIO1_0__SDMA_EXTDMA_0
+19 MX35_PAD_GPIO1_1__GPIO1_1
+20 MX35_PAD_GPIO1_1__PWM_PWMO
+21 MX35_PAD_GPIO1_1__CSPI1_SS2
+22 MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT
+23 MX35_PAD_GPIO1_1__SDMA_EXTDMA_1
+24 MX35_PAD_GPIO2_0__GPIO2_0
+25 MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK
+26 MX35_PAD_GPIO3_0__GPIO3_0
+27 MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK
+28 MX35_PAD_RESET_IN_B__CCM_RESET_IN_B
+29 MX35_PAD_POR_B__CCM_POR_B
+30 MX35_PAD_CLKO__CCM_CLKO
+31 MX35_PAD_CLKO__GPIO1_8
+32 MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0
+33 MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1
+34 MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0
+35 MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1
+36 MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26
+37 MX35_PAD_VSTBY__CCM_VSTBY
+38 MX35_PAD_VSTBY__GPIO1_7
+39 MX35_PAD_A0__EMI_EIM_DA_L_0
+40 MX35_PAD_A1__EMI_EIM_DA_L_1
+41 MX35_PAD_A2__EMI_EIM_DA_L_2
+42 MX35_PAD_A3__EMI_EIM_DA_L_3
+43 MX35_PAD_A4__EMI_EIM_DA_L_4
+44 MX35_PAD_A5__EMI_EIM_DA_L_5
+45 MX35_PAD_A6__EMI_EIM_DA_L_6
+46 MX35_PAD_A7__EMI_EIM_DA_L_7
+47 MX35_PAD_A8__EMI_EIM_DA_H_8
+48 MX35_PAD_A9__EMI_EIM_DA_H_9
+49 MX35_PAD_A10__EMI_EIM_DA_H_10
+50 MX35_PAD_MA10__EMI_MA10
+51 MX35_PAD_A11__EMI_EIM_DA_H_11
+52 MX35_PAD_A12__EMI_EIM_DA_H_12
+53 MX35_PAD_A13__EMI_EIM_DA_H_13
+54 MX35_PAD_A14__EMI_EIM_DA_H2_14
+55 MX35_PAD_A15__EMI_EIM_DA_H2_15
+56 MX35_PAD_A16__EMI_EIM_A_16
+57 MX35_PAD_A17__EMI_EIM_A_17
+58 MX35_PAD_A18__EMI_EIM_A_18
+59 MX35_PAD_A19__EMI_EIM_A_19
+60 MX35_PAD_A20__EMI_EIM_A_20
+61 MX35_PAD_A21__EMI_EIM_A_21
+62 MX35_PAD_A22__EMI_EIM_A_22
+63 MX35_PAD_A23__EMI_EIM_A_23
+64 MX35_PAD_A24__EMI_EIM_A_24
+65 MX35_PAD_A25__EMI_EIM_A_25
+66 MX35_PAD_SDBA1__EMI_EIM_SDBA1
+67 MX35_PAD_SDBA0__EMI_EIM_SDBA0
+68 MX35_PAD_SD0__EMI_DRAM_D_0
+69 MX35_PAD_SD1__EMI_DRAM_D_1
+70 MX35_PAD_SD2__EMI_DRAM_D_2
+71 MX35_PAD_SD3__EMI_DRAM_D_3
+72 MX35_PAD_SD4__EMI_DRAM_D_4
+73 MX35_PAD_SD5__EMI_DRAM_D_5
+74 MX35_PAD_SD6__EMI_DRAM_D_6
+75 MX35_PAD_SD7__EMI_DRAM_D_7
+76 MX35_PAD_SD8__EMI_DRAM_D_8
+77 MX35_PAD_SD9__EMI_DRAM_D_9
+78 MX35_PAD_SD10__EMI_DRAM_D_10
+79 MX35_PAD_SD11__EMI_DRAM_D_11
+80 MX35_PAD_SD12__EMI_DRAM_D_12
+81 MX35_PAD_SD13__EMI_DRAM_D_13
+82 MX35_PAD_SD14__EMI_DRAM_D_14
+83 MX35_PAD_SD15__EMI_DRAM_D_15
+84 MX35_PAD_SD16__EMI_DRAM_D_16
+85 MX35_PAD_SD17__EMI_DRAM_D_17
+86 MX35_PAD_SD18__EMI_DRAM_D_18
+87 MX35_PAD_SD19__EMI_DRAM_D_19
+88 MX35_PAD_SD20__EMI_DRAM_D_20
+89 MX35_PAD_SD21__EMI_DRAM_D_21
+90 MX35_PAD_SD22__EMI_DRAM_D_22
+91 MX35_PAD_SD23__EMI_DRAM_D_23
+92 MX35_PAD_SD24__EMI_DRAM_D_24
+93 MX35_PAD_SD25__EMI_DRAM_D_25
+94 MX35_PAD_SD26__EMI_DRAM_D_26
+95 MX35_PAD_SD27__EMI_DRAM_D_27
+96 MX35_PAD_SD28__EMI_DRAM_D_28
+97 MX35_PAD_SD29__EMI_DRAM_D_29
+98 MX35_PAD_SD30__EMI_DRAM_D_30
+99 MX35_PAD_SD31__EMI_DRAM_D_31
+100 MX35_PAD_DQM0__EMI_DRAM_DQM_0
+101 MX35_PAD_DQM1__EMI_DRAM_DQM_1
+102 MX35_PAD_DQM2__EMI_DRAM_DQM_2
+103 MX35_PAD_DQM3__EMI_DRAM_DQM_3
+104 MX35_PAD_EB0__EMI_EIM_EB0_B
+105 MX35_PAD_EB1__EMI_EIM_EB1_B
+106 MX35_PAD_OE__EMI_EIM_OE
+107 MX35_PAD_CS0__EMI_EIM_CS0
+108 MX35_PAD_CS1__EMI_EIM_CS1
+109 MX35_PAD_CS1__EMI_NANDF_CE3
+110 MX35_PAD_CS2__EMI_EIM_CS2
+111 MX35_PAD_CS3__EMI_EIM_CS3
+112 MX35_PAD_CS4__EMI_EIM_CS4
+113 MX35_PAD_CS4__EMI_DTACK_B
+114 MX35_PAD_CS4__EMI_NANDF_CE1
+115 MX35_PAD_CS4__GPIO1_20
+116 MX35_PAD_CS5__EMI_EIM_CS5
+117 MX35_PAD_CS5__CSPI2_SS2
+118 MX35_PAD_CS5__CSPI1_SS2
+119 MX35_PAD_CS5__EMI_NANDF_CE2
+120 MX35_PAD_CS5__GPIO1_21
+121 MX35_PAD_NF_CE0__EMI_NANDF_CE0
+122 MX35_PAD_NF_CE0__GPIO1_22
+123 MX35_PAD_ECB__EMI_EIM_ECB
+124 MX35_PAD_LBA__EMI_EIM_LBA
+125 MX35_PAD_BCLK__EMI_EIM_BCLK
+126 MX35_PAD_RW__EMI_EIM_RW
+127 MX35_PAD_RAS__EMI_DRAM_RAS
+128 MX35_PAD_CAS__EMI_DRAM_CAS
+129 MX35_PAD_SDWE__EMI_DRAM_SDWE
+130 MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0
+131 MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1
+132 MX35_PAD_SDCLK__EMI_DRAM_SDCLK
+133 MX35_PAD_SDQS0__EMI_DRAM_SDQS_0
+134 MX35_PAD_SDQS1__EMI_DRAM_SDQS_1
+135 MX35_PAD_SDQS2__EMI_DRAM_SDQS_2
+136 MX35_PAD_SDQS3__EMI_DRAM_SDQS_3
+137 MX35_PAD_NFWE_B__EMI_NANDF_WE_B
+138 MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3
+139 MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC
+140 MX35_PAD_NFWE_B__GPIO2_18
+141 MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0
+142 MX35_PAD_NFRE_B__EMI_NANDF_RE_B
+143 MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR
+144 MX35_PAD_NFRE_B__IPU_DISPB_BCLK
+145 MX35_PAD_NFRE_B__GPIO2_19
+146 MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1
+147 MX35_PAD_NFALE__EMI_NANDF_ALE
+148 MX35_PAD_NFALE__USB_TOP_USBH2_STP
+149 MX35_PAD_NFALE__IPU_DISPB_CS0
+150 MX35_PAD_NFALE__GPIO2_20
+151 MX35_PAD_NFALE__ARM11P_TOP_TRACE_2
+152 MX35_PAD_NFCLE__EMI_NANDF_CLE
+153 MX35_PAD_NFCLE__USB_TOP_USBH2_NXT
+154 MX35_PAD_NFCLE__IPU_DISPB_PAR_RS
+155 MX35_PAD_NFCLE__GPIO2_21
+156 MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3
+157 MX35_PAD_NFWP_B__EMI_NANDF_WP_B
+158 MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7
+159 MX35_PAD_NFWP_B__IPU_DISPB_WR
+160 MX35_PAD_NFWP_B__GPIO2_22
+161 MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL
+162 MX35_PAD_NFRB__EMI_NANDF_RB
+163 MX35_PAD_NFRB__IPU_DISPB_RD
+164 MX35_PAD_NFRB__GPIO2_23
+165 MX35_PAD_NFRB__ARM11P_TOP_TRCLK
+166 MX35_PAD_D15__EMI_EIM_D_15
+167 MX35_PAD_D14__EMI_EIM_D_14
+168 MX35_PAD_D13__EMI_EIM_D_13
+169 MX35_PAD_D12__EMI_EIM_D_12
+170 MX35_PAD_D11__EMI_EIM_D_11
+171 MX35_PAD_D10__EMI_EIM_D_10
+172 MX35_PAD_D9__EMI_EIM_D_9
+173 MX35_PAD_D8__EMI_EIM_D_8
+174 MX35_PAD_D7__EMI_EIM_D_7
+175 MX35_PAD_D6__EMI_EIM_D_6
+176 MX35_PAD_D5__EMI_EIM_D_5
+177 MX35_PAD_D4__EMI_EIM_D_4
+178 MX35_PAD_D3__EMI_EIM_D_3
+179 MX35_PAD_D2__EMI_EIM_D_2
+180 MX35_PAD_D1__EMI_EIM_D_1
+181 MX35_PAD_D0__EMI_EIM_D_0
+182 MX35_PAD_CSI_D8__IPU_CSI_D_8
+183 MX35_PAD_CSI_D8__KPP_COL_0
+184 MX35_PAD_CSI_D8__GPIO1_20
+185 MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13
+186 MX35_PAD_CSI_D9__IPU_CSI_D_9
+187 MX35_PAD_CSI_D9__KPP_COL_1
+188 MX35_PAD_CSI_D9__GPIO1_21
+189 MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14
+190 MX35_PAD_CSI_D10__IPU_CSI_D_10
+191 MX35_PAD_CSI_D10__KPP_COL_2
+192 MX35_PAD_CSI_D10__GPIO1_22
+193 MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15
+194 MX35_PAD_CSI_D11__IPU_CSI_D_11
+195 MX35_PAD_CSI_D11__KPP_COL_3
+196 MX35_PAD_CSI_D11__GPIO1_23
+197 MX35_PAD_CSI_D12__IPU_CSI_D_12
+198 MX35_PAD_CSI_D12__KPP_ROW_0
+199 MX35_PAD_CSI_D12__GPIO1_24
+200 MX35_PAD_CSI_D13__IPU_CSI_D_13
+201 MX35_PAD_CSI_D13__KPP_ROW_1
+202 MX35_PAD_CSI_D13__GPIO1_25
+203 MX35_PAD_CSI_D14__IPU_CSI_D_14
+204 MX35_PAD_CSI_D14__KPP_ROW_2
+205 MX35_PAD_CSI_D14__GPIO1_26
+206 MX35_PAD_CSI_D15__IPU_CSI_D_15
+207 MX35_PAD_CSI_D15__KPP_ROW_3
+208 MX35_PAD_CSI_D15__GPIO1_27
+209 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK
+210 MX35_PAD_CSI_MCLK__GPIO1_28
+211 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC
+212 MX35_PAD_CSI_VSYNC__GPIO1_29
+213 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC
+214 MX35_PAD_CSI_HSYNC__GPIO1_30
+215 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK
+216 MX35_PAD_CSI_PIXCLK__GPIO1_31
+217 MX35_PAD_I2C1_CLK__I2C1_SCL
+218 MX35_PAD_I2C1_CLK__GPIO2_24
+219 MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK
+220 MX35_PAD_I2C1_DAT__I2C1_SDA
+221 MX35_PAD_I2C1_DAT__GPIO2_25
+222 MX35_PAD_I2C2_CLK__I2C2_SCL
+223 MX35_PAD_I2C2_CLK__CAN1_TXCAN
+224 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR
+225 MX35_PAD_I2C2_CLK__GPIO2_26
+226 MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2
+227 MX35_PAD_I2C2_DAT__I2C2_SDA
+228 MX35_PAD_I2C2_DAT__CAN1_RXCAN
+229 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC
+230 MX35_PAD_I2C2_DAT__GPIO2_27
+231 MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3
+232 MX35_PAD_STXD4__AUDMUX_AUD4_TXD
+233 MX35_PAD_STXD4__GPIO2_28
+234 MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0
+235 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD
+236 MX35_PAD_SRXD4__GPIO2_29
+237 MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1
+238 MX35_PAD_SCK4__AUDMUX_AUD4_TXC
+239 MX35_PAD_SCK4__GPIO2_30
+240 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2
+241 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS
+242 MX35_PAD_STXFS4__GPIO2_31
+243 MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3
+244 MX35_PAD_STXD5__AUDMUX_AUD5_TXD
+245 MX35_PAD_STXD5__SPDIF_SPDIF_OUT1
+246 MX35_PAD_STXD5__CSPI2_MOSI
+247 MX35_PAD_STXD5__GPIO1_0
+248 MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4
+249 MX35_PAD_SRXD5__AUDMUX_AUD5_RXD
+250 MX35_PAD_SRXD5__SPDIF_SPDIF_IN1
+251 MX35_PAD_SRXD5__CSPI2_MISO
+252 MX35_PAD_SRXD5__GPIO1_1
+253 MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5
+254 MX35_PAD_SCK5__AUDMUX_AUD5_TXC
+255 MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK
+256 MX35_PAD_SCK5__CSPI2_SCLK
+257 MX35_PAD_SCK5__GPIO1_2
+258 MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6
+259 MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS
+260 MX35_PAD_STXFS5__CSPI2_RDY
+261 MX35_PAD_STXFS5__GPIO1_3
+262 MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7
+263 MX35_PAD_SCKR__ESAI_SCKR
+264 MX35_PAD_SCKR__GPIO1_4
+265 MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10
+266 MX35_PAD_FSR__ESAI_FSR
+267 MX35_PAD_FSR__GPIO1_5
+268 MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11
+269 MX35_PAD_HCKR__ESAI_HCKR
+270 MX35_PAD_HCKR__AUDMUX_AUD5_RXFS
+271 MX35_PAD_HCKR__CSPI2_SS0
+272 MX35_PAD_HCKR__IPU_FLASH_STROBE
+273 MX35_PAD_HCKR__GPIO1_6
+274 MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12
+275 MX35_PAD_SCKT__ESAI_SCKT
+276 MX35_PAD_SCKT__GPIO1_7
+277 MX35_PAD_SCKT__IPU_CSI_D_0
+278 MX35_PAD_SCKT__KPP_ROW_2
+279 MX35_PAD_FST__ESAI_FST
+280 MX35_PAD_FST__GPIO1_8
+281 MX35_PAD_FST__IPU_CSI_D_1
+282 MX35_PAD_FST__KPP_ROW_3
+283 MX35_PAD_HCKT__ESAI_HCKT
+284 MX35_PAD_HCKT__AUDMUX_AUD5_RXC
+285 MX35_PAD_HCKT__GPIO1_9
+286 MX35_PAD_HCKT__IPU_CSI_D_2
+287 MX35_PAD_HCKT__KPP_COL_3
+288 MX35_PAD_TX5_RX0__ESAI_TX5_RX0
+289 MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC
+290 MX35_PAD_TX5_RX0__CSPI2_SS2
+291 MX35_PAD_TX5_RX0__CAN2_TXCAN
+292 MX35_PAD_TX5_RX0__UART2_DTR
+293 MX35_PAD_TX5_RX0__GPIO1_10
+294 MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0
+295 MX35_PAD_TX4_RX1__ESAI_TX4_RX1
+296 MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS
+297 MX35_PAD_TX4_RX1__CSPI2_SS3
+298 MX35_PAD_TX4_RX1__CAN2_RXCAN
+299 MX35_PAD_TX4_RX1__UART2_DSR
+300 MX35_PAD_TX4_RX1__GPIO1_11
+301 MX35_PAD_TX4_RX1__IPU_CSI_D_3
+302 MX35_PAD_TX4_RX1__KPP_ROW_0
+303 MX35_PAD_TX3_RX2__ESAI_TX3_RX2
+304 MX35_PAD_TX3_RX2__I2C3_SCL
+305 MX35_PAD_TX3_RX2__EMI_NANDF_CE1
+306 MX35_PAD_TX3_RX2__GPIO1_12
+307 MX35_PAD_TX3_RX2__IPU_CSI_D_4
+308 MX35_PAD_TX3_RX2__KPP_ROW_1
+309 MX35_PAD_TX2_RX3__ESAI_TX2_RX3
+310 MX35_PAD_TX2_RX3__I2C3_SDA
+311 MX35_PAD_TX2_RX3__EMI_NANDF_CE2
+312 MX35_PAD_TX2_RX3__GPIO1_13
+313 MX35_PAD_TX2_RX3__IPU_CSI_D_5
+314 MX35_PAD_TX2_RX3__KPP_COL_0
+315 MX35_PAD_TX1__ESAI_TX1
+316 MX35_PAD_TX1__CCM_PMIC_RDY
+317 MX35_PAD_TX1__CSPI1_SS2
+318 MX35_PAD_TX1__EMI_NANDF_CE3
+319 MX35_PAD_TX1__UART2_RI
+320 MX35_PAD_TX1__GPIO1_14
+321 MX35_PAD_TX1__IPU_CSI_D_6
+322 MX35_PAD_TX1__KPP_COL_1
+323 MX35_PAD_TX0__ESAI_TX0
+324 MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK
+325 MX35_PAD_TX0__CSPI1_SS3
+326 MX35_PAD_TX0__EMI_DTACK_B
+327 MX35_PAD_TX0__UART2_DCD
+328 MX35_PAD_TX0__GPIO1_15
+329 MX35_PAD_TX0__IPU_CSI_D_7
+330 MX35_PAD_TX0__KPP_COL_2
+331 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI
+332 MX35_PAD_CSPI1_MOSI__GPIO1_16
+333 MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2
+334 MX35_PAD_CSPI1_MISO__CSPI1_MISO
+335 MX35_PAD_CSPI1_MISO__GPIO1_17
+336 MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3
+337 MX35_PAD_CSPI1_SS0__CSPI1_SS0
+338 MX35_PAD_CSPI1_SS0__OWIRE_LINE
+339 MX35_PAD_CSPI1_SS0__CSPI2_SS3
+340 MX35_PAD_CSPI1_SS0__GPIO1_18
+341 MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4
+342 MX35_PAD_CSPI1_SS1__CSPI1_SS1
+343 MX35_PAD_CSPI1_SS1__PWM_PWMO
+344 MX35_PAD_CSPI1_SS1__CCM_CLK32K
+345 MX35_PAD_CSPI1_SS1__GPIO1_19
+346 MX35_PAD_CSPI1_SS1__IPU_DIAGB_29
+347 MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5
+348 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK
+349 MX35_PAD_CSPI1_SCLK__GPIO3_4
+350 MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30
+351 MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1
+352 MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY
+353 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5
+354 MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31
+355 MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2
+356 MX35_PAD_RXD1__UART1_RXD_MUX
+357 MX35_PAD_RXD1__CSPI2_MOSI
+358 MX35_PAD_RXD1__KPP_COL_4
+359 MX35_PAD_RXD1__GPIO3_6
+360 MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16
+361 MX35_PAD_TXD1__UART1_TXD_MUX
+362 MX35_PAD_TXD1__CSPI2_MISO
+363 MX35_PAD_TXD1__KPP_COL_5
+364 MX35_PAD_TXD1__GPIO3_7
+365 MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17
+366 MX35_PAD_RTS1__UART1_RTS
+367 MX35_PAD_RTS1__CSPI2_SCLK
+368 MX35_PAD_RTS1__I2C3_SCL
+369 MX35_PAD_RTS1__IPU_CSI_D_0
+370 MX35_PAD_RTS1__KPP_COL_6
+371 MX35_PAD_RTS1__GPIO3_8
+372 MX35_PAD_RTS1__EMI_NANDF_CE1
+373 MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18
+374 MX35_PAD_CTS1__UART1_CTS
+375 MX35_PAD_CTS1__CSPI2_RDY
+376 MX35_PAD_CTS1__I2C3_SDA
+377 MX35_PAD_CTS1__IPU_CSI_D_1
+378 MX35_PAD_CTS1__KPP_COL_7
+379 MX35_PAD_CTS1__GPIO3_9
+380 MX35_PAD_CTS1__EMI_NANDF_CE2
+381 MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19
+382 MX35_PAD_RXD2__UART2_RXD_MUX
+383 MX35_PAD_RXD2__KPP_ROW_4
+384 MX35_PAD_RXD2__GPIO3_10
+385 MX35_PAD_TXD2__UART2_TXD_MUX
+386 MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK
+387 MX35_PAD_TXD2__KPP_ROW_5
+388 MX35_PAD_TXD2__GPIO3_11
+389 MX35_PAD_RTS2__UART2_RTS
+390 MX35_PAD_RTS2__SPDIF_SPDIF_IN1
+391 MX35_PAD_RTS2__CAN2_RXCAN
+392 MX35_PAD_RTS2__IPU_CSI_D_2
+393 MX35_PAD_RTS2__KPP_ROW_6
+394 MX35_PAD_RTS2__GPIO3_12
+395 MX35_PAD_RTS2__AUDMUX_AUD5_RXC
+396 MX35_PAD_RTS2__UART3_RXD_MUX
+397 MX35_PAD_CTS2__UART2_CTS
+398 MX35_PAD_CTS2__SPDIF_SPDIF_OUT1
+399 MX35_PAD_CTS2__CAN2_TXCAN
+400 MX35_PAD_CTS2__IPU_CSI_D_3
+401 MX35_PAD_CTS2__KPP_ROW_7
+402 MX35_PAD_CTS2__GPIO3_13
+403 MX35_PAD_CTS2__AUDMUX_AUD5_RXFS
+404 MX35_PAD_CTS2__UART3_TXD_MUX
+405 MX35_PAD_RTCK__ARM11P_TOP_RTCK
+406 MX35_PAD_TCK__SJC_TCK
+407 MX35_PAD_TMS__SJC_TMS
+408 MX35_PAD_TDI__SJC_TDI
+409 MX35_PAD_TDO__SJC_TDO
+410 MX35_PAD_TRSTB__SJC_TRSTB
+411 MX35_PAD_DE_B__SJC_DE_B
+412 MX35_PAD_SJC_MOD__SJC_MOD
+413 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR
+414 MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR
+415 MX35_PAD_USBOTG_PWR__GPIO3_14
+416 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC
+417 MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC
+418 MX35_PAD_USBOTG_OC__GPIO3_15
+419 MX35_PAD_LD0__IPU_DISPB_DAT_0
+420 MX35_PAD_LD0__GPIO2_0
+421 MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0
+422 MX35_PAD_LD1__IPU_DISPB_DAT_1
+423 MX35_PAD_LD1__GPIO2_1
+424 MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1
+425 MX35_PAD_LD2__IPU_DISPB_DAT_2
+426 MX35_PAD_LD2__GPIO2_2
+427 MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2
+428 MX35_PAD_LD3__IPU_DISPB_DAT_3
+429 MX35_PAD_LD3__GPIO2_3
+430 MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3
+431 MX35_PAD_LD4__IPU_DISPB_DAT_4
+432 MX35_PAD_LD4__GPIO2_4
+433 MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4
+434 MX35_PAD_LD5__IPU_DISPB_DAT_5
+435 MX35_PAD_LD5__GPIO2_5
+436 MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5
+437 MX35_PAD_LD6__IPU_DISPB_DAT_6
+438 MX35_PAD_LD6__GPIO2_6
+439 MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6
+440 MX35_PAD_LD7__IPU_DISPB_DAT_7
+441 MX35_PAD_LD7__GPIO2_7
+442 MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7
+443 MX35_PAD_LD8__IPU_DISPB_DAT_8
+444 MX35_PAD_LD8__GPIO2_8
+445 MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8
+446 MX35_PAD_LD9__IPU_DISPB_DAT_9
+447 MX35_PAD_LD9__GPIO2_9
+448 MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9
+449 MX35_PAD_LD10__IPU_DISPB_DAT_10
+450 MX35_PAD_LD10__GPIO2_10
+451 MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10
+452 MX35_PAD_LD11__IPU_DISPB_DAT_11
+453 MX35_PAD_LD11__GPIO2_11
+454 MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11
+455 MX35_PAD_LD11__ARM11P_TOP_TRACE_4
+456 MX35_PAD_LD12__IPU_DISPB_DAT_12
+457 MX35_PAD_LD12__GPIO2_12
+458 MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12
+459 MX35_PAD_LD12__ARM11P_TOP_TRACE_5
+460 MX35_PAD_LD13__IPU_DISPB_DAT_13
+461 MX35_PAD_LD13__GPIO2_13
+462 MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13
+463 MX35_PAD_LD13__ARM11P_TOP_TRACE_6
+464 MX35_PAD_LD14__IPU_DISPB_DAT_14
+465 MX35_PAD_LD14__GPIO2_14
+466 MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0
+467 MX35_PAD_LD14__ARM11P_TOP_TRACE_7
+468 MX35_PAD_LD15__IPU_DISPB_DAT_15
+469 MX35_PAD_LD15__GPIO2_15
+470 MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1
+471 MX35_PAD_LD15__ARM11P_TOP_TRACE_8
+472 MX35_PAD_LD16__IPU_DISPB_DAT_16
+473 MX35_PAD_LD16__IPU_DISPB_D12_VSYNC
+474 MX35_PAD_LD16__GPIO2_16
+475 MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2
+476 MX35_PAD_LD16__ARM11P_TOP_TRACE_9
+477 MX35_PAD_LD17__IPU_DISPB_DAT_17
+478 MX35_PAD_LD17__IPU_DISPB_CS2
+479 MX35_PAD_LD17__GPIO2_17
+480 MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3
+481 MX35_PAD_LD17__ARM11P_TOP_TRACE_10
+482 MX35_PAD_LD18__IPU_DISPB_DAT_18
+483 MX35_PAD_LD18__IPU_DISPB_D0_VSYNC
+484 MX35_PAD_LD18__IPU_DISPB_D12_VSYNC
+485 MX35_PAD_LD18__ESDHC3_CMD
+486 MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3
+487 MX35_PAD_LD18__GPIO3_24
+488 MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4
+489 MX35_PAD_LD18__ARM11P_TOP_TRACE_11
+490 MX35_PAD_LD19__IPU_DISPB_DAT_19
+491 MX35_PAD_LD19__IPU_DISPB_BCLK
+492 MX35_PAD_LD19__IPU_DISPB_CS1
+493 MX35_PAD_LD19__ESDHC3_CLK
+494 MX35_PAD_LD19__USB_TOP_USBOTG_DIR
+495 MX35_PAD_LD19__GPIO3_25
+496 MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5
+497 MX35_PAD_LD19__ARM11P_TOP_TRACE_12
+498 MX35_PAD_LD20__IPU_DISPB_DAT_20
+499 MX35_PAD_LD20__IPU_DISPB_CS0
+500 MX35_PAD_LD20__IPU_DISPB_SD_CLK
+501 MX35_PAD_LD20__ESDHC3_DAT0
+502 MX35_PAD_LD20__GPIO3_26
+503 MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3
+504 MX35_PAD_LD20__ARM11P_TOP_TRACE_13
+505 MX35_PAD_LD21__IPU_DISPB_DAT_21
+506 MX35_PAD_LD21__IPU_DISPB_PAR_RS
+507 MX35_PAD_LD21__IPU_DISPB_SER_RS
+508 MX35_PAD_LD21__ESDHC3_DAT1
+509 MX35_PAD_LD21__USB_TOP_USBOTG_STP
+510 MX35_PAD_LD21__GPIO3_27
+511 MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL
+512 MX35_PAD_LD21__ARM11P_TOP_TRACE_14
+513 MX35_PAD_LD22__IPU_DISPB_DAT_22
+514 MX35_PAD_LD22__IPU_DISPB_WR
+515 MX35_PAD_LD22__IPU_DISPB_SD_D_I
+516 MX35_PAD_LD22__ESDHC3_DAT2
+517 MX35_PAD_LD22__USB_TOP_USBOTG_NXT
+518 MX35_PAD_LD22__GPIO3_28
+519 MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR
+520 MX35_PAD_LD22__ARM11P_TOP_TRCTL
+521 MX35_PAD_LD23__IPU_DISPB_DAT_23
+522 MX35_PAD_LD23__IPU_DISPB_RD
+523 MX35_PAD_LD23__IPU_DISPB_SD_D_IO
+524 MX35_PAD_LD23__ESDHC3_DAT3
+525 MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7
+526 MX35_PAD_LD23__GPIO3_29
+527 MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS
+528 MX35_PAD_LD23__ARM11P_TOP_TRCLK
+529 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC
+530 MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO
+531 MX35_PAD_D3_HSYNC__GPIO3_30
+532 MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE
+533 MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15
+534 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK
+535 MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK
+536 MX35_PAD_D3_FPSHIFT__GPIO3_31
+537 MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0
+538 MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16
+539 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY
+540 MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O
+541 MX35_PAD_D3_DRDY__GPIO1_0
+542 MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1
+543 MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17
+544 MX35_PAD_CONTRAST__IPU_DISPB_CONTR
+545 MX35_PAD_CONTRAST__GPIO1_1
+546 MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2
+547 MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18
+548 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC
+549 MX35_PAD_D3_VSYNC__IPU_DISPB_CS1
+550 MX35_PAD_D3_VSYNC__GPIO1_2
+551 MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD
+552 MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19
+553 MX35_PAD_D3_REV__IPU_DISPB_D3_REV
+554 MX35_PAD_D3_REV__IPU_DISPB_SER_RS
+555 MX35_PAD_D3_REV__GPIO1_3
+556 MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB
+557 MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20
+558 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS
+559 MX35_PAD_D3_CLS__IPU_DISPB_CS2
+560 MX35_PAD_D3_CLS__GPIO1_4
+561 MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0
+562 MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21
+563 MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
+564 MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC
+565 MX35_PAD_D3_SPL__GPIO1_5
+566 MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1
+567 MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22
+568 MX35_PAD_SD1_CMD__ESDHC1_CMD
+569 MX35_PAD_SD1_CMD__MSHC_SCLK
+570 MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC
+571 MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4
+572 MX35_PAD_SD1_CMD__GPIO1_6
+573 MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL
+574 MX35_PAD_SD1_CLK__ESDHC1_CLK
+575 MX35_PAD_SD1_CLK__MSHC_BS
+576 MX35_PAD_SD1_CLK__IPU_DISPB_BCLK
+577 MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5
+578 MX35_PAD_SD1_CLK__GPIO1_7
+579 MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK
+580 MX35_PAD_SD1_DATA0__ESDHC1_DAT0
+581 MX35_PAD_SD1_DATA0__MSHC_DATA_0
+582 MX35_PAD_SD1_DATA0__IPU_DISPB_CS0
+583 MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6
+584 MX35_PAD_SD1_DATA0__GPIO1_8
+585 MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23
+586 MX35_PAD_SD1_DATA1__ESDHC1_DAT1
+587 MX35_PAD_SD1_DATA1__MSHC_DATA_1
+588 MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS
+589 MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0
+590 MX35_PAD_SD1_DATA1__GPIO1_9
+591 MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24
+592 MX35_PAD_SD1_DATA2__ESDHC1_DAT2
+593 MX35_PAD_SD1_DATA2__MSHC_DATA_2
+594 MX35_PAD_SD1_DATA2__IPU_DISPB_WR
+595 MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1
+596 MX35_PAD_SD1_DATA2__GPIO1_10
+597 MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25
+598 MX35_PAD_SD1_DATA3__ESDHC1_DAT3
+599 MX35_PAD_SD1_DATA3__MSHC_DATA_3
+600 MX35_PAD_SD1_DATA3__IPU_DISPB_RD
+601 MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2
+602 MX35_PAD_SD1_DATA3__GPIO1_11
+603 MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26
+604 MX35_PAD_SD2_CMD__ESDHC2_CMD
+605 MX35_PAD_SD2_CMD__I2C3_SCL
+606 MX35_PAD_SD2_CMD__ESDHC1_DAT4
+607 MX35_PAD_SD2_CMD__IPU_CSI_D_2
+608 MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4
+609 MX35_PAD_SD2_CMD__GPIO2_0
+610 MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1
+611 MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC
+612 MX35_PAD_SD2_CLK__ESDHC2_CLK
+613 MX35_PAD_SD2_CLK__I2C3_SDA
+614 MX35_PAD_SD2_CLK__ESDHC1_DAT5
+615 MX35_PAD_SD2_CLK__IPU_CSI_D_3
+616 MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5
+617 MX35_PAD_SD2_CLK__GPIO2_1
+618 MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1
+619 MX35_PAD_SD2_CLK__IPU_DISPB_CS2
+620 MX35_PAD_SD2_DATA0__ESDHC2_DAT0
+621 MX35_PAD_SD2_DATA0__UART3_RXD_MUX
+622 MX35_PAD_SD2_DATA0__ESDHC1_DAT6
+623 MX35_PAD_SD2_DATA0__IPU_CSI_D_4
+624 MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6
+625 MX35_PAD_SD2_DATA0__GPIO2_2
+626 MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK
+627 MX35_PAD_SD2_DATA1__ESDHC2_DAT1
+628 MX35_PAD_SD2_DATA1__UART3_TXD_MUX
+629 MX35_PAD_SD2_DATA1__ESDHC1_DAT7
+630 MX35_PAD_SD2_DATA1__IPU_CSI_D_5
+631 MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0
+632 MX35_PAD_SD2_DATA1__GPIO2_3
+633 MX35_PAD_SD2_DATA2__ESDHC2_DAT2
+634 MX35_PAD_SD2_DATA2__UART3_RTS
+635 MX35_PAD_SD2_DATA2__CAN1_RXCAN
+636 MX35_PAD_SD2_DATA2__IPU_CSI_D_6
+637 MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1
+638 MX35_PAD_SD2_DATA2__GPIO2_4
+639 MX35_PAD_SD2_DATA3__ESDHC2_DAT3
+640 MX35_PAD_SD2_DATA3__UART3_CTS
+641 MX35_PAD_SD2_DATA3__CAN1_TXCAN
+642 MX35_PAD_SD2_DATA3__IPU_CSI_D_7
+643 MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2
+644 MX35_PAD_SD2_DATA3__GPIO2_5
+645 MX35_PAD_ATA_CS0__ATA_CS0
+646 MX35_PAD_ATA_CS0__CSPI1_SS3
+647 MX35_PAD_ATA_CS0__IPU_DISPB_CS1
+648 MX35_PAD_ATA_CS0__GPIO2_6
+649 MX35_PAD_ATA_CS0__IPU_DIAGB_0
+650 MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0
+651 MX35_PAD_ATA_CS1__ATA_CS1
+652 MX35_PAD_ATA_CS1__IPU_DISPB_CS2
+653 MX35_PAD_ATA_CS1__CSPI2_SS0
+654 MX35_PAD_ATA_CS1__GPIO2_7
+655 MX35_PAD_ATA_CS1__IPU_DIAGB_1
+656 MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1
+657 MX35_PAD_ATA_DIOR__ATA_DIOR
+658 MX35_PAD_ATA_DIOR__ESDHC3_DAT0
+659 MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR
+660 MX35_PAD_ATA_DIOR__IPU_DISPB_BE0
+661 MX35_PAD_ATA_DIOR__CSPI2_SS1
+662 MX35_PAD_ATA_DIOR__GPIO2_8
+663 MX35_PAD_ATA_DIOR__IPU_DIAGB_2
+664 MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2
+665 MX35_PAD_ATA_DIOW__ATA_DIOW
+666 MX35_PAD_ATA_DIOW__ESDHC3_DAT1
+667 MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP
+668 MX35_PAD_ATA_DIOW__IPU_DISPB_BE1
+669 MX35_PAD_ATA_DIOW__CSPI2_MOSI
+670 MX35_PAD_ATA_DIOW__GPIO2_9
+671 MX35_PAD_ATA_DIOW__IPU_DIAGB_3
+672 MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3
+673 MX35_PAD_ATA_DMACK__ATA_DMACK
+674 MX35_PAD_ATA_DMACK__ESDHC3_DAT2
+675 MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT
+676 MX35_PAD_ATA_DMACK__CSPI2_MISO
+677 MX35_PAD_ATA_DMACK__GPIO2_10
+678 MX35_PAD_ATA_DMACK__IPU_DIAGB_4
+679 MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0
+680 MX35_PAD_ATA_RESET_B__ATA_RESET_B
+681 MX35_PAD_ATA_RESET_B__ESDHC3_DAT3
+682 MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0
+683 MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O
+684 MX35_PAD_ATA_RESET_B__CSPI2_RDY
+685 MX35_PAD_ATA_RESET_B__GPIO2_11
+686 MX35_PAD_ATA_RESET_B__IPU_DIAGB_5
+687 MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1
+688 MX35_PAD_ATA_IORDY__ATA_IORDY
+689 MX35_PAD_ATA_IORDY__ESDHC3_DAT4
+690 MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1
+691 MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO
+692 MX35_PAD_ATA_IORDY__ESDHC2_DAT4
+693 MX35_PAD_ATA_IORDY__GPIO2_12
+694 MX35_PAD_ATA_IORDY__IPU_DIAGB_6
+695 MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2
+696 MX35_PAD_ATA_DATA0__ATA_DATA_0
+697 MX35_PAD_ATA_DATA0__ESDHC3_DAT5
+698 MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2
+699 MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC
+700 MX35_PAD_ATA_DATA0__ESDHC2_DAT5
+701 MX35_PAD_ATA_DATA0__GPIO2_13
+702 MX35_PAD_ATA_DATA0__IPU_DIAGB_7
+703 MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3
+704 MX35_PAD_ATA_DATA1__ATA_DATA_1
+705 MX35_PAD_ATA_DATA1__ESDHC3_DAT6
+706 MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3
+707 MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK
+708 MX35_PAD_ATA_DATA1__ESDHC2_DAT6
+709 MX35_PAD_ATA_DATA1__GPIO2_14
+710 MX35_PAD_ATA_DATA1__IPU_DIAGB_8
+711 MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27
+712 MX35_PAD_ATA_DATA2__ATA_DATA_2
+713 MX35_PAD_ATA_DATA2__ESDHC3_DAT7
+714 MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4
+715 MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS
+716 MX35_PAD_ATA_DATA2__ESDHC2_DAT7
+717 MX35_PAD_ATA_DATA2__GPIO2_15
+718 MX35_PAD_ATA_DATA2__IPU_DIAGB_9
+719 MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28
+720 MX35_PAD_ATA_DATA3__ATA_DATA_3
+721 MX35_PAD_ATA_DATA3__ESDHC3_CLK
+722 MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5
+723 MX35_PAD_ATA_DATA3__CSPI2_SCLK
+724 MX35_PAD_ATA_DATA3__GPIO2_16
+725 MX35_PAD_ATA_DATA3__IPU_DIAGB_10
+726 MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29
+727 MX35_PAD_ATA_DATA4__ATA_DATA_4
+728 MX35_PAD_ATA_DATA4__ESDHC3_CMD
+729 MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6
+730 MX35_PAD_ATA_DATA4__GPIO2_17
+731 MX35_PAD_ATA_DATA4__IPU_DIAGB_11
+732 MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30
+733 MX35_PAD_ATA_DATA5__ATA_DATA_5
+734 MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7
+735 MX35_PAD_ATA_DATA5__GPIO2_18
+736 MX35_PAD_ATA_DATA5__IPU_DIAGB_12
+737 MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31
+738 MX35_PAD_ATA_DATA6__ATA_DATA_6
+739 MX35_PAD_ATA_DATA6__CAN1_TXCAN
+740 MX35_PAD_ATA_DATA6__UART1_DTR
+741 MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD
+742 MX35_PAD_ATA_DATA6__GPIO2_19
+743 MX35_PAD_ATA_DATA6__IPU_DIAGB_13
+744 MX35_PAD_ATA_DATA7__ATA_DATA_7
+745 MX35_PAD_ATA_DATA7__CAN1_RXCAN
+746 MX35_PAD_ATA_DATA7__UART1_DSR
+747 MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD
+748 MX35_PAD_ATA_DATA7__GPIO2_20
+749 MX35_PAD_ATA_DATA7__IPU_DIAGB_14
+750 MX35_PAD_ATA_DATA8__ATA_DATA_8
+751 MX35_PAD_ATA_DATA8__UART3_RTS
+752 MX35_PAD_ATA_DATA8__UART1_RI
+753 MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC
+754 MX35_PAD_ATA_DATA8__GPIO2_21
+755 MX35_PAD_ATA_DATA8__IPU_DIAGB_15
+756 MX35_PAD_ATA_DATA9__ATA_DATA_9
+757 MX35_PAD_ATA_DATA9__UART3_CTS
+758 MX35_PAD_ATA_DATA9__UART1_DCD
+759 MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS
+760 MX35_PAD_ATA_DATA9__GPIO2_22
+761 MX35_PAD_ATA_DATA9__IPU_DIAGB_16
+762 MX35_PAD_ATA_DATA10__ATA_DATA_10
+763 MX35_PAD_ATA_DATA10__UART3_RXD_MUX
+764 MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC
+765 MX35_PAD_ATA_DATA10__GPIO2_23
+766 MX35_PAD_ATA_DATA10__IPU_DIAGB_17
+767 MX35_PAD_ATA_DATA11__ATA_DATA_11
+768 MX35_PAD_ATA_DATA11__UART3_TXD_MUX
+769 MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS
+770 MX35_PAD_ATA_DATA11__GPIO2_24
+771 MX35_PAD_ATA_DATA11__IPU_DIAGB_18
+772 MX35_PAD_ATA_DATA12__ATA_DATA_12
+773 MX35_PAD_ATA_DATA12__I2C3_SCL
+774 MX35_PAD_ATA_DATA12__GPIO2_25
+775 MX35_PAD_ATA_DATA12__IPU_DIAGB_19
+776 MX35_PAD_ATA_DATA13__ATA_DATA_13
+777 MX35_PAD_ATA_DATA13__I2C3_SDA
+778 MX35_PAD_ATA_DATA13__GPIO2_26
+779 MX35_PAD_ATA_DATA13__IPU_DIAGB_20
+780 MX35_PAD_ATA_DATA14__ATA_DATA_14
+781 MX35_PAD_ATA_DATA14__IPU_CSI_D_0
+782 MX35_PAD_ATA_DATA14__KPP_ROW_0
+783 MX35_PAD_ATA_DATA14__GPIO2_27
+784 MX35_PAD_ATA_DATA14__IPU_DIAGB_21
+785 MX35_PAD_ATA_DATA15__ATA_DATA_15
+786 MX35_PAD_ATA_DATA15__IPU_CSI_D_1
+787 MX35_PAD_ATA_DATA15__KPP_ROW_1
+788 MX35_PAD_ATA_DATA15__GPIO2_28
+789 MX35_PAD_ATA_DATA15__IPU_DIAGB_22
+790 MX35_PAD_ATA_INTRQ__ATA_INTRQ
+791 MX35_PAD_ATA_INTRQ__IPU_CSI_D_2
+792 MX35_PAD_ATA_INTRQ__KPP_ROW_2
+793 MX35_PAD_ATA_INTRQ__GPIO2_29
+794 MX35_PAD_ATA_INTRQ__IPU_DIAGB_23
+795 MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN
+796 MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3
+797 MX35_PAD_ATA_BUFF_EN__KPP_ROW_3
+798 MX35_PAD_ATA_BUFF_EN__GPIO2_30
+799 MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24
+800 MX35_PAD_ATA_DMARQ__ATA_DMARQ
+801 MX35_PAD_ATA_DMARQ__IPU_CSI_D_4
+802 MX35_PAD_ATA_DMARQ__KPP_COL_0
+803 MX35_PAD_ATA_DMARQ__GPIO2_31
+804 MX35_PAD_ATA_DMARQ__IPU_DIAGB_25
+805 MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4
+806 MX35_PAD_ATA_DA0__ATA_DA_0
+807 MX35_PAD_ATA_DA0__IPU_CSI_D_5
+808 MX35_PAD_ATA_DA0__KPP_COL_1
+809 MX35_PAD_ATA_DA0__GPIO3_0
+810 MX35_PAD_ATA_DA0__IPU_DIAGB_26
+811 MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5
+812 MX35_PAD_ATA_DA1__ATA_DA_1
+813 MX35_PAD_ATA_DA1__IPU_CSI_D_6
+814 MX35_PAD_ATA_DA1__KPP_COL_2
+815 MX35_PAD_ATA_DA1__GPIO3_1
+816 MX35_PAD_ATA_DA1__IPU_DIAGB_27
+817 MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6
+818 MX35_PAD_ATA_DA2__ATA_DA_2
+819 MX35_PAD_ATA_DA2__IPU_CSI_D_7
+820 MX35_PAD_ATA_DA2__KPP_COL_3
+821 MX35_PAD_ATA_DA2__GPIO3_2
+822 MX35_PAD_ATA_DA2__IPU_DIAGB_28
+823 MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7
+824 MX35_PAD_MLB_CLK__MLB_MLBCLK
+825 MX35_PAD_MLB_CLK__GPIO3_3
+826 MX35_PAD_MLB_DAT__MLB_MLBDAT
+827 MX35_PAD_MLB_DAT__GPIO3_4
+828 MX35_PAD_MLB_SIG__MLB_MLBSIG
+829 MX35_PAD_MLB_SIG__GPIO3_5
+830 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK
+831 MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4
+832 MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX
+833 MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR
+834 MX35_PAD_FEC_TX_CLK__CSPI2_MOSI
+835 MX35_PAD_FEC_TX_CLK__GPIO3_6
+836 MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC
+837 MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0
+838 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK
+839 MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5
+840 MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX
+841 MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP
+842 MX35_PAD_FEC_RX_CLK__CSPI2_MISO
+843 MX35_PAD_FEC_RX_CLK__GPIO3_7
+844 MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I
+845 MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1
+846 MX35_PAD_FEC_RX_DV__FEC_RX_DV
+847 MX35_PAD_FEC_RX_DV__ESDHC1_DAT6
+848 MX35_PAD_FEC_RX_DV__UART3_RTS
+849 MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT
+850 MX35_PAD_FEC_RX_DV__CSPI2_SCLK
+851 MX35_PAD_FEC_RX_DV__GPIO3_8
+852 MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK
+853 MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2
+854 MX35_PAD_FEC_COL__FEC_COL
+855 MX35_PAD_FEC_COL__ESDHC1_DAT7
+856 MX35_PAD_FEC_COL__UART3_CTS
+857 MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0
+858 MX35_PAD_FEC_COL__CSPI2_RDY
+859 MX35_PAD_FEC_COL__GPIO3_9
+860 MX35_PAD_FEC_COL__IPU_DISPB_SER_RS
+861 MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3
+862 MX35_PAD_FEC_RDATA0__FEC_RDATA_0
+863 MX35_PAD_FEC_RDATA0__PWM_PWMO
+864 MX35_PAD_FEC_RDATA0__UART3_DTR
+865 MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1
+866 MX35_PAD_FEC_RDATA0__CSPI2_SS0
+867 MX35_PAD_FEC_RDATA0__GPIO3_10
+868 MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1
+869 MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4
+870 MX35_PAD_FEC_TDATA0__FEC_TDATA_0
+871 MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1
+872 MX35_PAD_FEC_TDATA0__UART3_DSR
+873 MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2
+874 MX35_PAD_FEC_TDATA0__CSPI2_SS1
+875 MX35_PAD_FEC_TDATA0__GPIO3_11
+876 MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0
+877 MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5
+878 MX35_PAD_FEC_TX_EN__FEC_TX_EN
+879 MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1
+880 MX35_PAD_FEC_TX_EN__UART3_RI
+881 MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3
+882 MX35_PAD_FEC_TX_EN__GPIO3_12
+883 MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS
+884 MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6
+885 MX35_PAD_FEC_MDC__FEC_MDC
+886 MX35_PAD_FEC_MDC__CAN2_TXCAN
+887 MX35_PAD_FEC_MDC__UART3_DCD
+888 MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4
+889 MX35_PAD_FEC_MDC__GPIO3_13
+890 MX35_PAD_FEC_MDC__IPU_DISPB_WR
+891 MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7
+892 MX35_PAD_FEC_MDIO__FEC_MDIO
+893 MX35_PAD_FEC_MDIO__CAN2_RXCAN
+894 MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5
+895 MX35_PAD_FEC_MDIO__GPIO3_14
+896 MX35_PAD_FEC_MDIO__IPU_DISPB_RD
+897 MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8
+898 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR
+899 MX35_PAD_FEC_TX_ERR__OWIRE_LINE
+900 MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK
+901 MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6
+902 MX35_PAD_FEC_TX_ERR__GPIO3_15
+903 MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC
+904 MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9
+905 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR
+906 MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0
+907 MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7
+908 MX35_PAD_FEC_RX_ERR__KPP_COL_4
+909 MX35_PAD_FEC_RX_ERR__GPIO3_16
+910 MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO
+911 MX35_PAD_FEC_CRS__FEC_CRS
+912 MX35_PAD_FEC_CRS__IPU_CSI_D_1
+913 MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR
+914 MX35_PAD_FEC_CRS__KPP_COL_5
+915 MX35_PAD_FEC_CRS__GPIO3_17
+916 MX35_PAD_FEC_CRS__IPU_FLASH_STROBE
+917 MX35_PAD_FEC_RDATA1__FEC_RDATA_1
+918 MX35_PAD_FEC_RDATA1__IPU_CSI_D_2
+919 MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC
+920 MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC
+921 MX35_PAD_FEC_RDATA1__KPP_COL_6
+922 MX35_PAD_FEC_RDATA1__GPIO3_18
+923 MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0
+924 MX35_PAD_FEC_TDATA1__FEC_TDATA_1
+925 MX35_PAD_FEC_TDATA1__IPU_CSI_D_3
+926 MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS
+927 MX35_PAD_FEC_TDATA1__KPP_COL_7
+928 MX35_PAD_FEC_TDATA1__GPIO3_19
+929 MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1
+930 MX35_PAD_FEC_RDATA2__FEC_RDATA_2
+931 MX35_PAD_FEC_RDATA2__IPU_CSI_D_4
+932 MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD
+933 MX35_PAD_FEC_RDATA2__KPP_ROW_4
+934 MX35_PAD_FEC_RDATA2__GPIO3_20
+935 MX35_PAD_FEC_TDATA2__FEC_TDATA_2
+936 MX35_PAD_FEC_TDATA2__IPU_CSI_D_5
+937 MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD
+938 MX35_PAD_FEC_TDATA2__KPP_ROW_5
+939 MX35_PAD_FEC_TDATA2__GPIO3_21
+940 MX35_PAD_FEC_RDATA3__FEC_RDATA_3
+941 MX35_PAD_FEC_RDATA3__IPU_CSI_D_6
+942 MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC
+943 MX35_PAD_FEC_RDATA3__KPP_ROW_6
+944 MX35_PAD_FEC_RDATA3__GPIO3_22
+945 MX35_PAD_FEC_TDATA3__FEC_TDATA_3
+946 MX35_PAD_FEC_TDATA3__IPU_CSI_D_7
+947 MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS
+948 MX35_PAD_FEC_TDATA3__KPP_ROW_7
+949 MX35_PAD_FEC_TDATA3__GPIO3_23
+950 MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK
+951 MX35_PAD_TEST_MODE__TCU_TEST_MODE

diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index e40f4b4e1977c73d1f6984c705c1065878ad4ad4..1479aca2374441976c14668b7bc7e523fbb2211f 100644 (file)
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -840,9 +840,9 @@ static unsigned long i2c_pin_configs[] = {
 
 static struct pinctrl_map __initdata mapping[] = {
        PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
-       PIN_MAP_MUX_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
-       PIN_MAP_MUX_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
-       PIN_MAP_MUX_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
+       PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
+       PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
+       PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
 };
 
 Finally, some devices expect the mapping table to contain certain specific

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 36a9fd66bb8088b04ad3f7c1c6332c85596dbdef..c0c457e779b299437a148bb91a9d6ee26d2e6f5f 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -958,6 +958,7 @@ config ARCH_NOMADIK
        select COMMON_CLK
        select GENERIC_CLOCKEVENTS
        select PINCTRL
+       select PINCTRL_STN8815
        select MIGHT_HAVE_CACHE_L2X0
        select ARCH_REQUIRE_GPIOLIB
        help

diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index f4535a7dadf537d7ffc0a691598db24103ba4ab1..66862fb981f953107d8409fd1b3418e8fdb5f6fc 100644 (file)
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -23,6 +23,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/hardware/vic.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
@@ -33,6 +34,7 @@
 
 #include <plat/gpio-nomadik.h>
 #include <plat/mtu.h>
+#include <plat/pincfg.h>
 
 #include <mach/nand.h>
 #include <mach/fsmc.h>
@@ -291,8 +293,42 @@ static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = {
        },
 };
 
+static unsigned long out_low[] = { PIN_OUTPUT_LOW };
+static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
+static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
+static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
+
+static struct pinctrl_map __initdata nhk8815_pinmap[] = {
+       PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
+       PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
+       /* Hog in MMC/SD card mux */
+       PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
+       /* MCCLK */
+       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
+       /* MCCMD */
+       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
+       /* MCCMDDIR */
+       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
+       /* MCDAT3-0 */
+       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
+       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
+       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
+       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
+       /* MCDAT0DIR */
+       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
+       /* MCDAT31DIR */
+       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
+       /* MCMSFBCLK */
+       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
+       /* CD input GPIO */
+       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
+       /* CD bias drive */
+       PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
+};
+
 static void __init nhk8815_platform_init(void)
 {
+       pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
        cpu8815_platform_init();
        nhk8815_onenand_init();
        platform_add_devices(nhk8815_platform_devices,

diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 6fd8e46567a4e602fc15bed22f97f8661e7dc1c5..b617eaed0ce58695ac709b460ac29b8ac2d4b1d6 100644 (file)
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -83,6 +83,18 @@ void cpu8815_add_gpios(resource_size_t *base, int num, int irq,
        }
 }
 
+static inline void
+cpu8815_add_pinctrl(struct device *parent, const char *name)
+{
+       struct platform_device_info pdevinfo = {
+               .parent = parent,
+               .name = name,
+               .id = -1,
+       };
+
+       platform_device_register_full(&pdevinfo);
+}
+
 static int __init cpu8815_init(void)
 {
        struct nmk_gpio_platform_data pdata = {
@@ -91,6 +103,7 @@ static int __init cpu8815_init(void)
 
        cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base),
                          IRQ_GPIO0, &pdata);
+       cpu8815_add_pinctrl(NULL, "pinctrl-stn8815");
        amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0);
        amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0);
        return 0;

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 54e3588bef62ab73ef75cbc6f8878d84c72e43ec..73aafd96271fea082b9261b16e46960847f14bbe 100644 (file)
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -31,6 +31,14 @@ config PINCTRL_IMX
        select PINMUX
        select PINCONF
 
+config PINCTRL_IMX35
+       bool "IMX35 pinctrl driver"
+       depends on OF
+       depends on SOC_IMX35
+       select PINCTRL_IMX
+       help
+         Say Y here to enable the imx35 pinctrl driver
+
 config PINCTRL_IMX51
        bool "IMX51 pinctrl driver"
        depends on OF
@@ -86,10 +94,18 @@ config PINCTRL_NOMADIK
        select PINMUX
        select PINCONF
 
+config PINCTRL_STN8815
+       bool "STN8815 pin controller driver"
+       depends on PINCTRL_NOMADIK && ARCH_NOMADIK
+
 config PINCTRL_DB8500
        bool "DB8500 pin controller driver"
        depends on PINCTRL_NOMADIK && ARCH_U8500
 
+config PINCTRL_DB8540
+       bool "DB8540 pin controller driver"
+       depends on PINCTRL_NOMADIK && ARCH_U8500
+
 config PINCTRL_PXA168
        bool "PXA168 pin controller driver"
        depends on ARCH_MMP

diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f40b1f81ff2ceea2f7421bc8d9761f7bb990bb11..cda3984951e28c4f465623cdca3922e68eab4c17 100644 (file)
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL)         += devicetree.o
 endif
 obj-$(CONFIG_GENERIC_PINCONF)  += pinconf-generic.o
 obj-$(CONFIG_PINCTRL_IMX)      += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX35)    += pinctrl-imx35.o
 obj-$(CONFIG_PINCTRL_IMX51)    += pinctrl-imx51.o
 obj-$(CONFIG_PINCTRL_IMX53)    += pinctrl-imx53.o
 obj-$(CONFIG_PINCTRL_IMX6Q)    += pinctrl-imx6q.o
@@ -19,7 +20,9 @@ obj-$(CONFIG_PINCTRL_MXS)     += pinctrl-mxs.o
 obj-$(CONFIG_PINCTRL_IMX23)    += pinctrl-imx23.o
 obj-$(CONFIG_PINCTRL_IMX28)    += pinctrl-imx28.o
 obj-$(CONFIG_PINCTRL_NOMADIK)  += pinctrl-nomadik.o
+obj-$(CONFIG_PINCTRL_STN8815)  += pinctrl-nomadik-stn8815.o
 obj-$(CONFIG_PINCTRL_DB8500)   += pinctrl-nomadik-db8500.o
+obj-$(CONFIG_PINCTRL_DB8540)   += pinctrl-nomadik-db8540.o
 obj-$(CONFIG_PINCTRL_PXA168)   += pinctrl-pxa168.o
 obj-$(CONFIG_PINCTRL_PXA910)   += pinctrl-pxa910.o
 obj-$(CONFIG_PINCTRL_SINGLE)   += pinctrl-single.o

diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index fb7f3bebdc69dadec1451773c596c9b901821265..dc5c126e398a0ac84fc13fa5f564d832ade0831e 100644 (file)
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -657,11 +657,7 @@ static struct pinctrl *pinctrl_get_locked(struct device *dev)
        if (p != NULL)
                return ERR_PTR(-EBUSY);
 
-       p = create_pinctrl(dev);
-       if (IS_ERR(p))
-               return p;
-
-       return p;
+       return create_pinctrl(dev);
 }
 
 /**
@@ -738,11 +734,8 @@ static struct pinctrl_state *pinctrl_lookup_state_locked(struct pinctrl *p,
                        dev_dbg(p->dev, "using pinctrl dummy state (%s)\n",
                                name);
                        state = create_state(p, name);
-                       if (IS_ERR(state))
-                               return state;
-               } else {
-                       return ERR_PTR(-ENODEV);
-               }
+               } else
+                       state = ERR_PTR(-ENODEV);
        }
 
        return state;

diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c
new file mode 100644 (file)
index 0000000..82f109e
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx35.c
@@ -0,0 +1,1595 @@
+/*
+ * imx35 pinctrl driver.
+ *
+ * This driver was mostly copied from the imx51 pinctrl driver which has:
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx35_pads {
+       MX35_PAD_CAPTURE = 0,
+       MX35_PAD_COMPARE = 1,
+       MX35_PAD_WDOG_RST = 2,
+       MX35_PAD_GPIO1_0 = 3,
+       MX35_PAD_GPIO1_1 = 4,
+       MX35_PAD_GPIO2_0 = 5,
+       MX35_PAD_GPIO3_0 = 6,
+       MX35_PAD_RESET_IN_B = 7,
+       MX35_PAD_POR_B = 8,
+       MX35_PAD_CLKO = 9,
+       MX35_PAD_BOOT_MODE0 = 10,
+       MX35_PAD_BOOT_MODE1 = 11,
+       MX35_PAD_CLK_MODE0 = 12,
+       MX35_PAD_CLK_MODE1 = 13,
+       MX35_PAD_POWER_FAIL = 14,
+       MX35_PAD_VSTBY = 15,
+       MX35_PAD_A0 = 16,
+       MX35_PAD_A1 = 17,
+       MX35_PAD_A2 = 18,
+       MX35_PAD_A3 = 19,
+       MX35_PAD_A4 = 20,
+       MX35_PAD_A5 = 21,
+       MX35_PAD_A6 = 22,
+       MX35_PAD_A7 = 23,
+       MX35_PAD_A8 = 24,
+       MX35_PAD_A9 = 25,
+       MX35_PAD_A10 = 26,
+       MX35_PAD_MA10 = 27,
+       MX35_PAD_A11 = 28,
+       MX35_PAD_A12 = 29,
+       MX35_PAD_A13 = 30,
+       MX35_PAD_A14 = 31,
+       MX35_PAD_A15 = 32,
+       MX35_PAD_A16 = 33,
+       MX35_PAD_A17 = 34,
+       MX35_PAD_A18 = 35,
+       MX35_PAD_A19 = 36,
+       MX35_PAD_A20 = 37,
+       MX35_PAD_A21 = 38,
+       MX35_PAD_A22 = 39,
+       MX35_PAD_A23 = 40,
+       MX35_PAD_A24 = 41,
+       MX35_PAD_A25 = 42,
+       MX35_PAD_SDBA1 = 43,
+       MX35_PAD_SDBA0 = 44,
+       MX35_PAD_SD0 = 45,
+       MX35_PAD_SD1 = 46,
+       MX35_PAD_SD2 = 47,
+       MX35_PAD_SD3 = 48,
+       MX35_PAD_SD4 = 49,
+       MX35_PAD_SD5 = 50,
+       MX35_PAD_SD6 = 51,
+       MX35_PAD_SD7 = 52,
+       MX35_PAD_SD8 = 53,
+       MX35_PAD_SD9 = 54,
+       MX35_PAD_SD10 = 55,
+       MX35_PAD_SD11 = 56,
+       MX35_PAD_SD12 = 57,
+       MX35_PAD_SD13 = 58,
+       MX35_PAD_SD14 = 59,
+       MX35_PAD_SD15 = 60,
+       MX35_PAD_SD16 = 61,
+       MX35_PAD_SD17 = 62,
+       MX35_PAD_SD18 = 63,
+       MX35_PAD_SD19 = 64,
+       MX35_PAD_SD20 = 65,
+       MX35_PAD_SD21 = 66,
+       MX35_PAD_SD22 = 67,
+       MX35_PAD_SD23 = 68,
+       MX35_PAD_SD24 = 69,
+       MX35_PAD_SD25 = 70,
+       MX35_PAD_SD26 = 71,
+       MX35_PAD_SD27 = 72,
+       MX35_PAD_SD28 = 73,
+       MX35_PAD_SD29 = 74,
+       MX35_PAD_SD30 = 75,
+       MX35_PAD_SD31 = 76,
+       MX35_PAD_DQM0 = 77,
+       MX35_PAD_DQM1 = 78,
+       MX35_PAD_DQM2 = 79,
+       MX35_PAD_DQM3 = 80,
+       MX35_PAD_EB0 = 81,
+       MX35_PAD_EB1 = 82,
+       MX35_PAD_OE = 83,
+       MX35_PAD_CS0 = 84,
+       MX35_PAD_CS1 = 85,
+       MX35_PAD_CS2 = 86,
+       MX35_PAD_CS3 = 87,
+       MX35_PAD_CS4 = 88,
+       MX35_PAD_CS5 = 89,
+       MX35_PAD_NF_CE0 = 90,
+       MX35_PAD_ECB = 91,
+       MX35_PAD_LBA = 92,
+       MX35_PAD_BCLK = 93,
+       MX35_PAD_RW = 94,
+       MX35_PAD_RAS = 95,
+       MX35_PAD_CAS = 96,
+       MX35_PAD_SDWE = 97,
+       MX35_PAD_SDCKE0 = 98,
+       MX35_PAD_SDCKE1 = 99,
+       MX35_PAD_SDCLK = 100,
+       MX35_PAD_SDQS0 = 101,
+       MX35_PAD_SDQS1 = 102,
+       MX35_PAD_SDQS2 = 103,
+       MX35_PAD_SDQS3 = 104,
+       MX35_PAD_NFWE_B = 105,
+       MX35_PAD_NFRE_B = 106,
+       MX35_PAD_NFALE = 107,
+       MX35_PAD_NFCLE = 108,
+       MX35_PAD_NFWP_B = 109,
+       MX35_PAD_NFRB = 110,
+       MX35_PAD_D15 = 111,
+       MX35_PAD_D14 = 112,
+       MX35_PAD_D13 = 113,
+       MX35_PAD_D12 = 114,
+       MX35_PAD_D11 = 115,
+       MX35_PAD_D10 = 116,
+       MX35_PAD_D9 = 117,
+       MX35_PAD_D8 = 118,
+       MX35_PAD_D7 = 119,
+       MX35_PAD_D6 = 120,
+       MX35_PAD_D5 = 121,
+       MX35_PAD_D4 = 122,
+       MX35_PAD_D3 = 123,
+       MX35_PAD_D2 = 124,
+       MX35_PAD_D1 = 125,
+       MX35_PAD_D0 = 126,
+       MX35_PAD_CSI_D8 = 127,
+       MX35_PAD_CSI_D9 = 128,
+       MX35_PAD_CSI_D10 = 129,
+       MX35_PAD_CSI_D11 = 130,
+       MX35_PAD_CSI_D12 = 131,
+       MX35_PAD_CSI_D13 = 132,
+       MX35_PAD_CSI_D14 = 133,
+       MX35_PAD_CSI_D15 = 134,
+       MX35_PAD_CSI_MCLK = 135,
+       MX35_PAD_CSI_VSYNC = 136,
+       MX35_PAD_CSI_HSYNC = 137,
+       MX35_PAD_CSI_PIXCLK = 138,
+       MX35_PAD_I2C1_CLK = 139,
+       MX35_PAD_I2C1_DAT = 140,
+       MX35_PAD_I2C2_CLK = 141,
+       MX35_PAD_I2C2_DAT = 142,
+       MX35_PAD_STXD4 = 143,
+       MX35_PAD_SRXD4 = 144,
+       MX35_PAD_SCK4 = 145,
+       MX35_PAD_STXFS4 = 146,
+       MX35_PAD_STXD5 = 147,
+       MX35_PAD_SRXD5 = 148,
+       MX35_PAD_SCK5 = 149,
+       MX35_PAD_STXFS5 = 150,
+       MX35_PAD_SCKR = 151,
+       MX35_PAD_FSR = 152,
+       MX35_PAD_HCKR = 153,
+       MX35_PAD_SCKT = 154,
+       MX35_PAD_FST = 155,
+       MX35_PAD_HCKT = 156,
+       MX35_PAD_TX5_RX0 = 157,
+       MX35_PAD_TX4_RX1 = 158,
+       MX35_PAD_TX3_RX2 = 159,
+       MX35_PAD_TX2_RX3 = 160,
+       MX35_PAD_TX1 = 161,
+       MX35_PAD_TX0 = 162,
+       MX35_PAD_CSPI1_MOSI = 163,
+       MX35_PAD_CSPI1_MISO = 164,
+       MX35_PAD_CSPI1_SS0 = 165,
+       MX35_PAD_CSPI1_SS1 = 166,
+       MX35_PAD_CSPI1_SCLK = 167,
+       MX35_PAD_CSPI1_SPI_RDY = 168,
+       MX35_PAD_RXD1 = 169,
+       MX35_PAD_TXD1 = 170,
+       MX35_PAD_RTS1 = 171,
+       MX35_PAD_CTS1 = 172,
+       MX35_PAD_RXD2 = 173,
+       MX35_PAD_TXD2 = 174,
+       MX35_PAD_RTS2 = 175,
+       MX35_PAD_CTS2 = 176,
+       MX35_PAD_RTCK = 177,
+       MX35_PAD_TCK = 178,
+       MX35_PAD_TMS = 179,
+       MX35_PAD_TDI = 180,
+       MX35_PAD_TDO = 181,
+       MX35_PAD_TRSTB = 182,
+       MX35_PAD_DE_B = 183,
+       MX35_PAD_SJC_MOD = 184,
+       MX35_PAD_USBOTG_PWR = 185,
+       MX35_PAD_USBOTG_OC = 186,
+       MX35_PAD_LD0 = 187,
+       MX35_PAD_LD1 = 188,
+       MX35_PAD_LD2 = 189,
+       MX35_PAD_LD3 = 190,
+       MX35_PAD_LD4 = 191,
+       MX35_PAD_LD5 = 192,
+       MX35_PAD_LD6 = 193,
+       MX35_PAD_LD7 = 194,
+       MX35_PAD_LD8 = 195,
+       MX35_PAD_LD9 = 196,
+       MX35_PAD_LD10 = 197,
+       MX35_PAD_LD11 = 198,
+       MX35_PAD_LD12 = 199,
+       MX35_PAD_LD13 = 200,
+       MX35_PAD_LD14 = 201,
+       MX35_PAD_LD15 = 202,
+       MX35_PAD_LD16 = 203,
+       MX35_PAD_LD17 = 204,
+       MX35_PAD_LD18 = 205,
+       MX35_PAD_LD19 = 206,
+       MX35_PAD_LD20 = 207,
+       MX35_PAD_LD21 = 208,
+       MX35_PAD_LD22 = 209,
+       MX35_PAD_LD23 = 210,
+       MX35_PAD_D3_HSYNC = 211,
+       MX35_PAD_D3_FPSHIFT = 212,
+       MX35_PAD_D3_DRDY = 213,
+       MX35_PAD_CONTRAST = 214,
+       MX35_PAD_D3_VSYNC = 215,
+       MX35_PAD_D3_REV = 216,
+       MX35_PAD_D3_CLS = 217,
+       MX35_PAD_D3_SPL = 218,
+       MX35_PAD_SD1_CMD = 219,
+       MX35_PAD_SD1_CLK = 220,
+       MX35_PAD_SD1_DATA0 = 221,
+       MX35_PAD_SD1_DATA1 = 222,
+       MX35_PAD_SD1_DATA2 = 223,
+       MX35_PAD_SD1_DATA3 = 224,
+       MX35_PAD_SD2_CMD = 225,
+       MX35_PAD_SD2_CLK = 226,
+       MX35_PAD_SD2_DATA0 = 227,
+       MX35_PAD_SD2_DATA1 = 228,
+       MX35_PAD_SD2_DATA2 = 229,
+       MX35_PAD_SD2_DATA3 = 230,
+       MX35_PAD_ATA_CS0 = 231,
+       MX35_PAD_ATA_CS1 = 232,
+       MX35_PAD_ATA_DIOR = 233,
+       MX35_PAD_ATA_DIOW = 234,
+       MX35_PAD_ATA_DMACK = 235,
+       MX35_PAD_ATA_RESET_B = 236,
+       MX35_PAD_ATA_IORDY = 237,
+       MX35_PAD_ATA_DATA0 = 238,
+       MX35_PAD_ATA_DATA1 = 239,
+       MX35_PAD_ATA_DATA2 = 240,
+       MX35_PAD_ATA_DATA3 = 241,
+       MX35_PAD_ATA_DATA4 = 242,
+       MX35_PAD_ATA_DATA5 = 243,
+       MX35_PAD_ATA_DATA6 = 244,
+       MX35_PAD_ATA_DATA7 = 245,
+       MX35_PAD_ATA_DATA8 = 246,
+       MX35_PAD_ATA_DATA9 = 247,
+       MX35_PAD_ATA_DATA10 = 248,
+       MX35_PAD_ATA_DATA11 = 249,
+       MX35_PAD_ATA_DATA12 = 250,
+       MX35_PAD_ATA_DATA13 = 251,
+       MX35_PAD_ATA_DATA14 = 252,
+       MX35_PAD_ATA_DATA15 = 253,
+       MX35_PAD_ATA_INTRQ = 254,
+       MX35_PAD_ATA_BUFF_EN = 255,
+       MX35_PAD_ATA_DMARQ = 256,
+       MX35_PAD_ATA_DA0 = 257,
+       MX35_PAD_ATA_DA1 = 258,
+       MX35_PAD_ATA_DA2 = 259,
+       MX35_PAD_MLB_CLK = 260,
+       MX35_PAD_MLB_DAT = 261,
+       MX35_PAD_MLB_SIG = 262,
+       MX35_PAD_FEC_TX_CLK = 263,
+       MX35_PAD_FEC_RX_CLK = 264,
+       MX35_PAD_FEC_RX_DV = 265,
+       MX35_PAD_FEC_COL = 266,
+       MX35_PAD_FEC_RDATA0 = 267,
+       MX35_PAD_FEC_TDATA0 = 268,
+       MX35_PAD_FEC_TX_EN = 269,
+       MX35_PAD_FEC_MDC = 270,
+       MX35_PAD_FEC_MDIO = 271,
+       MX35_PAD_FEC_TX_ERR = 272,
+       MX35_PAD_FEC_RX_ERR = 273,
+       MX35_PAD_FEC_CRS = 274,
+       MX35_PAD_FEC_RDATA1 = 275,
+       MX35_PAD_FEC_TDATA1 = 276,
+       MX35_PAD_FEC_RDATA2 = 277,
+       MX35_PAD_FEC_TDATA2 = 278,
+       MX35_PAD_FEC_RDATA3 = 279,
+       MX35_PAD_FEC_TDATA3 = 280,
+       MX35_PAD_EXT_ARMCLK = 281,
+       MX35_PAD_TEST_MODE = 282,
+};
+
+/* imx35 register maps */
+static struct imx_pin_reg imx35_pin_regs[] = {
+       [0] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 0, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CAPIN1 */
+       [1] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 1, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CMPOUT2 */
+       [2] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 2, 0x7f4, 0), /* MX35_PAD_CAPTURE__CSPI2_SS1 */
+       [3] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 3, 0x0, 0), /* MX35_PAD_CAPTURE__EPIT1_EPITO */
+       [4] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 4, 0x7d0, 0), /* MX35_PAD_CAPTURE__CCM_CLK32K */
+       [5] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 5, 0x850, 0), /* MX35_PAD_CAPTURE__GPIO1_4 */
+       [6] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 0, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT1 */
+       [7] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 1, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CAPIN2 */
+       [8] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 2, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT3 */
+       [9] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 3, 0x0, 0), /* MX35_PAD_COMPARE__EPIT2_EPITO */
+       [10] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 5, 0x854, 0), /* MX35_PAD_COMPARE__GPIO1_5 */
+       [11] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 7, 0x0, 0), /* MX35_PAD_COMPARE__SDMA_EXTDMA_2 */
+       [12] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 0, 0x0, 0), /* MX35_PAD_WDOG_RST__WDOG_WDOG_B */
+       [13] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 3, 0x0, 0), /* MX35_PAD_WDOG_RST__IPU_FLASH_STROBE */
+       [14] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 5, 0x858, 0), /* MX35_PAD_WDOG_RST__GPIO1_6 */
+       [15] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 0, 0x82c, 0), /* MX35_PAD_GPIO1_0__GPIO1_0 */
+       [16] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 1, 0x7d4, 0), /* MX35_PAD_GPIO1_0__CCM_PMIC_RDY */
+       [17] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 2, 0x990, 0), /* MX35_PAD_GPIO1_0__OWIRE_LINE */
+       [18] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 7, 0x0, 0), /* MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 */
+       [19] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 0, 0x838, 0), /* MX35_PAD_GPIO1_1__GPIO1_1 */
+       [20] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 2, 0x0, 0), /* MX35_PAD_GPIO1_1__PWM_PWMO */
+       [21] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 3, 0x7d8, 0), /* MX35_PAD_GPIO1_1__CSPI1_SS2 */
+       [22] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 6, 0x0, 0), /* MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT */
+       [23] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 7, 0x0, 0), /* MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 */
+       [24] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 0, 0x868, 0), /* MX35_PAD_GPIO2_0__GPIO2_0 */
+       [25] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 1, 0x0, 0), /* MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK */
+       [26] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 0, 0x8e8, 0), /* MX35_PAD_GPIO3_0__GPIO3_0 */
+       [27] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 1, 0x0, 0), /* MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK */
+       [28] = IMX_PIN_REG(MX35_PAD_RESET_IN_B, 0x344, 0x0, 0, 0x0, 0), /* MX35_PAD_RESET_IN_B__CCM_RESET_IN_B */
+       [29] = IMX_PIN_REG(MX35_PAD_POR_B, 0x348, 0x0, 0, 0x0, 0), /* MX35_PAD_POR_B__CCM_POR_B */
+       [30] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 0, 0x0, 0), /* MX35_PAD_CLKO__CCM_CLKO */
+       [31] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 5, 0x860, 0), /* MX35_PAD_CLKO__GPIO1_8 */
+       [32] = IMX_PIN_REG(MX35_PAD_BOOT_MODE0, 0x350, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 */
+       [33] = IMX_PIN_REG(MX35_PAD_BOOT_MODE1, 0x354, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 */
+       [34] = IMX_PIN_REG(MX35_PAD_CLK_MODE0, 0x358, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 */
+       [35] = IMX_PIN_REG(MX35_PAD_CLK_MODE1, 0x35c, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 */
+       [36] = IMX_PIN_REG(MX35_PAD_POWER_FAIL, 0x360, 0x0, 0, 0x0, 0), /* MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 */
+       [37] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 0, 0x0, 0), /* MX35_PAD_VSTBY__CCM_VSTBY */
+       [38] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 5, 0x85c, 0), /* MX35_PAD_VSTBY__GPIO1_7 */
+       [39] = IMX_PIN_REG(MX35_PAD_A0, 0x368, 0x028, 0, 0x0, 0), /* MX35_PAD_A0__EMI_EIM_DA_L_0 */
+       [40] = IMX_PIN_REG(MX35_PAD_A1, 0x36c, 0x02c, 0, 0x0, 0), /* MX35_PAD_A1__EMI_EIM_DA_L_1 */
+       [41] = IMX_PIN_REG(MX35_PAD_A2, 0x370, 0x030, 0, 0x0, 0), /* MX35_PAD_A2__EMI_EIM_DA_L_2 */
+       [42] = IMX_PIN_REG(MX35_PAD_A3, 0x374, 0x034, 0, 0x0, 0), /* MX35_PAD_A3__EMI_EIM_DA_L_3 */
+       [43] = IMX_PIN_REG(MX35_PAD_A4, 0x378, 0x038, 0, 0x0, 0), /* MX35_PAD_A4__EMI_EIM_DA_L_4 */
+       [44] = IMX_PIN_REG(MX35_PAD_A5, 0x37c, 0x03c, 0, 0x0, 0), /* MX35_PAD_A5__EMI_EIM_DA_L_5 */
+       [45] = IMX_PIN_REG(MX35_PAD_A6, 0x380, 0x040, 0, 0x0, 0), /* MX35_PAD_A6__EMI_EIM_DA_L_6 */
+       [46] = IMX_PIN_REG(MX35_PAD_A7, 0x384, 0x044, 0, 0x0, 0), /* MX35_PAD_A7__EMI_EIM_DA_L_7 */
+       [47] = IMX_PIN_REG(MX35_PAD_A8, 0x388, 0x048, 0, 0x0, 0), /* MX35_PAD_A8__EMI_EIM_DA_H_8 */
+       [48] = IMX_PIN_REG(MX35_PAD_A9, 0x38c, 0x04c, 0, 0x0, 0), /* MX35_PAD_A9__EMI_EIM_DA_H_9 */
+       [49] = IMX_PIN_REG(MX35_PAD_A10, 0x390, 0x050, 0, 0x0, 0), /* MX35_PAD_A10__EMI_EIM_DA_H_10 */
+       [50] = IMX_PIN_REG(MX35_PAD_MA10, 0x394, 0x054, 0, 0x0, 0), /* MX35_PAD_MA10__EMI_MA10 */
+       [51] = IMX_PIN_REG(MX35_PAD_A11, 0x398, 0x058, 0, 0x0, 0), /* MX35_PAD_A11__EMI_EIM_DA_H_11 */
+       [52] = IMX_PIN_REG(MX35_PAD_A12, 0x39c, 0x05c, 0, 0x0, 0), /* MX35_PAD_A12__EMI_EIM_DA_H_12 */
+       [53] = IMX_PIN_REG(MX35_PAD_A13, 0x3a0, 0x060, 0, 0x0, 0), /* MX35_PAD_A13__EMI_EIM_DA_H_13 */
+       [54] = IMX_PIN_REG(MX35_PAD_A14, 0x3a4, 0x064, 0, 0x0, 0), /* MX35_PAD_A14__EMI_EIM_DA_H2_14 */
+       [55] = IMX_PIN_REG(MX35_PAD_A15, 0x3a8, 0x068, 0, 0x0, 0), /* MX35_PAD_A15__EMI_EIM_DA_H2_15 */
+       [56] = IMX_PIN_REG(MX35_PAD_A16, 0x3ac, 0x06c, 0, 0x0, 0), /* MX35_PAD_A16__EMI_EIM_A_16 */
+       [57] = IMX_PIN_REG(MX35_PAD_A17, 0x3b0, 0x070, 0, 0x0, 0), /* MX35_PAD_A17__EMI_EIM_A_17 */
+       [58] = IMX_PIN_REG(MX35_PAD_A18, 0x3b4, 0x074, 0, 0x0, 0), /* MX35_PAD_A18__EMI_EIM_A_18 */
+       [59] = IMX_PIN_REG(MX35_PAD_A19, 0x3b8, 0x078, 0, 0x0, 0), /* MX35_PAD_A19__EMI_EIM_A_19 */
+       [60] = IMX_PIN_REG(MX35_PAD_A20, 0x3bc, 0x07c, 0, 0x0, 0), /* MX35_PAD_A20__EMI_EIM_A_20 */
+       [61] = IMX_PIN_REG(MX35_PAD_A21, 0x3c0, 0x080, 0, 0x0, 0), /* MX35_PAD_A21__EMI_EIM_A_21 */
+       [62] = IMX_PIN_REG(MX35_PAD_A22, 0x3c4, 0x084, 0, 0x0, 0), /* MX35_PAD_A22__EMI_EIM_A_22 */
+       [63] = IMX_PIN_REG(MX35_PAD_A23, 0x3c8, 0x088, 0, 0x0, 0), /* MX35_PAD_A23__EMI_EIM_A_23 */
+       [64] = IMX_PIN_REG(MX35_PAD_A24, 0x3cc, 0x08c, 0, 0x0, 0), /* MX35_PAD_A24__EMI_EIM_A_24 */
+       [65] = IMX_PIN_REG(MX35_PAD_A25, 0x3d0, 0x090, 0, 0x0, 0), /* MX35_PAD_A25__EMI_EIM_A_25 */
+       [66] = IMX_PIN_REG(MX35_PAD_SDBA1, 0x3d4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA1__EMI_EIM_SDBA1 */
+       [67] = IMX_PIN_REG(MX35_PAD_SDBA0, 0x3d8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA0__EMI_EIM_SDBA0 */
+       [68] = IMX_PIN_REG(MX35_PAD_SD0, 0x3dc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD0__EMI_DRAM_D_0 */
+       [69] = IMX_PIN_REG(MX35_PAD_SD1, 0x3e0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD1__EMI_DRAM_D_1 */
+       [70] = IMX_PIN_REG(MX35_PAD_SD2, 0x3e4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD2__EMI_DRAM_D_2 */
+       [71] = IMX_PIN_REG(MX35_PAD_SD3, 0x3e8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD3__EMI_DRAM_D_3 */
+       [72] = IMX_PIN_REG(MX35_PAD_SD4, 0x3ec, 0x0, 0, 0x0, 0), /* MX35_PAD_SD4__EMI_DRAM_D_4 */
+       [73] = IMX_PIN_REG(MX35_PAD_SD5, 0x3f0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD5__EMI_DRAM_D_5 */
+       [74] = IMX_PIN_REG(MX35_PAD_SD6, 0x3f4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD6__EMI_DRAM_D_6 */
+       [75] = IMX_PIN_REG(MX35_PAD_SD7, 0x3f8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD7__EMI_DRAM_D_7 */
+       [76] = IMX_PIN_REG(MX35_PAD_SD8, 0x3fc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD8__EMI_DRAM_D_8 */
+       [77] = IMX_PIN_REG(MX35_PAD_SD9, 0x400, 0x0, 0, 0x0, 0), /* MX35_PAD_SD9__EMI_DRAM_D_9 */
+       [78] = IMX_PIN_REG(MX35_PAD_SD10, 0x404, 0x0, 0, 0x0, 0), /* MX35_PAD_SD10__EMI_DRAM_D_10 */
+       [79] = IMX_PIN_REG(MX35_PAD_SD11, 0x408, 0x0, 0, 0x0, 0), /* MX35_PAD_SD11__EMI_DRAM_D_11 */
+       [80] = IMX_PIN_REG(MX35_PAD_SD12, 0x40c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD12__EMI_DRAM_D_12 */
+       [81] = IMX_PIN_REG(MX35_PAD_SD13, 0x410, 0x0, 0, 0x0, 0), /* MX35_PAD_SD13__EMI_DRAM_D_13 */
+       [82] = IMX_PIN_REG(MX35_PAD_SD14, 0x414, 0x0, 0, 0x0, 0), /* MX35_PAD_SD14__EMI_DRAM_D_14 */
+       [83] = IMX_PIN_REG(MX35_PAD_SD15, 0x418, 0x0, 0, 0x0, 0), /* MX35_PAD_SD15__EMI_DRAM_D_15 */
+       [84] = IMX_PIN_REG(MX35_PAD_SD16, 0x41c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD16__EMI_DRAM_D_16 */
+       [85] = IMX_PIN_REG(MX35_PAD_SD17, 0x420, 0x0, 0, 0x0, 0), /* MX35_PAD_SD17__EMI_DRAM_D_17 */
+       [86] = IMX_PIN_REG(MX35_PAD_SD18, 0x424, 0x0, 0, 0x0, 0), /* MX35_PAD_SD18__EMI_DRAM_D_18 */
+       [87] = IMX_PIN_REG(MX35_PAD_SD19, 0x428, 0x0, 0, 0x0, 0), /* MX35_PAD_SD19__EMI_DRAM_D_19 */
+       [88] = IMX_PIN_REG(MX35_PAD_SD20, 0x42c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD20__EMI_DRAM_D_20 */
+       [89] = IMX_PIN_REG(MX35_PAD_SD21, 0x430, 0x0, 0, 0x0, 0), /* MX35_PAD_SD21__EMI_DRAM_D_21 */
+       [90] = IMX_PIN_REG(MX35_PAD_SD22, 0x434, 0x0, 0, 0x0, 0), /* MX35_PAD_SD22__EMI_DRAM_D_22 */
+       [91] = IMX_PIN_REG(MX35_PAD_SD23, 0x438, 0x0, 0, 0x0, 0), /* MX35_PAD_SD23__EMI_DRAM_D_23 */
+       [92] = IMX_PIN_REG(MX35_PAD_SD24, 0x43c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD24__EMI_DRAM_D_24 */
+       [93] = IMX_PIN_REG(MX35_PAD_SD25, 0x440, 0x0, 0, 0x0, 0), /* MX35_PAD_SD25__EMI_DRAM_D_25 */
+       [94] = IMX_PIN_REG(MX35_PAD_SD26, 0x444, 0x0, 0, 0x0, 0), /* MX35_PAD_SD26__EMI_DRAM_D_26 */
+       [95] = IMX_PIN_REG(MX35_PAD_SD27, 0x448, 0x0, 0, 0x0, 0), /* MX35_PAD_SD27__EMI_DRAM_D_27 */
+       [96] = IMX_PIN_REG(MX35_PAD_SD28, 0x44c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD28__EMI_DRAM_D_28 */
+       [97] = IMX_PIN_REG(MX35_PAD_SD29, 0x450, 0x0, 0, 0x0, 0), /* MX35_PAD_SD29__EMI_DRAM_D_29 */
+       [98] = IMX_PIN_REG(MX35_PAD_SD30, 0x454, 0x0, 0, 0x0, 0), /* MX35_PAD_SD30__EMI_DRAM_D_30 */
+       [99] = IMX_PIN_REG(MX35_PAD_SD31, 0x458, 0x0, 0, 0x0, 0), /* MX35_PAD_SD31__EMI_DRAM_D_31 */
+       [100] = IMX_PIN_REG(MX35_PAD_DQM0, 0x45c, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM0__EMI_DRAM_DQM_0 */
+       [101] = IMX_PIN_REG(MX35_PAD_DQM1, 0x460, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM1__EMI_DRAM_DQM_1 */
+       [102] = IMX_PIN_REG(MX35_PAD_DQM2, 0x464, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM2__EMI_DRAM_DQM_2 */
+       [103] = IMX_PIN_REG(MX35_PAD_DQM3, 0x468, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM3__EMI_DRAM_DQM_3 */
+       [104] = IMX_PIN_REG(MX35_PAD_EB0, 0x46c, 0x094, 0, 0x0, 0), /* MX35_PAD_EB0__EMI_EIM_EB0_B */
+       [105] = IMX_PIN_REG(MX35_PAD_EB1, 0x470, 0x098, 0, 0x0, 0), /* MX35_PAD_EB1__EMI_EIM_EB1_B */
+       [106] = IMX_PIN_REG(MX35_PAD_OE, 0x474, 0x09c, 0, 0x0, 0), /* MX35_PAD_OE__EMI_EIM_OE */
+       [107] = IMX_PIN_REG(MX35_PAD_CS0, 0x478, 0x0a0, 0, 0x0, 0), /* MX35_PAD_CS0__EMI_EIM_CS0 */
+       [108] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 0, 0x0, 0), /* MX35_PAD_CS1__EMI_EIM_CS1 */
+       [109] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 3, 0x0, 0), /* MX35_PAD_CS1__EMI_NANDF_CE3 */
+       [110] = IMX_PIN_REG(MX35_PAD_CS2, 0x480, 0x0a8, 0, 0x0, 0), /* MX35_PAD_CS2__EMI_EIM_CS2 */
+       [111] = IMX_PIN_REG(MX35_PAD_CS3, 0x484, 0x0ac, 0, 0x0, 0), /* MX35_PAD_CS3__EMI_EIM_CS3 */
+       [112] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 0, 0x0, 0), /* MX35_PAD_CS4__EMI_EIM_CS4 */
+       [113] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 1, 0x800, 0), /* MX35_PAD_CS4__EMI_DTACK_B */
+       [114] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 3, 0x0, 0), /* MX35_PAD_CS4__EMI_NANDF_CE1 */
+       [115] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 5, 0x83c, 0), /* MX35_PAD_CS4__GPIO1_20 */
+       [116] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 0, 0x0, 0), /* MX35_PAD_CS5__EMI_EIM_CS5 */
+       [117] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 1, 0x7f8, 0), /* MX35_PAD_CS5__CSPI2_SS2 */
+       [118] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 2, 0x7d8, 1), /* MX35_PAD_CS5__CSPI1_SS2 */
+       [119] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 3, 0x0, 0), /* MX35_PAD_CS5__EMI_NANDF_CE2 */
+       [120] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 5, 0x840, 0), /* MX35_PAD_CS5__GPIO1_21 */
+       [121] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 0, 0x0, 0), /* MX35_PAD_NF_CE0__EMI_NANDF_CE0 */
+       [122] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 5, 0x844, 0), /* MX35_PAD_NF_CE0__GPIO1_22 */
+       [123] = IMX_PIN_REG(MX35_PAD_ECB, 0x494, 0x0, 0, 0x0, 0), /* MX35_PAD_ECB__EMI_EIM_ECB */
+       [124] = IMX_PIN_REG(MX35_PAD_LBA, 0x498, 0x0bc, 0, 0x0, 0), /* MX35_PAD_LBA__EMI_EIM_LBA */
+       [125] = IMX_PIN_REG(MX35_PAD_BCLK, 0x49c, 0x0c0, 0, 0x0, 0), /* MX35_PAD_BCLK__EMI_EIM_BCLK */
+       [126] = IMX_PIN_REG(MX35_PAD_RW, 0x4a0, 0x0c4, 0, 0x0, 0), /* MX35_PAD_RW__EMI_EIM_RW */
+       [127] = IMX_PIN_REG(MX35_PAD_RAS, 0x4a4, 0x0, 0, 0x0, 0), /* MX35_PAD_RAS__EMI_DRAM_RAS */
+       [128] = IMX_PIN_REG(MX35_PAD_CAS, 0x4a8, 0x0, 0, 0x0, 0), /* MX35_PAD_CAS__EMI_DRAM_CAS */
+       [129] = IMX_PIN_REG(MX35_PAD_SDWE, 0x4ac, 0x0, 0, 0x0, 0), /* MX35_PAD_SDWE__EMI_DRAM_SDWE */
+       [130] = IMX_PIN_REG(MX35_PAD_SDCKE0, 0x4b0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 */
+       [131] = IMX_PIN_REG(MX35_PAD_SDCKE1, 0x4b4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 */
+       [132] = IMX_PIN_REG(MX35_PAD_SDCLK, 0x4b8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCLK__EMI_DRAM_SDCLK */
+       [133] = IMX_PIN_REG(MX35_PAD_SDQS0, 0x4bc, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 */
+       [134] = IMX_PIN_REG(MX35_PAD_SDQS1, 0x4c0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 */
+       [135] = IMX_PIN_REG(MX35_PAD_SDQS2, 0x4c4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 */
+       [136] = IMX_PIN_REG(MX35_PAD_SDQS3, 0x4c8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 */
+       [137] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 0, 0x0, 0), /* MX35_PAD_NFWE_B__EMI_NANDF_WE_B */
+       [138] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 1, 0x9d8, 0), /* MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 */
+       [139] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 2, 0x924, 0), /* MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC */
+       [140] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 5, 0x88c, 0), /* MX35_PAD_NFWE_B__GPIO2_18 */
+       [141] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 7, 0x0, 0), /* MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 */
+       [142] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 0, 0x0, 0), /* MX35_PAD_NFRE_B__EMI_NANDF_RE_B */
+       [143] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 1, 0x9ec, 0), /* MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR */
+       [144] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 2, 0x0, 0), /* MX35_PAD_NFRE_B__IPU_DISPB_BCLK */
+       [145] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 5, 0x890, 0), /* MX35_PAD_NFRE_B__GPIO2_19 */
+       [146] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 7, 0x0, 0), /* MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 */
+       [147] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 0, 0x0, 0), /* MX35_PAD_NFALE__EMI_NANDF_ALE */
+       [148] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 1, 0x0, 0), /* MX35_PAD_NFALE__USB_TOP_USBH2_STP */
+       [149] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 2, 0x0, 0), /* MX35_PAD_NFALE__IPU_DISPB_CS0 */
+       [150] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 5, 0x898, 0), /* MX35_PAD_NFALE__GPIO2_20 */
+       [151] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 7, 0x0, 0), /* MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 */
+       [152] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 0, 0x0, 0), /* MX35_PAD_NFCLE__EMI_NANDF_CLE */
+       [153] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 1, 0x9f0, 0), /* MX35_PAD_NFCLE__USB_TOP_USBH2_NXT */
+       [154] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 2, 0x0, 0), /* MX35_PAD_NFCLE__IPU_DISPB_PAR_RS */
+       [155] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 5, 0x89c, 0), /* MX35_PAD_NFCLE__GPIO2_21 */
+       [156] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 7, 0x0, 0), /* MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 */
+       [157] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 0, 0x0, 0), /* MX35_PAD_NFWP_B__EMI_NANDF_WP_B */
+       [158] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 1, 0x9e8, 0), /* MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 */
+       [159] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 2, 0x0, 0), /* MX35_PAD_NFWP_B__IPU_DISPB_WR */
+       [160] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 5, 0x8a0, 0), /* MX35_PAD_NFWP_B__GPIO2_22 */
+       [161] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 7, 0x0, 0), /* MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL */
+       [162] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 0, 0x0, 0), /* MX35_PAD_NFRB__EMI_NANDF_RB */
+       [163] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 2, 0x0, 0), /* MX35_PAD_NFRB__IPU_DISPB_RD */
+       [164] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 5, 0x8a4, 0), /* MX35_PAD_NFRB__GPIO2_23 */
+       [165] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 7, 0x0, 0), /* MX35_PAD_NFRB__ARM11P_TOP_TRCLK */
+       [166] = IMX_PIN_REG(MX35_PAD_D15, 0x4e4, 0x0, 0, 0x0, 0), /* MX35_PAD_D15__EMI_EIM_D_15 */
+       [167] = IMX_PIN_REG(MX35_PAD_D14, 0x4e8, 0x0, 0, 0x0, 0), /* MX35_PAD_D14__EMI_EIM_D_14 */
+       [168] = IMX_PIN_REG(MX35_PAD_D13, 0x4ec, 0x0, 0, 0x0, 0), /* MX35_PAD_D13__EMI_EIM_D_13 */
+       [169] = IMX_PIN_REG(MX35_PAD_D12, 0x4f0, 0x0, 0, 0x0, 0), /* MX35_PAD_D12__EMI_EIM_D_12 */
+       [170] = IMX_PIN_REG(MX35_PAD_D11, 0x4f4, 0x0, 0, 0x0, 0), /* MX35_PAD_D11__EMI_EIM_D_11 */
+       [171] = IMX_PIN_REG(MX35_PAD_D10, 0x4f8, 0x0, 0, 0x0, 0), /* MX35_PAD_D10__EMI_EIM_D_10 */
+       [172] = IMX_PIN_REG(MX35_PAD_D9, 0x4fc, 0x0, 0, 0x0, 0), /* MX35_PAD_D9__EMI_EIM_D_9 */
+       [173] = IMX_PIN_REG(MX35_PAD_D8, 0x500, 0x0, 0, 0x0, 0), /* MX35_PAD_D8__EMI_EIM_D_8 */
+       [174] = IMX_PIN_REG(MX35_PAD_D7, 0x504, 0x0, 0, 0x0, 0), /* MX35_PAD_D7__EMI_EIM_D_7 */
+       [175] = IMX_PIN_REG(MX35_PAD_D6, 0x508, 0x0, 0, 0x0, 0), /* MX35_PAD_D6__EMI_EIM_D_6 */
+       [176] = IMX_PIN_REG(MX35_PAD_D5, 0x50c, 0x0, 0, 0x0, 0), /* MX35_PAD_D5__EMI_EIM_D_5 */
+       [177] = IMX_PIN_REG(MX35_PAD_D4, 0x510, 0x0, 0, 0x0, 0), /* MX35_PAD_D4__EMI_EIM_D_4 */
+       [178] = IMX_PIN_REG(MX35_PAD_D3, 0x514, 0x0, 0, 0x0, 0), /* MX35_PAD_D3__EMI_EIM_D_3 */
+       [179] = IMX_PIN_REG(MX35_PAD_D2, 0x518, 0x0, 0, 0x0, 0), /* MX35_PAD_D2__EMI_EIM_D_2 */
+       [180] = IMX_PIN_REG(MX35_PAD_D1, 0x51c, 0x0, 0, 0x0, 0), /* MX35_PAD_D1__EMI_EIM_D_1 */
+       [181] = IMX_PIN_REG(MX35_PAD_D0, 0x520, 0x0, 0, 0x0, 0), /* MX35_PAD_D0__EMI_EIM_D_0 */
+       [182] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 0, 0x0, 0), /* MX35_PAD_CSI_D8__IPU_CSI_D_8 */
+       [183] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 1, 0x950, 0), /* MX35_PAD_CSI_D8__KPP_COL_0 */
+       [184] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 5, 0x83c, 1), /* MX35_PAD_CSI_D8__GPIO1_20 */
+       [185] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 7, 0x0, 0), /* MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 */
+       [186] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 0, 0x0, 0), /* MX35_PAD_CSI_D9__IPU_CSI_D_9 */
+       [187] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 1, 0x954, 0), /* MX35_PAD_CSI_D9__KPP_COL_1 */
+       [188] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 5, 0x840, 1), /* MX35_PAD_CSI_D9__GPIO1_21 */
+       [189] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 7, 0x0, 0), /* MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 */
+       [190] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 0, 0x0, 0), /* MX35_PAD_CSI_D10__IPU_CSI_D_10 */
+       [191] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 1, 0x958, 0), /* MX35_PAD_CSI_D10__KPP_COL_2 */
+       [192] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 5, 0x844, 1), /* MX35_PAD_CSI_D10__GPIO1_22 */
+       [193] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 7, 0x0, 0), /* MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 */
+       [194] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 0, 0x0, 0), /* MX35_PAD_CSI_D11__IPU_CSI_D_11 */
+       [195] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 1, 0x95c, 0), /* MX35_PAD_CSI_D11__KPP_COL_3 */
+       [196] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 5, 0x0, 0), /* MX35_PAD_CSI_D11__GPIO1_23 */
+       [197] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 0, 0x0, 0), /* MX35_PAD_CSI_D12__IPU_CSI_D_12 */
+       [198] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 1, 0x970, 0), /* MX35_PAD_CSI_D12__KPP_ROW_0 */
+       [199] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 5, 0x0, 0), /* MX35_PAD_CSI_D12__GPIO1_24 */
+       [200] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 0, 0x0, 0), /* MX35_PAD_CSI_D13__IPU_CSI_D_13 */
+       [201] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 1, 0x974, 0), /* MX35_PAD_CSI_D13__KPP_ROW_1 */
+       [202] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 5, 0x0, 0), /* MX35_PAD_CSI_D13__GPIO1_25 */
+       [203] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 0, 0x0, 0), /* MX35_PAD_CSI_D14__IPU_CSI_D_14 */
+       [204] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 1, 0x978, 0), /* MX35_PAD_CSI_D14__KPP_ROW_2 */
+       [205] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 5, 0x0, 0), /* MX35_PAD_CSI_D14__GPIO1_26 */
+       [206] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 0, 0x97c, 0), /* MX35_PAD_CSI_D15__IPU_CSI_D_15 */
+       [207] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 1, 0x0, 0), /* MX35_PAD_CSI_D15__KPP_ROW_3 */
+       [208] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 5, 0x0, 0), /* MX35_PAD_CSI_D15__GPIO1_27 */
+       [209] = IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 0, 0x0, 0), /* MX35_PAD_CSI_MCLK__IPU_CSI_MCLK */
+       [210] = IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 5, 0x0, 0), /* MX35_PAD_CSI_MCLK__GPIO1_28 */
+       [211] = IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 0, 0x0, 0), /* MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC */
+       [212] = IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 5, 0x0, 0), /* MX35_PAD_CSI_VSYNC__GPIO1_29 */
+       [213] = IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 0, 0x0, 0), /* MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC */
+       [214] = IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 5, 0x0, 0), /* MX35_PAD_CSI_HSYNC__GPIO1_30 */
+       [215] = IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 0, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK */
+       [216] = IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 5, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__GPIO1_31 */
+       [217] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 0, 0x0, 0), /* MX35_PAD_I2C1_CLK__I2C1_SCL */
+       [218] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 5, 0x8a8, 0), /* MX35_PAD_I2C1_CLK__GPIO2_24 */
+       [219] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 6, 0x0, 0), /* MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK */
+       [220] = IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 0, 0x0, 0), /* MX35_PAD_I2C1_DAT__I2C1_SDA */
+       [221] = IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 5, 0x8ac, 0), /* MX35_PAD_I2C1_DAT__GPIO2_25 */
+       [222] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 0, 0x0, 0), /* MX35_PAD_I2C2_CLK__I2C2_SCL */
+       [223] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 1, 0x0, 0), /* MX35_PAD_I2C2_CLK__CAN1_TXCAN */
+       [224] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 2, 0x0, 0), /* MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR */
+       [225] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 5, 0x8b0, 0), /* MX35_PAD_I2C2_CLK__GPIO2_26 */
+       [226] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 6, 0x0, 0), /* MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 */
+       [227] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 0, 0x0, 0), /* MX35_PAD_I2C2_DAT__I2C2_SDA */
+       [228] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 1, 0x7c8, 0), /* MX35_PAD_I2C2_DAT__CAN1_RXCAN */
+       [229] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 2, 0x9f4, 0), /* MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC */
+       [230] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 5, 0x8b4, 0), /* MX35_PAD_I2C2_DAT__GPIO2_27 */
+       [231] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 6, 0x0, 0), /* MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 */
+       [232] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 0, 0x0, 0), /* MX35_PAD_STXD4__AUDMUX_AUD4_TXD */
+       [233] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 5, 0x8b8, 0), /* MX35_PAD_STXD4__GPIO2_28 */
+       [234] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 7, 0x0, 0), /* MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 */
+       [235] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 0, 0x0, 0), /* MX35_PAD_SRXD4__AUDMUX_AUD4_RXD */
+       [236] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 5, 0x8bc, 0), /* MX35_PAD_SRXD4__GPIO2_29 */
+       [237] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 7, 0x0, 0), /* MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 */
+       [238] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 0, 0x0, 0), /* MX35_PAD_SCK4__AUDMUX_AUD4_TXC */
+       [239] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 5, 0x8c4, 0), /* MX35_PAD_SCK4__GPIO2_30 */
+       [240] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 7, 0x0, 0), /* MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 */
+       [241] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 0, 0x0, 0), /* MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS */
+       [242] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 5, 0x8c8, 0), /* MX35_PAD_STXFS4__GPIO2_31 */
+       [243] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 7, 0x0, 0), /* MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 */
+       [244] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 0, 0x0, 0), /* MX35_PAD_STXD5__AUDMUX_AUD5_TXD */
+       [245] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 1, 0x0, 0), /* MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 */
+       [246] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 2, 0x7ec, 0), /* MX35_PAD_STXD5__CSPI2_MOSI */
+       [247] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 5, 0x82c, 1), /* MX35_PAD_STXD5__GPIO1_0 */
+       [248] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 7, 0x0, 0), /* MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 */
+       [249] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 0, 0x0, 0), /* MX35_PAD_SRXD5__AUDMUX_AUD5_RXD */
+       [250] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 1, 0x998, 0), /* MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 */
+       [251] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 2, 0x7e8, 0), /* MX35_PAD_SRXD5__CSPI2_MISO */
+       [252] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 5, 0x838, 1), /* MX35_PAD_SRXD5__GPIO1_1 */
+       [253] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 7, 0x0, 0), /* MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 */
+       [254] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 0, 0x0, 0), /* MX35_PAD_SCK5__AUDMUX_AUD5_TXC */
+       [255] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 1, 0x994, 0), /* MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK */
+       [256] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 2, 0x7e0, 0), /* MX35_PAD_SCK5__CSPI2_SCLK */
+       [257] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 5, 0x848, 0), /* MX35_PAD_SCK5__GPIO1_2 */
+       [258] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 7, 0x0, 0), /* MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 */
+       [259] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 0, 0x0, 0), /* MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS */
+       [260] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 2, 0x7e4, 0), /* MX35_PAD_STXFS5__CSPI2_RDY */
+       [261] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 5, 0x84c, 0), /* MX35_PAD_STXFS5__GPIO1_3 */
+       [262] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 7, 0x0, 0), /* MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 */
+       [263] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 0, 0x0, 0), /* MX35_PAD_SCKR__ESAI_SCKR */
+       [264] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 5, 0x850, 1), /* MX35_PAD_SCKR__GPIO1_4 */
+       [265] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 7, 0x0, 0), /* MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 */
+       [266] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 0, 0x0, 0), /* MX35_PAD_FSR__ESAI_FSR */
+       [267] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 5, 0x854, 1), /* MX35_PAD_FSR__GPIO1_5 */
+       [268] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 7, 0x0, 0), /* MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 */
+       [269] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 0, 0x0, 0), /* MX35_PAD_HCKR__ESAI_HCKR */
+       [270] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 1, 0x0, 0), /* MX35_PAD_HCKR__AUDMUX_AUD5_RXFS */
+       [271] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 2, 0x7f0, 0), /* MX35_PAD_HCKR__CSPI2_SS0 */
+       [272] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 3, 0x0, 0), /* MX35_PAD_HCKR__IPU_FLASH_STROBE */
+       [273] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 5, 0x858, 1), /* MX35_PAD_HCKR__GPIO1_6 */
+       [274] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 7, 0x0, 0), /* MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 */
+       [275] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 0, 0x0, 0), /* MX35_PAD_SCKT__ESAI_SCKT */
+       [276] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 5, 0x85c, 1), /* MX35_PAD_SCKT__GPIO1_7 */
+       [277] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 6, 0x930, 0), /* MX35_PAD_SCKT__IPU_CSI_D_0 */
+       [278] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 7, 0x978, 1), /* MX35_PAD_SCKT__KPP_ROW_2 */
+       [279] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 0, 0x0, 0), /* MX35_PAD_FST__ESAI_FST */
+       [280] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 5, 0x860, 1), /* MX35_PAD_FST__GPIO1_8 */
+       [281] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 6, 0x934, 0), /* MX35_PAD_FST__IPU_CSI_D_1 */
+       [282] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 7, 0x97c, 1), /* MX35_PAD_FST__KPP_ROW_3 */
+       [283] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 0, 0x0, 0), /* MX35_PAD_HCKT__ESAI_HCKT */
+       [284] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 1, 0x7a8, 0), /* MX35_PAD_HCKT__AUDMUX_AUD5_RXC */
+       [285] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 5, 0x864, 0), /* MX35_PAD_HCKT__GPIO1_9 */
+       [286] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 6, 0x938, 0), /* MX35_PAD_HCKT__IPU_CSI_D_2 */
+       [287] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 7, 0x95c, 1), /* MX35_PAD_HCKT__KPP_COL_3 */
+       [288] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 0, 0x0, 0), /* MX35_PAD_TX5_RX0__ESAI_TX5_RX0 */
+       [289] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 1, 0x0, 0), /* MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC */
+       [290] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 2, 0x7f8, 1), /* MX35_PAD_TX5_RX0__CSPI2_SS2 */
+       [291] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 3, 0x0, 0), /* MX35_PAD_TX5_RX0__CAN2_TXCAN */
+       [292] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 4, 0x0, 0), /* MX35_PAD_TX5_RX0__UART2_DTR */
+       [293] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 5, 0x830, 0), /* MX35_PAD_TX5_RX0__GPIO1_10 */
+       [294] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 7, 0x0, 0), /* MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 */
+       [295] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 0, 0x0, 0), /* MX35_PAD_TX4_RX1__ESAI_TX4_RX1 */
+       [296] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 1, 0x0, 0), /* MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS */
+       [297] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 2, 0x7fc, 0), /* MX35_PAD_TX4_RX1__CSPI2_SS3 */
+       [298] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 3, 0x7cc, 0), /* MX35_PAD_TX4_RX1__CAN2_RXCAN */
+       [299] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 4, 0x0, 0), /* MX35_PAD_TX4_RX1__UART2_DSR */
+       [300] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 5, 0x834, 0), /* MX35_PAD_TX4_RX1__GPIO1_11 */
+       [301] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 6, 0x93c, 0), /* MX35_PAD_TX4_RX1__IPU_CSI_D_3 */
+       [302] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 7, 0x970, 1), /* MX35_PAD_TX4_RX1__KPP_ROW_0 */
+       [303] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 0, 0x0, 0), /* MX35_PAD_TX3_RX2__ESAI_TX3_RX2 */
+       [304] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 1, 0x91c, 0), /* MX35_PAD_TX3_RX2__I2C3_SCL */
+       [305] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 3, 0x0, 0), /* MX35_PAD_TX3_RX2__EMI_NANDF_CE1 */
+       [306] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 5, 0x0, 0), /* MX35_PAD_TX3_RX2__GPIO1_12 */
+       [307] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 6, 0x940, 0), /* MX35_PAD_TX3_RX2__IPU_CSI_D_4 */
+       [308] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 7, 0x974, 1), /* MX35_PAD_TX3_RX2__KPP_ROW_1 */
+       [309] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 0, 0x0, 0), /* MX35_PAD_TX2_RX3__ESAI_TX2_RX3 */
+       [310] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 1, 0x920, 0), /* MX35_PAD_TX2_RX3__I2C3_SDA */
+       [311] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 3, 0x0, 0), /* MX35_PAD_TX2_RX3__EMI_NANDF_CE2 */
+       [312] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 5, 0x0, 0), /* MX35_PAD_TX2_RX3__GPIO1_13 */
+       [313] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 6, 0x944, 0), /* MX35_PAD_TX2_RX3__IPU_CSI_D_5 */
+       [314] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 7, 0x950, 1), /* MX35_PAD_TX2_RX3__KPP_COL_0 */
+       [315] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 0, 0x0, 0), /* MX35_PAD_TX1__ESAI_TX1 */
+       [316] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 1, 0x7d4, 1), /* MX35_PAD_TX1__CCM_PMIC_RDY */
+       [317] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 2, 0x7d8, 2), /* MX35_PAD_TX1__CSPI1_SS2 */
+       [318] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 3, 0x0, 0), /* MX35_PAD_TX1__EMI_NANDF_CE3 */
+       [319] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 4, 0x0, 0), /* MX35_PAD_TX1__UART2_RI */
+       [320] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 5, 0x0, 0), /* MX35_PAD_TX1__GPIO1_14 */
+       [321] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 6, 0x948, 0), /* MX35_PAD_TX1__IPU_CSI_D_6 */
+       [322] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 7, 0x954, 1), /* MX35_PAD_TX1__KPP_COL_1 */
+       [323] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 0, 0x0, 0), /* MX35_PAD_TX0__ESAI_TX0 */
+       [324] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 1, 0x994, 1), /* MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK */
+       [325] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 2, 0x7dc, 0), /* MX35_PAD_TX0__CSPI1_SS3 */
+       [326] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 3, 0x800, 1), /* MX35_PAD_TX0__EMI_DTACK_B */
+       [327] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 4, 0x0, 0), /* MX35_PAD_TX0__UART2_DCD */
+       [328] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 5, 0x0, 0), /* MX35_PAD_TX0__GPIO1_15 */
+       [329] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 6, 0x94c, 0), /* MX35_PAD_TX0__IPU_CSI_D_7 */
+       [330] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 7, 0x958, 1), /* MX35_PAD_TX0__KPP_COL_2 */
+       [331] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 0, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__CSPI1_MOSI */
+       [332] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 5, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__GPIO1_16 */
+       [333] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 7, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 */
+       [334] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 0, 0x0, 0), /* MX35_PAD_CSPI1_MISO__CSPI1_MISO */
+       [335] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 5, 0x0, 0), /* MX35_PAD_CSPI1_MISO__GPIO1_17 */
+       [336] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 7, 0x0, 0), /* MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 */
+       [337] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS0__CSPI1_SS0 */
+       [338] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 1, 0x990, 1), /* MX35_PAD_CSPI1_SS0__OWIRE_LINE */
+       [339] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 2, 0x7fc, 1), /* MX35_PAD_CSPI1_SS0__CSPI2_SS3 */
+       [340] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS0__GPIO1_18 */
+       [341] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 */
+       [342] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS1__CSPI1_SS1 */
+       [343] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 1, 0x0, 0), /* MX35_PAD_CSPI1_SS1__PWM_PWMO */
+       [344] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 2, 0x7d0, 1), /* MX35_PAD_CSPI1_SS1__CCM_CLK32K */
+       [345] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS1__GPIO1_19 */
+       [346] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 6, 0x0, 0), /* MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 */
+       [347] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 */
+       [348] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 0, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__CSPI1_SCLK */
+       [349] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 5, 0x904, 0), /* MX35_PAD_CSPI1_SCLK__GPIO3_4 */
+       [350] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 6, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 */
+       [351] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 7, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 */
+       [352] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 0, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY */
+       [353] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 5, 0x908, 0), /* MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 */
+       [354] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 6, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 */
+       [355] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 7, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 */
+       [356] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 0, 0x0, 0), /* MX35_PAD_RXD1__UART1_RXD_MUX */
+       [357] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 1, 0x7ec, 1), /* MX35_PAD_RXD1__CSPI2_MOSI */
+       [358] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 4, 0x960, 0), /* MX35_PAD_RXD1__KPP_COL_4 */
+       [359] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 5, 0x90c, 0), /* MX35_PAD_RXD1__GPIO3_6 */
+       [360] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 7, 0x0, 0), /* MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 */
+       [361] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 0, 0x0, 0), /* MX35_PAD_TXD1__UART1_TXD_MUX */
+       [362] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 1, 0x7e8, 1), /* MX35_PAD_TXD1__CSPI2_MISO */
+       [363] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 4, 0x964, 0), /* MX35_PAD_TXD1__KPP_COL_5 */
+       [364] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 5, 0x910, 0), /* MX35_PAD_TXD1__GPIO3_7 */
+       [365] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 7, 0x0, 0), /* MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 */
+       [366] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 0, 0x0, 0), /* MX35_PAD_RTS1__UART1_RTS */
+       [367] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 1, 0x7e0, 1), /* MX35_PAD_RTS1__CSPI2_SCLK */
+       [368] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 2, 0x91c, 1), /* MX35_PAD_RTS1__I2C3_SCL */
+       [369] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 3, 0x930, 1), /* MX35_PAD_RTS1__IPU_CSI_D_0 */
+       [370] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 4, 0x968, 0), /* MX35_PAD_RTS1__KPP_COL_6 */
+       [371] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 5, 0x914, 0), /* MX35_PAD_RTS1__GPIO3_8 */
+       [372] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 6, 0x0, 0), /* MX35_PAD_RTS1__EMI_NANDF_CE1 */
+       [373] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 7, 0x0, 0), /* MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 */
+       [374] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 0, 0x0, 0), /* MX35_PAD_CTS1__UART1_CTS */
+       [375] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 1, 0x7e4, 1), /* MX35_PAD_CTS1__CSPI2_RDY */
+       [376] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 2, 0x920, 1), /* MX35_PAD_CTS1__I2C3_SDA */
+       [377] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 3, 0x934, 1), /* MX35_PAD_CTS1__IPU_CSI_D_1 */
+       [378] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 4, 0x96c, 0), /* MX35_PAD_CTS1__KPP_COL_7 */
+       [379] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 5, 0x918, 0), /* MX35_PAD_CTS1__GPIO3_9 */
+       [380] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 6, 0x0, 0), /* MX35_PAD_CTS1__EMI_NANDF_CE2 */
+       [381] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 7, 0x0, 0), /* MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 */
+       [382] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 0, 0x0, 0), /* MX35_PAD_RXD2__UART2_RXD_MUX */
+       [383] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 4, 0x980, 0), /* MX35_PAD_RXD2__KPP_ROW_4 */
+       [384] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 5, 0x8ec, 0), /* MX35_PAD_RXD2__GPIO3_10 */
+       [385] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 0, 0x0, 0), /* MX35_PAD_TXD2__UART2_TXD_MUX */
+       [386] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 1, 0x994, 2), /* MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK */
+       [387] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 4, 0x984, 0), /* MX35_PAD_TXD2__KPP_ROW_5 */
+       [388] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 5, 0x8f0, 0), /* MX35_PAD_TXD2__GPIO3_11 */
+       [389] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 0, 0x0, 0), /* MX35_PAD_RTS2__UART2_RTS */
+       [390] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 1, 0x998, 1), /* MX35_PAD_RTS2__SPDIF_SPDIF_IN1 */
+       [391] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 2, 0x7cc, 1), /* MX35_PAD_RTS2__CAN2_RXCAN */
+       [392] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 3, 0x938, 1), /* MX35_PAD_RTS2__IPU_CSI_D_2 */
+       [393] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 4, 0x988, 0), /* MX35_PAD_RTS2__KPP_ROW_6 */
+       [394] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 5, 0x8f4, 0), /* MX35_PAD_RTS2__GPIO3_12 */
+       [395] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 6, 0x0, 0), /* MX35_PAD_RTS2__AUDMUX_AUD5_RXC */
+       [396] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 7, 0x9a0, 0), /* MX35_PAD_RTS2__UART3_RXD_MUX */
+       [397] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 0, 0x0, 0), /* MX35_PAD_CTS2__UART2_CTS */
+       [398] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 1, 0x0, 0), /* MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 */
+       [399] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 2, 0x0, 0), /* MX35_PAD_CTS2__CAN2_TXCAN */
+       [400] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 3, 0x93c, 1), /* MX35_PAD_CTS2__IPU_CSI_D_3 */
+       [401] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 4, 0x98c, 0), /* MX35_PAD_CTS2__KPP_ROW_7 */
+       [402] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 5, 0x8f8, 0), /* MX35_PAD_CTS2__GPIO3_13 */
+       [403] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 6, 0x0, 0), /* MX35_PAD_CTS2__AUDMUX_AUD5_RXFS */
+       [404] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 7, 0x0, 0), /* MX35_PAD_CTS2__UART3_TXD_MUX */
+       [405] = IMX_PIN_REG(MX35_PAD_RTCK, 0x5ec, 0x0, 0, 0x0, 0), /* MX35_PAD_RTCK__ARM11P_TOP_RTCK */
+       [406] = IMX_PIN_REG(MX35_PAD_TCK, 0x5f0, 0x0, 0, 0x0, 0), /* MX35_PAD_TCK__SJC_TCK */
+       [407] = IMX_PIN_REG(MX35_PAD_TMS, 0x5f4, 0x0, 0, 0x0, 0), /* MX35_PAD_TMS__SJC_TMS */
+       [408] = IMX_PIN_REG(MX35_PAD_TDI, 0x5f8, 0x0, 0, 0x0, 0), /* MX35_PAD_TDI__SJC_TDI */
+       [409] = IMX_PIN_REG(MX35_PAD_TDO, 0x5fc, 0x0, 0, 0x0, 0), /* MX35_PAD_TDO__SJC_TDO */
+       [410] = IMX_PIN_REG(MX35_PAD_TRSTB, 0x600, 0x0, 0, 0x0, 0), /* MX35_PAD_TRSTB__SJC_TRSTB */
+       [411] = IMX_PIN_REG(MX35_PAD_DE_B, 0x604, 0x0, 0, 0x0, 0), /* MX35_PAD_DE_B__SJC_DE_B */
+       [412] = IMX_PIN_REG(MX35_PAD_SJC_MOD, 0x608, 0x0, 0, 0x0, 0), /* MX35_PAD_SJC_MOD__SJC_MOD */
+       [413] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 0, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR */
+       [414] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 1, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR */
+       [415] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 5, 0x8fc, 0), /* MX35_PAD_USBOTG_PWR__GPIO3_14 */
+       [416] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 0, 0x0, 0), /* MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC */
+       [417] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 1, 0x9f4, 1), /* MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC */
+       [418] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 5, 0x900, 0), /* MX35_PAD_USBOTG_OC__GPIO3_15 */
+       [419] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 0, 0x0, 0), /* MX35_PAD_LD0__IPU_DISPB_DAT_0 */
+       [420] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 5, 0x868, 1), /* MX35_PAD_LD0__GPIO2_0 */
+       [421] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 6, 0x0, 0), /* MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 */
+       [422] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 0, 0x0, 0), /* MX35_PAD_LD1__IPU_DISPB_DAT_1 */
+       [423] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 5, 0x894, 0), /* MX35_PAD_LD1__GPIO2_1 */
+       [424] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 6, 0x0, 0), /* MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 */
+       [425] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 0, 0x0, 0), /* MX35_PAD_LD2__IPU_DISPB_DAT_2 */
+       [426] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 5, 0x8c0, 0), /* MX35_PAD_LD2__GPIO2_2 */
+       [427] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 6, 0x0, 0), /* MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 */
+       [428] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 0, 0x0, 0), /* MX35_PAD_LD3__IPU_DISPB_DAT_3 */
+       [429] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 5, 0x8cc, 0), /* MX35_PAD_LD3__GPIO2_3 */
+       [430] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 6, 0x0, 0), /* MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 */
+       [431] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 0, 0x0, 0), /* MX35_PAD_LD4__IPU_DISPB_DAT_4 */
+       [432] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 5, 0x8d0, 0), /* MX35_PAD_LD4__GPIO2_4 */
+       [433] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 6, 0x0, 0), /* MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 */
+       [434] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 0, 0x0, 0), /* MX35_PAD_LD5__IPU_DISPB_DAT_5 */
+       [435] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 5, 0x8d4, 0), /* MX35_PAD_LD5__GPIO2_5 */
+       [436] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 6, 0x0, 0), /* MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 */
+       [437] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 0, 0x0, 0), /* MX35_PAD_LD6__IPU_DISPB_DAT_6 */
+       [438] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 5, 0x8d8, 0), /* MX35_PAD_LD6__GPIO2_6 */
+       [439] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 6, 0x0, 0), /* MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 */
+       [440] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 0, 0x0, 0), /* MX35_PAD_LD7__IPU_DISPB_DAT_7 */
+       [441] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 5, 0x8dc, 0), /* MX35_PAD_LD7__GPIO2_7 */
+       [442] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 6, 0x0, 0), /* MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 */
+       [443] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 0, 0x0, 0), /* MX35_PAD_LD8__IPU_DISPB_DAT_8 */
+       [444] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 5, 0x8e0, 0), /* MX35_PAD_LD8__GPIO2_8 */
+       [445] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 6, 0x0, 0), /* MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 */
+       [446] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 0, 0x0, 0), /* MX35_PAD_LD9__IPU_DISPB_DAT_9 */
+       [447] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 5, 0x8e4, 0), /* MX35_PAD_LD9__GPIO2_9 */
+       [448] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 6, 0x0, 0), /* MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 */
+       [449] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 0, 0x0, 0), /* MX35_PAD_LD10__IPU_DISPB_DAT_10 */
+       [450] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 5, 0x86c, 0), /* MX35_PAD_LD10__GPIO2_10 */
+       [451] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 6, 0x0, 0), /* MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 */
+       [452] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 0, 0x0, 0), /* MX35_PAD_LD11__IPU_DISPB_DAT_11 */
+       [453] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 5, 0x870, 0), /* MX35_PAD_LD11__GPIO2_11 */
+       [454] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 6, 0x0, 0), /* MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 */
+       [455] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 7, 0x0, 0), /* MX35_PAD_LD11__ARM11P_TOP_TRACE_4 */
+       [456] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 0, 0x0, 0), /* MX35_PAD_LD12__IPU_DISPB_DAT_12 */
+       [457] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 5, 0x874, 0), /* MX35_PAD_LD12__GPIO2_12 */
+       [458] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 6, 0x0, 0), /* MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 */
+       [459] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 7, 0x0, 0), /* MX35_PAD_LD12__ARM11P_TOP_TRACE_5 */
+       [460] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 0, 0x0, 0), /* MX35_PAD_LD13__IPU_DISPB_DAT_13 */
+       [461] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 5, 0x878, 0), /* MX35_PAD_LD13__GPIO2_13 */
+       [462] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 6, 0x0, 0), /* MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 */
+       [463] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 7, 0x0, 0), /* MX35_PAD_LD13__ARM11P_TOP_TRACE_6 */
+       [464] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 0, 0x0, 0), /* MX35_PAD_LD14__IPU_DISPB_DAT_14 */
+       [465] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 5, 0x87c, 0), /* MX35_PAD_LD14__GPIO2_14 */
+       [466] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 6, 0x0, 0), /* MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 */
+       [467] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 7, 0x0, 0), /* MX35_PAD_LD14__ARM11P_TOP_TRACE_7 */
+       [468] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 0, 0x0, 0), /* MX35_PAD_LD15__IPU_DISPB_DAT_15 */
+       [469] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 5, 0x880, 0), /* MX35_PAD_LD15__GPIO2_15 */
+       [470] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 6, 0x0, 0), /* MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 */
+       [471] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 7, 0x0, 0), /* MX35_PAD_LD15__ARM11P_TOP_TRACE_8 */
+       [472] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 0, 0x0, 0), /* MX35_PAD_LD16__IPU_DISPB_DAT_16 */
+       [473] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 2, 0x928, 0), /* MX35_PAD_LD16__IPU_DISPB_D12_VSYNC */
+       [474] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 5, 0x884, 0), /* MX35_PAD_LD16__GPIO2_16 */
+       [475] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 6, 0x0, 0), /* MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 */
+       [476] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 7, 0x0, 0), /* MX35_PAD_LD16__ARM11P_TOP_TRACE_9 */
+       [477] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 0, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_DAT_17 */
+       [478] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 2, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_CS2 */
+       [479] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 5, 0x888, 0), /* MX35_PAD_LD17__GPIO2_17 */
+       [480] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 6, 0x0, 0), /* MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 */
+       [481] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 7, 0x0, 0), /* MX35_PAD_LD17__ARM11P_TOP_TRACE_10 */
+       [482] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 0, 0x0, 0), /* MX35_PAD_LD18__IPU_DISPB_DAT_18 */
+       [483] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 1, 0x924, 1), /* MX35_PAD_LD18__IPU_DISPB_D0_VSYNC */
+       [484] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 2, 0x928, 1), /* MX35_PAD_LD18__IPU_DISPB_D12_VSYNC */
+       [485] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 3, 0x818, 0), /* MX35_PAD_LD18__ESDHC3_CMD */
+       [486] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 4, 0x9b0, 0), /* MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 */
+       [487] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 5, 0x0, 0), /* MX35_PAD_LD18__GPIO3_24 */
+       [488] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 6, 0x0, 0), /* MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 */
+       [489] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 7, 0x0, 0), /* MX35_PAD_LD18__ARM11P_TOP_TRACE_11 */
+       [490] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 0, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_DAT_19 */
+       [491] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 1, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_BCLK */
+       [492] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 2, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_CS1 */
+       [493] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 3, 0x814, 0), /* MX35_PAD_LD19__ESDHC3_CLK */
+       [494] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 4, 0x9c4, 0), /* MX35_PAD_LD19__USB_TOP_USBOTG_DIR */
+       [495] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 5, 0x0, 0), /* MX35_PAD_LD19__GPIO3_25 */
+       [496] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 6, 0x0, 0), /* MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 */
+       [497] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 7, 0x0, 0), /* MX35_PAD_LD19__ARM11P_TOP_TRACE_12 */
+       [498] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 0, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_DAT_20 */
+       [499] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 1, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_CS0 */
+       [500] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 2, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_SD_CLK */
+       [501] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 3, 0x81c, 0), /* MX35_PAD_LD20__ESDHC3_DAT0 */
+       [502] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 5, 0x0, 0), /* MX35_PAD_LD20__GPIO3_26 */
+       [503] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 6, 0x0, 0), /* MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 */
+       [504] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 7, 0x0, 0), /* MX35_PAD_LD20__ARM11P_TOP_TRACE_13 */
+       [505] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 0, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_DAT_21 */
+       [506] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 1, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_PAR_RS */
+       [507] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 2, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_SER_RS */
+       [508] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 3, 0x820, 0), /* MX35_PAD_LD21__ESDHC3_DAT1 */
+       [509] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 4, 0x0, 0), /* MX35_PAD_LD21__USB_TOP_USBOTG_STP */
+       [510] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 5, 0x0, 0), /* MX35_PAD_LD21__GPIO3_27 */
+       [511] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 6, 0x0, 0), /* MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL */
+       [512] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 7, 0x0, 0), /* MX35_PAD_LD21__ARM11P_TOP_TRACE_14 */
+       [513] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 0, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_DAT_22 */
+       [514] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 1, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_WR */
+       [515] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 2, 0x92c, 0), /* MX35_PAD_LD22__IPU_DISPB_SD_D_I */
+       [516] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 3, 0x824, 0), /* MX35_PAD_LD22__ESDHC3_DAT2 */
+       [517] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 4, 0x9c8, 0), /* MX35_PAD_LD22__USB_TOP_USBOTG_NXT */
+       [518] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 5, 0x0, 0), /* MX35_PAD_LD22__GPIO3_28 */
+       [519] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 6, 0x0, 0), /* MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR */
+       [520] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 7, 0x0, 0), /* MX35_PAD_LD22__ARM11P_TOP_TRCTL */
+       [521] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 0, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_DAT_23 */
+       [522] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 1, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_RD */
+       [523] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 2, 0x92c, 1), /* MX35_PAD_LD23__IPU_DISPB_SD_D_IO */
+       [524] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 3, 0x828, 0), /* MX35_PAD_LD23__ESDHC3_DAT3 */
+       [525] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 4, 0x9c0, 0), /* MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 */
+       [526] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 5, 0x0, 0), /* MX35_PAD_LD23__GPIO3_29 */
+       [527] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 6, 0x0, 0), /* MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS */
+       [528] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 7, 0x0, 0), /* MX35_PAD_LD23__ARM11P_TOP_TRCLK */
+       [529] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 0, 0x0, 0), /* MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC */
+       [530] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 2, 0x92c, 2), /* MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO */
+       [531] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 5, 0x0, 0), /* MX35_PAD_D3_HSYNC__GPIO3_30 */
+       [532] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 6, 0x0, 0), /* MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE */
+       [533] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 7, 0x0, 0), /* MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 */
+       [534] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 0, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK */
+       [535] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 2, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK */
+       [536] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 5, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__GPIO3_31 */
+       [537] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 6, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 */
+       [538] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 7, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 */
+       [539] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 0, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY */
+       [540] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 2, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O */
+       [541] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 5, 0x82c, 2), /* MX35_PAD_D3_DRDY__GPIO1_0 */
+       [542] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 6, 0x0, 0), /* MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 */
+       [543] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 7, 0x0, 0), /* MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 */
+       [544] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 0, 0x0, 0), /* MX35_PAD_CONTRAST__IPU_DISPB_CONTR */
+       [545] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 5, 0x838, 2), /* MX35_PAD_CONTRAST__GPIO1_1 */
+       [546] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 6, 0x0, 0), /* MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 */
+       [547] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 7, 0x0, 0), /* MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 */
+       [548] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 0, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC */
+       [549] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 2, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 */
+       [550] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 5, 0x848, 1), /* MX35_PAD_D3_VSYNC__GPIO1_2 */
+       [551] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 6, 0x0, 0), /* MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD */
+       [552] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 7, 0x0, 0), /* MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 */
+       [553] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 0, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_D3_REV */
+       [554] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 2, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_SER_RS */
+       [555] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 5, 0x84c, 1), /* MX35_PAD_D3_REV__GPIO1_3 */
+       [556] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 6, 0x0, 0), /* MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB */
+       [557] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 7, 0x0, 0), /* MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 */
+       [558] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 0, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS */
+       [559] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 2, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_CS2 */
+       [560] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 5, 0x850, 2), /* MX35_PAD_D3_CLS__GPIO1_4 */
+       [561] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 6, 0x0, 0), /* MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 */
+       [562] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 7, 0x0, 0), /* MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 */
+       [563] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 0, 0x0, 0), /* MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL */
+       [564] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 2, 0x928, 2), /* MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC */
+       [565] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 5, 0x854, 2), /* MX35_PAD_D3_SPL__GPIO1_5 */
+       [566] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 6, 0x0, 0), /* MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 */
+       [567] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 7, 0x0, 0), /* MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 */
+       [568] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 0, 0x0, 0), /* MX35_PAD_SD1_CMD__ESDHC1_CMD */
+       [569] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 1, 0x0, 0), /* MX35_PAD_SD1_CMD__MSHC_SCLK */
+       [570] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 3, 0x924, 2), /* MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC */
+       [571] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 4, 0x9b4, 0), /* MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 */
+       [572] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 5, 0x858, 2), /* MX35_PAD_SD1_CMD__GPIO1_6 */
+       [573] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 7, 0x0, 0), /* MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL */
+       [574] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 0, 0x0, 0), /* MX35_PAD_SD1_CLK__ESDHC1_CLK */
+       [575] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 1, 0x0, 0), /* MX35_PAD_SD1_CLK__MSHC_BS */
+       [576] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 3, 0x0, 0), /* MX35_PAD_SD1_CLK__IPU_DISPB_BCLK */
+       [577] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 4, 0x9b8, 0), /* MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 */
+       [578] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 5, 0x85c, 2), /* MX35_PAD_SD1_CLK__GPIO1_7 */
+       [579] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 7, 0x0, 0), /* MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK */
+       [580] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 0, 0x0, 0), /* MX35_PAD_SD1_DATA0__ESDHC1_DAT0 */
+       [581] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 1, 0x0, 0), /* MX35_PAD_SD1_DATA0__MSHC_DATA_0 */
+       [582] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 3, 0x0, 0), /* MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 */
+       [583] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 4, 0x9bc, 0), /* MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 */
+       [584] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 5, 0x860, 2), /* MX35_PAD_SD1_DATA0__GPIO1_8 */
+       [585] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 7, 0x0, 0), /* MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 */
+       [586] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 0, 0x0, 0), /* MX35_PAD_SD1_DATA1__ESDHC1_DAT1 */
+       [587] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 1, 0x0, 0), /* MX35_PAD_SD1_DATA1__MSHC_DATA_1 */
+       [588] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 3, 0x0, 0), /* MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS */
+       [589] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 4, 0x9a4, 0), /* MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 */
+       [590] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 5, 0x864, 1), /* MX35_PAD_SD1_DATA1__GPIO1_9 */
+       [591] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 7, 0x0, 0), /* MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 */
+       [592] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 0, 0x0, 0), /* MX35_PAD_SD1_DATA2__ESDHC1_DAT2 */
+       [593] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 1, 0x0, 0), /* MX35_PAD_SD1_DATA2__MSHC_DATA_2 */
+       [594] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 3, 0x0, 0), /* MX35_PAD_SD1_DATA2__IPU_DISPB_WR */
+       [595] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 4, 0x9a8, 0), /* MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 */
+       [596] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 5, 0x830, 1), /* MX35_PAD_SD1_DATA2__GPIO1_10 */
+       [597] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 7, 0x0, 0), /* MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 */
+       [598] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 0, 0x0, 0), /* MX35_PAD_SD1_DATA3__ESDHC1_DAT3 */
+       [599] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 1, 0x0, 0), /* MX35_PAD_SD1_DATA3__MSHC_DATA_3 */
+       [600] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 3, 0x0, 0), /* MX35_PAD_SD1_DATA3__IPU_DISPB_RD */
+       [601] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 4, 0x9ac, 0), /* MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 */
+       [602] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 5, 0x834, 1), /* MX35_PAD_SD1_DATA3__GPIO1_11 */
+       [603] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 7, 0x0, 0), /* MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 */
+       [604] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 0, 0x0, 0), /* MX35_PAD_SD2_CMD__ESDHC2_CMD */
+       [605] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 1, 0x91c, 2), /* MX35_PAD_SD2_CMD__I2C3_SCL */
+       [606] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 2, 0x804, 0), /* MX35_PAD_SD2_CMD__ESDHC1_DAT4 */
+       [607] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 3, 0x938, 2), /* MX35_PAD_SD2_CMD__IPU_CSI_D_2 */
+       [608] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 4, 0x9dc, 0), /* MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 */
+       [609] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 5, 0x868, 2), /* MX35_PAD_SD2_CMD__GPIO2_0 */
+       [610] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 6, 0x0, 0), /* MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 */
+       [611] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 7, 0x928, 3), /* MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC */
+       [612] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 0, 0x0, 0), /* MX35_PAD_SD2_CLK__ESDHC2_CLK */
+       [613] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 1, 0x920, 2), /* MX35_PAD_SD2_CLK__I2C3_SDA */
+       [614] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 2, 0x808, 0), /* MX35_PAD_SD2_CLK__ESDHC1_DAT5 */
+       [615] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 3, 0x93c, 2), /* MX35_PAD_SD2_CLK__IPU_CSI_D_3 */
+       [616] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 4, 0x9e0, 0), /* MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 */
+       [617] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 5, 0x894, 1), /* MX35_PAD_SD2_CLK__GPIO2_1 */
+       [618] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 6, 0x998, 2), /* MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 */
+       [619] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 7, 0x0, 0), /* MX35_PAD_SD2_CLK__IPU_DISPB_CS2 */
+       [620] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 0, 0x0, 0), /* MX35_PAD_SD2_DATA0__ESDHC2_DAT0 */
+       [621] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 1, 0x9a0, 1), /* MX35_PAD_SD2_DATA0__UART3_RXD_MUX */
+       [622] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 2, 0x80c, 0), /* MX35_PAD_SD2_DATA0__ESDHC1_DAT6 */
+       [623] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 3, 0x940, 1), /* MX35_PAD_SD2_DATA0__IPU_CSI_D_4 */
+       [624] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 4, 0x9e4, 0), /* MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 */
+       [625] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 5, 0x8c0, 1), /* MX35_PAD_SD2_DATA0__GPIO2_2 */
+       [626] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 6, 0x994, 3), /* MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK */
+       [627] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 0, 0x0, 0), /* MX35_PAD_SD2_DATA1__ESDHC2_DAT1 */
+       [628] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 1, 0x0, 0), /* MX35_PAD_SD2_DATA1__UART3_TXD_MUX */
+       [629] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 2, 0x810, 0), /* MX35_PAD_SD2_DATA1__ESDHC1_DAT7 */
+       [630] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 3, 0x944, 1), /* MX35_PAD_SD2_DATA1__IPU_CSI_D_5 */
+       [631] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 4, 0x9cc, 0), /* MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 */
+       [632] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 5, 0x8cc, 1), /* MX35_PAD_SD2_DATA1__GPIO2_3 */
+       [633] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 0, 0x0, 0), /* MX35_PAD_SD2_DATA2__ESDHC2_DAT2 */
+       [634] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 1, 0x99c, 0), /* MX35_PAD_SD2_DATA2__UART3_RTS */
+       [635] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 2, 0x7c8, 1), /* MX35_PAD_SD2_DATA2__CAN1_RXCAN */
+       [636] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 3, 0x948, 1), /* MX35_PAD_SD2_DATA2__IPU_CSI_D_6 */
+       [637] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 4, 0x9d0, 0), /* MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 */
+       [638] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 5, 0x8d0, 1), /* MX35_PAD_SD2_DATA2__GPIO2_4 */
+       [639] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 0, 0x0, 0), /* MX35_PAD_SD2_DATA3__ESDHC2_DAT3 */
+       [640] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 1, 0x0, 0), /* MX35_PAD_SD2_DATA3__UART3_CTS */
+       [641] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 2, 0x0, 0), /* MX35_PAD_SD2_DATA3__CAN1_TXCAN */
+       [642] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 3, 0x94c, 1), /* MX35_PAD_SD2_DATA3__IPU_CSI_D_7 */
+       [643] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 4, 0x9d4, 0), /* MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 */
+       [644] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 5, 0x8d4, 1), /* MX35_PAD_SD2_DATA3__GPIO2_5 */
+       [645] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 0, 0x0, 0), /* MX35_PAD_ATA_CS0__ATA_CS0 */
+       [646] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 1, 0x7dc, 1), /* MX35_PAD_ATA_CS0__CSPI1_SS3 */
+       [647] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 3, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DISPB_CS1 */
+       [648] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 5, 0x8d8, 1), /* MX35_PAD_ATA_CS0__GPIO2_6 */
+       [649] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 6, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DIAGB_0 */
+       [650] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 7, 0x0, 0), /* MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 */
+       [651] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 0, 0x0, 0), /* MX35_PAD_ATA_CS1__ATA_CS1 */
+       [652] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 3, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DISPB_CS2 */
+       [653] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 4, 0x7f0, 1), /* MX35_PAD_ATA_CS1__CSPI2_SS0 */
+       [654] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 5, 0x8dc, 1), /* MX35_PAD_ATA_CS1__GPIO2_7 */
+       [655] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 6, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DIAGB_1 */
+       [656] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 7, 0x0, 0), /* MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 */
+       [657] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 0, 0x0, 0), /* MX35_PAD_ATA_DIOR__ATA_DIOR */
+       [658] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 1, 0x81c, 1), /* MX35_PAD_ATA_DIOR__ESDHC3_DAT0 */
+       [659] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 2, 0x9c4, 1), /* MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR */
+       [660] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 3, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 */
+       [661] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 4, 0x7f4, 1), /* MX35_PAD_ATA_DIOR__CSPI2_SS1 */
+       [662] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 5, 0x8e0, 1), /* MX35_PAD_ATA_DIOR__GPIO2_8 */
+       [663] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 6, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DIAGB_2 */
+       [664] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 7, 0x0, 0), /* MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 */
+       [665] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 0, 0x0, 0), /* MX35_PAD_ATA_DIOW__ATA_DIOW */
+       [666] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 1, 0x820, 1), /* MX35_PAD_ATA_DIOW__ESDHC3_DAT1 */
+       [667] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 2, 0x0, 0), /* MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP */
+       [668] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 3, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 */
+       [669] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 4, 0x7ec, 2), /* MX35_PAD_ATA_DIOW__CSPI2_MOSI */
+       [670] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 5, 0x8e4, 1), /* MX35_PAD_ATA_DIOW__GPIO2_9 */
+       [671] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 6, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DIAGB_3 */
+       [672] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 7, 0x0, 0), /* MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 */
+       [673] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 0, 0x0, 0), /* MX35_PAD_ATA_DMACK__ATA_DMACK */
+       [674] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 1, 0x824, 1), /* MX35_PAD_ATA_DMACK__ESDHC3_DAT2 */
+       [675] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 2, 0x9c8, 1), /* MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT */
+       [676] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 4, 0x7e8, 2), /* MX35_PAD_ATA_DMACK__CSPI2_MISO */
+       [677] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 5, 0x86c, 1), /* MX35_PAD_ATA_DMACK__GPIO2_10 */
+       [678] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 6, 0x0, 0), /* MX35_PAD_ATA_DMACK__IPU_DIAGB_4 */
+       [679] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 7, 0x0, 0), /* MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 */
+       [680] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 0, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ATA_RESET_B */
+       [681] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 1, 0x828, 1), /* MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 */
+       [682] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 2, 0x9a4, 1), /* MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 */
+       [683] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 3, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O */
+       [684] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 4, 0x7e4, 2), /* MX35_PAD_ATA_RESET_B__CSPI2_RDY */
+       [685] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 5, 0x870, 1), /* MX35_PAD_ATA_RESET_B__GPIO2_11 */
+       [686] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 6, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 */
+       [687] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 7, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 */
+       [688] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 0, 0x0, 0), /* MX35_PAD_ATA_IORDY__ATA_IORDY */
+       [689] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 1, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC3_DAT4 */
+       [690] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 2, 0x9a8, 1), /* MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 */
+       [691] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 3, 0x92c, 3), /* MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO */
+       [692] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 4, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC2_DAT4 */
+       [693] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 5, 0x874, 1), /* MX35_PAD_ATA_IORDY__GPIO2_12 */
+       [694] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 6, 0x0, 0), /* MX35_PAD_ATA_IORDY__IPU_DIAGB_6 */
+       [695] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 7, 0x0, 0), /* MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 */
+       [696] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA0__ATA_DATA_0 */
+       [697] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 1, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC3_DAT5 */
+       [698] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 2, 0x9ac, 1), /* MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 */
+       [699] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 3, 0x928, 4), /* MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC */
+       [700] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 4, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC2_DAT5 */
+       [701] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 5, 0x878, 1), /* MX35_PAD_ATA_DATA0__GPIO2_13 */
+       [702] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA0__IPU_DIAGB_7 */
+       [703] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 */
+       [704] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 0, 0x0, 0), /* MX35_PAD_ATA_DATA1__ATA_DATA_1 */
+       [705] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 1, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC3_DAT6 */
+       [706] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 2, 0x9b0, 1), /* MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 */
+       [707] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 3, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK */
+       [708] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 4, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC2_DAT6 */
+       [709] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 5, 0x87c, 1), /* MX35_PAD_ATA_DATA1__GPIO2_14 */
+       [710] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 6, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DIAGB_8 */
+       [711] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 7, 0x0, 0), /* MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 */
+       [712] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 0, 0x0, 0), /* MX35_PAD_ATA_DATA2__ATA_DATA_2 */
+       [713] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 1, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC3_DAT7 */
+       [714] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 2, 0x9b4, 1), /* MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 */
+       [715] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 3, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS */
+       [716] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 4, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC2_DAT7 */
+       [717] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 5, 0x880, 1), /* MX35_PAD_ATA_DATA2__GPIO2_15 */
+       [718] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 6, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DIAGB_9 */
+       [719] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 7, 0x0, 0), /* MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 */
+       [720] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 0, 0x0, 0), /* MX35_PAD_ATA_DATA3__ATA_DATA_3 */
+       [721] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 1, 0x814, 1), /* MX35_PAD_ATA_DATA3__ESDHC3_CLK */
+       [722] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 2, 0x9b8, 1), /* MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 */
+       [723] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 4, 0x7e0, 2), /* MX35_PAD_ATA_DATA3__CSPI2_SCLK */
+       [724] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 5, 0x884, 1), /* MX35_PAD_ATA_DATA3__GPIO2_16 */
+       [725] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 6, 0x0, 0), /* MX35_PAD_ATA_DATA3__IPU_DIAGB_10 */
+       [726] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 7, 0x0, 0), /* MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 */
+       [727] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA4__ATA_DATA_4 */
+       [728] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 1, 0x818, 1), /* MX35_PAD_ATA_DATA4__ESDHC3_CMD */
+       [729] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 2, 0x9bc, 1), /* MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 */
+       [730] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 5, 0x888, 1), /* MX35_PAD_ATA_DATA4__GPIO2_17 */
+       [731] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA4__IPU_DIAGB_11 */
+       [732] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 */
+       [733] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 0, 0x0, 0), /* MX35_PAD_ATA_DATA5__ATA_DATA_5 */
+       [734] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 2, 0x9c0, 1), /* MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 */
+       [735] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 5, 0x88c, 1), /* MX35_PAD_ATA_DATA5__GPIO2_18 */
+       [736] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 6, 0x0, 0), /* MX35_PAD_ATA_DATA5__IPU_DIAGB_12 */
+       [737] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 7, 0x0, 0), /* MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 */
+       [738] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 0, 0x0, 0), /* MX35_PAD_ATA_DATA6__ATA_DATA_6 */
+       [739] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 1, 0x0, 0), /* MX35_PAD_ATA_DATA6__CAN1_TXCAN */
+       [740] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 2, 0x0, 0), /* MX35_PAD_ATA_DATA6__UART1_DTR */
+       [741] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 3, 0x7b4, 0), /* MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD */
+       [742] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 5, 0x890, 1), /* MX35_PAD_ATA_DATA6__GPIO2_19 */
+       [743] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 6, 0x0, 0), /* MX35_PAD_ATA_DATA6__IPU_DIAGB_13 */
+       [744] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 0, 0x0, 0), /* MX35_PAD_ATA_DATA7__ATA_DATA_7 */
+       [745] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 1, 0x7c8, 2), /* MX35_PAD_ATA_DATA7__CAN1_RXCAN */
+       [746] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 2, 0x0, 0), /* MX35_PAD_ATA_DATA7__UART1_DSR */
+       [747] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 3, 0x7b0, 0), /* MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD */
+       [748] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 5, 0x898, 1), /* MX35_PAD_ATA_DATA7__GPIO2_20 */
+       [749] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 6, 0x0, 0), /* MX35_PAD_ATA_DATA7__IPU_DIAGB_14 */
+       [750] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA8__ATA_DATA_8 */
+       [751] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 1, 0x99c, 1), /* MX35_PAD_ATA_DATA8__UART3_RTS */
+       [752] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 2, 0x0, 0), /* MX35_PAD_ATA_DATA8__UART1_RI */
+       [753] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 3, 0x7c0, 0), /* MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC */
+       [754] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 5, 0x89c, 1), /* MX35_PAD_ATA_DATA8__GPIO2_21 */
+       [755] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA8__IPU_DIAGB_15 */
+       [756] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA9__ATA_DATA_9 */
+       [757] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 1, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART3_CTS */
+       [758] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 2, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART1_DCD */
+       [759] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 3, 0x7c4, 0), /* MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS */
+       [760] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 5, 0x8a0, 1), /* MX35_PAD_ATA_DATA9__GPIO2_22 */
+       [761] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA9__IPU_DIAGB_16 */
+       [762] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA10__ATA_DATA_10 */
+       [763] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 1, 0x9a0, 2), /* MX35_PAD_ATA_DATA10__UART3_RXD_MUX */
+       [764] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 3, 0x7b8, 0), /* MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC */
+       [765] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 5, 0x8a4, 1), /* MX35_PAD_ATA_DATA10__GPIO2_23 */
+       [766] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA10__IPU_DIAGB_17 */
+       [767] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA11__ATA_DATA_11 */
+       [768] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 1, 0x0, 0), /* MX35_PAD_ATA_DATA11__UART3_TXD_MUX */
+       [769] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 3, 0x7bc, 0), /* MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS */
+       [770] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 5, 0x8a8, 1), /* MX35_PAD_ATA_DATA11__GPIO2_24 */
+       [771] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA11__IPU_DIAGB_18 */
+       [772] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 0, 0x0, 0), /* MX35_PAD_ATA_DATA12__ATA_DATA_12 */
+       [773] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 1, 0x91c, 3), /* MX35_PAD_ATA_DATA12__I2C3_SCL */
+       [774] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 5, 0x8ac, 1), /* MX35_PAD_ATA_DATA12__GPIO2_25 */
+       [775] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 6, 0x0, 0), /* MX35_PAD_ATA_DATA12__IPU_DIAGB_19 */
+       [776] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA13__ATA_DATA_13 */
+       [777] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 1, 0x920, 3), /* MX35_PAD_ATA_DATA13__I2C3_SDA */
+       [778] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 5, 0x8b0, 1), /* MX35_PAD_ATA_DATA13__GPIO2_26 */
+       [779] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA13__IPU_DIAGB_20 */
+       [780] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA14__ATA_DATA_14 */
+       [781] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 1, 0x930, 2), /* MX35_PAD_ATA_DATA14__IPU_CSI_D_0 */
+       [782] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 3, 0x970, 2), /* MX35_PAD_ATA_DATA14__KPP_ROW_0 */
+       [783] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 5, 0x8b4, 1), /* MX35_PAD_ATA_DATA14__GPIO2_27 */
+       [784] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA14__IPU_DIAGB_21 */
+       [785] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA15__ATA_DATA_15 */
+       [786] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 1, 0x934, 2), /* MX35_PAD_ATA_DATA15__IPU_CSI_D_1 */
+       [787] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 3, 0x974, 2), /* MX35_PAD_ATA_DATA15__KPP_ROW_1 */
+       [788] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 5, 0x8b8, 1), /* MX35_PAD_ATA_DATA15__GPIO2_28 */
+       [789] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA15__IPU_DIAGB_22 */
+       [790] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 0, 0x0, 0), /* MX35_PAD_ATA_INTRQ__ATA_INTRQ */
+       [791] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 1, 0x938, 3), /* MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 */
+       [792] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 3, 0x978, 2), /* MX35_PAD_ATA_INTRQ__KPP_ROW_2 */
+       [793] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 5, 0x8bc, 1), /* MX35_PAD_ATA_INTRQ__GPIO2_29 */
+       [794] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 6, 0x0, 0), /* MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 */
+       [795] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 0, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN */
+       [796] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 1, 0x93c, 3), /* MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 */
+       [797] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 3, 0x97c, 2), /* MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 */
+       [798] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 5, 0x8c4, 1), /* MX35_PAD_ATA_BUFF_EN__GPIO2_30 */
+       [799] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 6, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 */
+       [800] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 0, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ATA_DMARQ */
+       [801] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 1, 0x940, 2), /* MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 */
+       [802] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 3, 0x950, 2), /* MX35_PAD_ATA_DMARQ__KPP_COL_0 */
+       [803] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 5, 0x8c8, 1), /* MX35_PAD_ATA_DMARQ__GPIO2_31 */
+       [804] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 6, 0x0, 0), /* MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 */
+       [805] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 7, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 */
+       [806] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 0, 0x0, 0), /* MX35_PAD_ATA_DA0__ATA_DA_0 */
+       [807] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 1, 0x944, 2), /* MX35_PAD_ATA_DA0__IPU_CSI_D_5 */
+       [808] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 3, 0x954, 2), /* MX35_PAD_ATA_DA0__KPP_COL_1 */
+       [809] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 5, 0x8e8, 1), /* MX35_PAD_ATA_DA0__GPIO3_0 */
+       [810] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 6, 0x0, 0), /* MX35_PAD_ATA_DA0__IPU_DIAGB_26 */
+       [811] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 7, 0x0, 0), /* MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 */
+       [812] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 0, 0x0, 0), /* MX35_PAD_ATA_DA1__ATA_DA_1 */
+       [813] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 1, 0x948, 2), /* MX35_PAD_ATA_DA1__IPU_CSI_D_6 */
+       [814] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 3, 0x958, 2), /* MX35_PAD_ATA_DA1__KPP_COL_2 */
+       [815] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 5, 0x0, 0), /* MX35_PAD_ATA_DA1__GPIO3_1 */
+       [816] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 6, 0x0, 0), /* MX35_PAD_ATA_DA1__IPU_DIAGB_27 */
+       [817] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 7, 0x0, 0), /* MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 */
+       [818] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 0, 0x0, 0), /* MX35_PAD_ATA_DA2__ATA_DA_2 */
+       [819] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 1, 0x94c, 2), /* MX35_PAD_ATA_DA2__IPU_CSI_D_7 */
+       [820] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 3, 0x95c, 2), /* MX35_PAD_ATA_DA2__KPP_COL_3 */
+       [821] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 5, 0x0, 0), /* MX35_PAD_ATA_DA2__GPIO3_2 */
+       [822] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 6, 0x0, 0), /* MX35_PAD_ATA_DA2__IPU_DIAGB_28 */
+       [823] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 7, 0x0, 0), /* MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 */
+       [824] = IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 0, 0x0, 0), /* MX35_PAD_MLB_CLK__MLB_MLBCLK */
+       [825] = IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 5, 0x0, 0), /* MX35_PAD_MLB_CLK__GPIO3_3 */
+       [826] = IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 0, 0x0, 0), /* MX35_PAD_MLB_DAT__MLB_MLBDAT */
+       [827] = IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 5, 0x904, 1), /* MX35_PAD_MLB_DAT__GPIO3_4 */
+       [828] = IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 0, 0x0, 0), /* MX35_PAD_MLB_SIG__MLB_MLBSIG */
+       [829] = IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 5, 0x908, 1), /* MX35_PAD_MLB_SIG__GPIO3_5 */
+       [830] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 0, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__FEC_TX_CLK */
+       [831] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 1, 0x804, 1), /* MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 */
+       [832] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 2, 0x9a0, 3), /* MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX */
+       [833] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 3, 0x9ec, 1), /* MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR */
+       [834] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 4, 0x7ec, 3), /* MX35_PAD_FEC_TX_CLK__CSPI2_MOSI */
+       [835] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 5, 0x90c, 1), /* MX35_PAD_FEC_TX_CLK__GPIO3_6 */
+       [836] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 6, 0x928, 5), /* MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC */
+       [837] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 7, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 */
+       [838] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 0, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__FEC_RX_CLK */
+       [839] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 1, 0x808, 1), /* MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 */
+       [840] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 2, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX */
+       [841] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 3, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP */
+       [842] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 4, 0x7e8, 3), /* MX35_PAD_FEC_RX_CLK__CSPI2_MISO */
+       [843] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 5, 0x910, 1), /* MX35_PAD_FEC_RX_CLK__GPIO3_7 */
+       [844] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 6, 0x92c, 4), /* MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I */
+       [845] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 7, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 */
+       [846] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 0, 0x0, 0), /* MX35_PAD_FEC_RX_DV__FEC_RX_DV */
+       [847] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 1, 0x80c, 1), /* MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 */
+       [848] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 2, 0x99c, 2), /* MX35_PAD_FEC_RX_DV__UART3_RTS */
+       [849] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 3, 0x9f0, 1), /* MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT */
+       [850] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 4, 0x7e0, 3), /* MX35_PAD_FEC_RX_DV__CSPI2_SCLK */
+       [851] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 5, 0x914, 1), /* MX35_PAD_FEC_RX_DV__GPIO3_8 */
+       [852] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 6, 0x0, 0), /* MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK */
+       [853] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 7, 0x0, 0), /* MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 */
+       [854] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 0, 0x0, 0), /* MX35_PAD_FEC_COL__FEC_COL */
+       [855] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 1, 0x810, 1), /* MX35_PAD_FEC_COL__ESDHC1_DAT7 */
+       [856] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 2, 0x0, 0), /* MX35_PAD_FEC_COL__UART3_CTS */
+       [857] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 3, 0x9cc, 1), /* MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 */
+       [858] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 4, 0x7e4, 3), /* MX35_PAD_FEC_COL__CSPI2_RDY */
+       [859] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 5, 0x918, 1), /* MX35_PAD_FEC_COL__GPIO3_9 */
+       [860] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 6, 0x0, 0), /* MX35_PAD_FEC_COL__IPU_DISPB_SER_RS */
+       [861] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 7, 0x0, 0), /* MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 */
+       [862] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA0__FEC_RDATA_0 */
+       [863] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 1, 0x0, 0), /* MX35_PAD_FEC_RDATA0__PWM_PWMO */
+       [864] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA0__UART3_DTR */
+       [865] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 3, 0x9d0, 1), /* MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 */
+       [866] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 4, 0x7f0, 2), /* MX35_PAD_FEC_RDATA0__CSPI2_SS0 */
+       [867] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 5, 0x8ec, 1), /* MX35_PAD_FEC_RDATA0__GPIO3_10 */
+       [868] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 */
+       [869] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 7, 0x0, 0), /* MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 */
+       [870] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA0__FEC_TDATA_0 */
+       [871] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 1, 0x0, 0), /* MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 */
+       [872] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 2, 0x0, 0), /* MX35_PAD_FEC_TDATA0__UART3_DSR */
+       [873] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 3, 0x9d4, 1), /* MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 */
+       [874] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 4, 0x7f4, 2), /* MX35_PAD_FEC_TDATA0__CSPI2_SS1 */
+       [875] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 5, 0x8f0, 1), /* MX35_PAD_FEC_TDATA0__GPIO3_11 */
+       [876] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 */
+       [877] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 7, 0x0, 0), /* MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 */
+       [878] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 0, 0x0, 0), /* MX35_PAD_FEC_TX_EN__FEC_TX_EN */
+       [879] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 1, 0x998, 3), /* MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 */
+       [880] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 2, 0x0, 0), /* MX35_PAD_FEC_TX_EN__UART3_RI */
+       [881] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 3, 0x9d8, 1), /* MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 */
+       [882] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 5, 0x8f4, 1), /* MX35_PAD_FEC_TX_EN__GPIO3_12 */
+       [883] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 6, 0x0, 0), /* MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS */
+       [884] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 7, 0x0, 0), /* MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 */
+       [885] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 0, 0x0, 0), /* MX35_PAD_FEC_MDC__FEC_MDC */
+       [886] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 1, 0x0, 0), /* MX35_PAD_FEC_MDC__CAN2_TXCAN */
+       [887] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 2, 0x0, 0), /* MX35_PAD_FEC_MDC__UART3_DCD */
+       [888] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 3, 0x9dc, 1), /* MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 */
+       [889] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 5, 0x8f8, 1), /* MX35_PAD_FEC_MDC__GPIO3_13 */
+       [890] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 6, 0x0, 0), /* MX35_PAD_FEC_MDC__IPU_DISPB_WR */
+       [891] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 7, 0x0, 0), /* MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 */
+       [892] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 0, 0x0, 0), /* MX35_PAD_FEC_MDIO__FEC_MDIO */
+       [893] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 1, 0x7cc, 2), /* MX35_PAD_FEC_MDIO__CAN2_RXCAN */
+       [894] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 3, 0x9e0, 1), /* MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 */
+       [895] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 5, 0x8fc, 1), /* MX35_PAD_FEC_MDIO__GPIO3_14 */
+       [896] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 6, 0x0, 0), /* MX35_PAD_FEC_MDIO__IPU_DISPB_RD */
+       [897] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 7, 0x0, 0), /* MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 */
+       [898] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 0, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__FEC_TX_ERR */
+       [899] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 1, 0x990, 2), /* MX35_PAD_FEC_TX_ERR__OWIRE_LINE */
+       [900] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 2, 0x994, 4), /* MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK */
+       [901] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 3, 0x9e4, 1), /* MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 */
+       [902] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 5, 0x900, 1), /* MX35_PAD_FEC_TX_ERR__GPIO3_15 */
+       [903] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 6, 0x924, 3), /* MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC */
+       [904] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 7, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 */
+       [905] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 0, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__FEC_RX_ERR */
+       [906] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 1, 0x930, 3), /* MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 */
+       [907] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 3, 0x9e8, 1), /* MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 */
+       [908] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 4, 0x960, 1), /* MX35_PAD_FEC_RX_ERR__KPP_COL_4 */
+       [909] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 5, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__GPIO3_16 */
+       [910] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 6, 0x92c, 5), /* MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO */
+       [911] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 0, 0x0, 0), /* MX35_PAD_FEC_CRS__FEC_CRS */
+       [912] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 1, 0x934, 3), /* MX35_PAD_FEC_CRS__IPU_CSI_D_1 */
+       [913] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 3, 0x0, 0), /* MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR */
+       [914] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 4, 0x964, 1), /* MX35_PAD_FEC_CRS__KPP_COL_5 */
+       [915] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 5, 0x0, 0), /* MX35_PAD_FEC_CRS__GPIO3_17 */
+       [916] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 6, 0x0, 0), /* MX35_PAD_FEC_CRS__IPU_FLASH_STROBE */
+       [917] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA1__FEC_RDATA_1 */
+       [918] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 1, 0x938, 4), /* MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 */
+       [919] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC */
+       [920] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 3, 0x9f4, 2), /* MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC */
+       [921] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 4, 0x968, 1), /* MX35_PAD_FEC_RDATA1__KPP_COL_6 */
+       [922] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA1__GPIO3_18 */
+       [923] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 */
+       [924] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA1__FEC_TDATA_1 */
+       [925] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 1, 0x93c, 4), /* MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 */
+       [926] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 2, 0x7bc, 1), /* MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS */
+       [927] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 4, 0x96c, 1), /* MX35_PAD_FEC_TDATA1__KPP_COL_7 */
+       [928] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA1__GPIO3_19 */
+       [929] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 */
+       [930] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA2__FEC_RDATA_2 */
+       [931] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 1, 0x940, 3), /* MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 */
+       [932] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 2, 0x7b4, 1), /* MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD */
+       [933] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 4, 0x980, 1), /* MX35_PAD_FEC_RDATA2__KPP_ROW_4 */
+       [934] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA2__GPIO3_20 */
+       [935] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA2__FEC_TDATA_2 */
+       [936] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 1, 0x944, 3), /* MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 */
+       [937] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 2, 0x7b0, 1), /* MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD */
+       [938] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 4, 0x984, 1), /* MX35_PAD_FEC_TDATA2__KPP_ROW_5 */
+       [939] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA2__GPIO3_21 */
+       [940] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA3__FEC_RDATA_3 */
+       [941] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 1, 0x948, 3), /* MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 */
+       [942] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 2, 0x7c0, 1), /* MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC */
+       [943] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 4, 0x988, 1), /* MX35_PAD_FEC_RDATA3__KPP_ROW_6 */
+       [944] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA3__GPIO3_22 */
+       [945] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA3__FEC_TDATA_3 */
+       [946] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 1, 0x94c, 3), /* MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 */
+       [947] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 2, 0x7c4, 1), /* MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS */
+       [948] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 4, 0x98c, 1), /* MX35_PAD_FEC_TDATA3__KPP_ROW_7 */
+       [949] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA3__GPIO3_23 */
+       [950] = IMX_PIN_REG(MX35_PAD_EXT_ARMCLK, 0x78c, 0x0, 0, 0x0, 0), /* MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK */
+       [951] = IMX_PIN_REG(MX35_PAD_TEST_MODE, 0x790, 0x0, 0, 0x0, 0), /* MX35_PAD_TEST_MODE__TCU_TEST_MODE */
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
+       IMX_PINCTRL_PIN(MX35_PAD_CAPTURE),
+       IMX_PINCTRL_PIN(MX35_PAD_COMPARE),
+       IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST),
+       IMX_PINCTRL_PIN(MX35_PAD_GPIO1_0),
+       IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1),
+       IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0),
+       IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0),
+       IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B),
+       IMX_PINCTRL_PIN(MX35_PAD_POR_B),
+       IMX_PINCTRL_PIN(MX35_PAD_CLKO),
+       IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0),
+       IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1),
+       IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0),
+       IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1),
+       IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL),
+       IMX_PINCTRL_PIN(MX35_PAD_VSTBY),
+       IMX_PINCTRL_PIN(MX35_PAD_A0),
+       IMX_PINCTRL_PIN(MX35_PAD_A1),
+       IMX_PINCTRL_PIN(MX35_PAD_A2),
+       IMX_PINCTRL_PIN(MX35_PAD_A3),
+       IMX_PINCTRL_PIN(MX35_PAD_A4),
+       IMX_PINCTRL_PIN(MX35_PAD_A5),
+       IMX_PINCTRL_PIN(MX35_PAD_A6),
+       IMX_PINCTRL_PIN(MX35_PAD_A7),
+       IMX_PINCTRL_PIN(MX35_PAD_A8),
+       IMX_PINCTRL_PIN(MX35_PAD_A9),
+       IMX_PINCTRL_PIN(MX35_PAD_A10),
+       IMX_PINCTRL_PIN(MX35_PAD_MA10),
+       IMX_PINCTRL_PIN(MX35_PAD_A11),
+       IMX_PINCTRL_PIN(MX35_PAD_A12),
+       IMX_PINCTRL_PIN(MX35_PAD_A13),
+       IMX_PINCTRL_PIN(MX35_PAD_A14),
+       IMX_PINCTRL_PIN(MX35_PAD_A15),
+       IMX_PINCTRL_PIN(MX35_PAD_A16),
+       IMX_PINCTRL_PIN(MX35_PAD_A17),
+       IMX_PINCTRL_PIN(MX35_PAD_A18),
+       IMX_PINCTRL_PIN(MX35_PAD_A19),
+       IMX_PINCTRL_PIN(MX35_PAD_A20),
+       IMX_PINCTRL_PIN(MX35_PAD_A21),
+       IMX_PINCTRL_PIN(MX35_PAD_A22),
+       IMX_PINCTRL_PIN(MX35_PAD_A23),
+       IMX_PINCTRL_PIN(MX35_PAD_A24),
+       IMX_PINCTRL_PIN(MX35_PAD_A25),
+       IMX_PINCTRL_PIN(MX35_PAD_SDBA1),
+       IMX_PINCTRL_PIN(MX35_PAD_SDBA0),
+       IMX_PINCTRL_PIN(MX35_PAD_SD0),
+       IMX_PINCTRL_PIN(MX35_PAD_SD1),
+       IMX_PINCTRL_PIN(MX35_PAD_SD2),
+       IMX_PINCTRL_PIN(MX35_PAD_SD3),
+       IMX_PINCTRL_PIN(MX35_PAD_SD4),
+       IMX_PINCTRL_PIN(MX35_PAD_SD5),
+       IMX_PINCTRL_PIN(MX35_PAD_SD6),
+       IMX_PINCTRL_PIN(MX35_PAD_SD7),
+       IMX_PINCTRL_PIN(MX35_PAD_SD8),
+       IMX_PINCTRL_PIN(MX35_PAD_SD9),
+       IMX_PINCTRL_PIN(MX35_PAD_SD10),
+       IMX_PINCTRL_PIN(MX35_PAD_SD11),
+       IMX_PINCTRL_PIN(MX35_PAD_SD12),
+       IMX_PINCTRL_PIN(MX35_PAD_SD13),
+       IMX_PINCTRL_PIN(MX35_PAD_SD14),
+       IMX_PINCTRL_PIN(MX35_PAD_SD15),
+       IMX_PINCTRL_PIN(MX35_PAD_SD16),
+       IMX_PINCTRL_PIN(MX35_PAD_SD17),
+       IMX_PINCTRL_PIN(MX35_PAD_SD18),
+       IMX_PINCTRL_PIN(MX35_PAD_SD19),
+       IMX_PINCTRL_PIN(MX35_PAD_SD20),
+       IMX_PINCTRL_PIN(MX35_PAD_SD21),
+       IMX_PINCTRL_PIN(MX35_PAD_SD22),
+       IMX_PINCTRL_PIN(MX35_PAD_SD23),
+       IMX_PINCTRL_PIN(MX35_PAD_SD24),
+       IMX_PINCTRL_PIN(MX35_PAD_SD25),
+       IMX_PINCTRL_PIN(MX35_PAD_SD26),
+       IMX_PINCTRL_PIN(MX35_PAD_SD27),
+       IMX_PINCTRL_PIN(MX35_PAD_SD28),
+       IMX_PINCTRL_PIN(MX35_PAD_SD29),
+       IMX_PINCTRL_PIN(MX35_PAD_SD30),
+       IMX_PINCTRL_PIN(MX35_PAD_SD31),
+       IMX_PINCTRL_PIN(MX35_PAD_DQM0),
+       IMX_PINCTRL_PIN(MX35_PAD_DQM1),
+       IMX_PINCTRL_PIN(MX35_PAD_DQM2),
+       IMX_PINCTRL_PIN(MX35_PAD_DQM3),
+       IMX_PINCTRL_PIN(MX35_PAD_EB0),
+       IMX_PINCTRL_PIN(MX35_PAD_EB1),
+       IMX_PINCTRL_PIN(MX35_PAD_OE),
+       IMX_PINCTRL_PIN(MX35_PAD_CS0),
+       IMX_PINCTRL_PIN(MX35_PAD_CS1),
+       IMX_PINCTRL_PIN(MX35_PAD_CS2),
+       IMX_PINCTRL_PIN(MX35_PAD_CS3),
+       IMX_PINCTRL_PIN(MX35_PAD_CS4),
+       IMX_PINCTRL_PIN(MX35_PAD_CS5),
+       IMX_PINCTRL_PIN(MX35_PAD_NF_CE0),
+       IMX_PINCTRL_PIN(MX35_PAD_ECB),
+       IMX_PINCTRL_PIN(MX35_PAD_LBA),
+       IMX_PINCTRL_PIN(MX35_PAD_BCLK),
+       IMX_PINCTRL_PIN(MX35_PAD_RW),
+       IMX_PINCTRL_PIN(MX35_PAD_RAS),
+       IMX_PINCTRL_PIN(MX35_PAD_CAS),
+       IMX_PINCTRL_PIN(MX35_PAD_SDWE),
+       IMX_PINCTRL_PIN(MX35_PAD_SDCKE0),
+       IMX_PINCTRL_PIN(MX35_PAD_SDCKE1),
+       IMX_PINCTRL_PIN(MX35_PAD_SDCLK),
+       IMX_PINCTRL_PIN(MX35_PAD_SDQS0),
+       IMX_PINCTRL_PIN(MX35_PAD_SDQS1),
+       IMX_PINCTRL_PIN(MX35_PAD_SDQS2),
+       IMX_PINCTRL_PIN(MX35_PAD_SDQS3),
+       IMX_PINCTRL_PIN(MX35_PAD_NFWE_B),
+       IMX_PINCTRL_PIN(MX35_PAD_NFRE_B),
+       IMX_PINCTRL_PIN(MX35_PAD_NFALE),
+       IMX_PINCTRL_PIN(MX35_PAD_NFCLE),
+       IMX_PINCTRL_PIN(MX35_PAD_NFWP_B),
+       IMX_PINCTRL_PIN(MX35_PAD_NFRB),
+       IMX_PINCTRL_PIN(MX35_PAD_D15),
+       IMX_PINCTRL_PIN(MX35_PAD_D14),
+       IMX_PINCTRL_PIN(MX35_PAD_D13),
+       IMX_PINCTRL_PIN(MX35_PAD_D12),
+       IMX_PINCTRL_PIN(MX35_PAD_D11),
+       IMX_PINCTRL_PIN(MX35_PAD_D10),
+       IMX_PINCTRL_PIN(MX35_PAD_D9),
+       IMX_PINCTRL_PIN(MX35_PAD_D8),
+       IMX_PINCTRL_PIN(MX35_PAD_D7),
+       IMX_PINCTRL_PIN(MX35_PAD_D6),
+       IMX_PINCTRL_PIN(MX35_PAD_D5),
+       IMX_PINCTRL_PIN(MX35_PAD_D4),
+       IMX_PINCTRL_PIN(MX35_PAD_D3),
+       IMX_PINCTRL_PIN(MX35_PAD_D2),
+       IMX_PINCTRL_PIN(MX35_PAD_D1),
+       IMX_PINCTRL_PIN(MX35_PAD_D0),
+       IMX_PINCTRL_PIN(MX35_PAD_CSI_D8),
+       IMX_PINCTRL_PIN(MX35_PAD_CSI_D9),
+       IMX_PINCTRL_PIN(MX35_PAD_CSI_D10),
+       IMX_PINCTRL_PIN(MX35_PAD_CSI_D11),
+       IMX_PINCTRL_PIN(MX35_PAD_CSI_D12),
+       IMX_PINCTRL_PIN(MX35_PAD_CSI_D13),
+       IMX_PINCTRL_PIN(MX35_PAD_CSI_D14),
+       IMX_PINCTRL_PIN(MX35_PAD_CSI_D15),
+       IMX_PINCTRL_PIN(MX35_PAD_CSI_MCLK),
+       IMX_PINCTRL_PIN(MX35_PAD_CSI_VSYNC),
+       IMX_PINCTRL_PIN(MX35_PAD_CSI_HSYNC),
+       IMX_PINCTRL_PIN(MX35_PAD_CSI_PIXCLK),
+       IMX_PINCTRL_PIN(MX35_PAD_I2C1_CLK),
+       IMX_PINCTRL_PIN(MX35_PAD_I2C1_DAT),
+       IMX_PINCTRL_PIN(MX35_PAD_I2C2_CLK),
+       IMX_PINCTRL_PIN(MX35_PAD_I2C2_DAT),
+       IMX_PINCTRL_PIN(MX35_PAD_STXD4),
+       IMX_PINCTRL_PIN(MX35_PAD_SRXD4),
+       IMX_PINCTRL_PIN(MX35_PAD_SCK4),
+       IMX_PINCTRL_PIN(MX35_PAD_STXFS4),
+       IMX_PINCTRL_PIN(MX35_PAD_STXD5),
+       IMX_PINCTRL_PIN(MX35_PAD_SRXD5),
+       IMX_PINCTRL_PIN(MX35_PAD_SCK5),
+       IMX_PINCTRL_PIN(MX35_PAD_STXFS5),
+       IMX_PINCTRL_PIN(MX35_PAD_SCKR),
+       IMX_PINCTRL_PIN(MX35_PAD_FSR),
+       IMX_PINCTRL_PIN(MX35_PAD_HCKR),
+       IMX_PINCTRL_PIN(MX35_PAD_SCKT),
+       IMX_PINCTRL_PIN(MX35_PAD_FST),
+       IMX_PINCTRL_PIN(MX35_PAD_HCKT),
+       IMX_PINCTRL_PIN(MX35_PAD_TX5_RX0),
+       IMX_PINCTRL_PIN(MX35_PAD_TX4_RX1),
+       IMX_PINCTRL_PIN(MX35_PAD_TX3_RX2),
+       IMX_PINCTRL_PIN(MX35_PAD_TX2_RX3),
+       IMX_PINCTRL_PIN(MX35_PAD_TX1),
+       IMX_PINCTRL_PIN(MX35_PAD_TX0),
+       IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MOSI),
+       IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MISO),
+       IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS0),
+       IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS1),
+       IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SCLK),
+       IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SPI_RDY),
+       IMX_PINCTRL_PIN(MX35_PAD_RXD1),
+       IMX_PINCTRL_PIN(MX35_PAD_TXD1),
+       IMX_PINCTRL_PIN(MX35_PAD_RTS1),
+       IMX_PINCTRL_PIN(MX35_PAD_CTS1),
+       IMX_PINCTRL_PIN(MX35_PAD_RXD2),
+       IMX_PINCTRL_PIN(MX35_PAD_TXD2),
+       IMX_PINCTRL_PIN(MX35_PAD_RTS2),
+       IMX_PINCTRL_PIN(MX35_PAD_CTS2),
+       IMX_PINCTRL_PIN(MX35_PAD_RTCK),
+       IMX_PINCTRL_PIN(MX35_PAD_TCK),
+       IMX_PINCTRL_PIN(MX35_PAD_TMS),
+       IMX_PINCTRL_PIN(MX35_PAD_TDI),
+       IMX_PINCTRL_PIN(MX35_PAD_TDO),
+       IMX_PINCTRL_PIN(MX35_PAD_TRSTB),
+       IMX_PINCTRL_PIN(MX35_PAD_DE_B),
+       IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD),
+       IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR),
+       IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC),
+       IMX_PINCTRL_PIN(MX35_PAD_LD0),
+       IMX_PINCTRL_PIN(MX35_PAD_LD1),
+       IMX_PINCTRL_PIN(MX35_PAD_LD2),
+       IMX_PINCTRL_PIN(MX35_PAD_LD3),
+       IMX_PINCTRL_PIN(MX35_PAD_LD4),
+       IMX_PINCTRL_PIN(MX35_PAD_LD5),
+       IMX_PINCTRL_PIN(MX35_PAD_LD6),
+       IMX_PINCTRL_PIN(MX35_PAD_LD7),
+       IMX_PINCTRL_PIN(MX35_PAD_LD8),
+       IMX_PINCTRL_PIN(MX35_PAD_LD9),
+       IMX_PINCTRL_PIN(MX35_PAD_LD10),
+       IMX_PINCTRL_PIN(MX35_PAD_LD11),
+       IMX_PINCTRL_PIN(MX35_PAD_LD12),
+       IMX_PINCTRL_PIN(MX35_PAD_LD13),
+       IMX_PINCTRL_PIN(MX35_PAD_LD14),
+       IMX_PINCTRL_PIN(MX35_PAD_LD15),
+       IMX_PINCTRL_PIN(MX35_PAD_LD16),
+       IMX_PINCTRL_PIN(MX35_PAD_LD17),
+       IMX_PINCTRL_PIN(MX35_PAD_LD18),
+       IMX_PINCTRL_PIN(MX35_PAD_LD19),
+       IMX_PINCTRL_PIN(MX35_PAD_LD20),
+       IMX_PINCTRL_PIN(MX35_PAD_LD21),
+       IMX_PINCTRL_PIN(MX35_PAD_LD22),
+       IMX_PINCTRL_PIN(MX35_PAD_LD23),
+       IMX_PINCTRL_PIN(MX35_PAD_D3_HSYNC),
+       IMX_PINCTRL_PIN(MX35_PAD_D3_FPSHIFT),
+       IMX_PINCTRL_PIN(MX35_PAD_D3_DRDY),
+       IMX_PINCTRL_PIN(MX35_PAD_CONTRAST),
+       IMX_PINCTRL_PIN(MX35_PAD_D3_VSYNC),
+       IMX_PINCTRL_PIN(MX35_PAD_D3_REV),
+       IMX_PINCTRL_PIN(MX35_PAD_D3_CLS),
+       IMX_PINCTRL_PIN(MX35_PAD_D3_SPL),
+       IMX_PINCTRL_PIN(MX35_PAD_SD1_CMD),
+       IMX_PINCTRL_PIN(MX35_PAD_SD1_CLK),
+       IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA0),
+       IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA1),
+       IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA2),
+       IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA3),
+       IMX_PINCTRL_PIN(MX35_PAD_SD2_CMD),
+       IMX_PINCTRL_PIN(MX35_PAD_SD2_CLK),
+       IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA0),
+       IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA1),
+       IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA2),
+       IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA3),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_CS0),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_CS1),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOR),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOW),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DMACK),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_RESET_B),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_IORDY),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA0),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA1),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA2),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA3),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA4),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA5),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA6),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA7),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA8),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA9),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA10),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA11),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA12),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA13),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA14),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA15),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_INTRQ),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_BUFF_EN),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DMARQ),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DA0),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DA1),
+       IMX_PINCTRL_PIN(MX35_PAD_ATA_DA2),
+       IMX_PINCTRL_PIN(MX35_PAD_MLB_CLK),
+       IMX_PINCTRL_PIN(MX35_PAD_MLB_DAT),
+       IMX_PINCTRL_PIN(MX35_PAD_MLB_SIG),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_CLK),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_CLK),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_DV),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_COL),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA0),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA0),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_EN),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_MDC),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_MDIO),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_ERR),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_ERR),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_CRS),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA1),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA1),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA2),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3),
+       IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3),
+       IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK),
+       IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE),
+};
+
+static struct imx_pinctrl_soc_info imx35_pinctrl_info = {
+       .pins = imx35_pinctrl_pads,
+       .npins = ARRAY_SIZE(imx35_pinctrl_pads),
+       .pin_regs = imx35_pin_regs,
+       .npin_regs = ARRAY_SIZE(imx35_pin_regs),
+};
+
+static struct of_device_id imx35_pinctrl_of_match[] __devinitdata = {
+       { .compatible = "fsl,imx35-iomuxc", },
+       { /* sentinel */ }
+};
+
+static int __devinit imx35_pinctrl_probe(struct platform_device *pdev)
+{
+       return imx_pinctrl_probe(pdev, &imx35_pinctrl_info);
+}
+
+static struct platform_driver imx35_pinctrl_driver = {
+       .driver = {
+               .name = "imx35-pinctrl",
+               .owner = THIS_MODULE,
+               .of_match_table = of_match_ptr(imx35_pinctrl_of_match),
+       },
+       .probe = imx35_pinctrl_probe,
+       .remove = __devexit_p(imx_pinctrl_remove),
+};
+
+static int __init imx35_pinctrl_init(void)
+{
+       return platform_driver_register(&imx35_pinctrl_driver);
+}
+arch_initcall(imx35_pinctrl_init);
+
+static void __exit imx35_pinctrl_exit(void)
+{
+       platform_driver_unregister(&imx35_pinctrl_driver);
+}
+module_exit(imx35_pinctrl_exit);
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
+MODULE_DESCRIPTION("Freescale IMX35 pinctrl driver");
+MODULE_LICENSE("GPL v2");

diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c
index 689b3c88dd2e723be68c5fd83a8bca99e9be78e8..fb846896677972f09e7a69661a469ea390d397c7 100644 (file)
--- a/drivers/pinctrl/pinctrl-imx51.c
+++ b/drivers/pinctrl/pinctrl-imx51.c
@@ -23,251 +23,251 @@
 #include "pinctrl-imx.h"
 
 enum imx51_pads {
-       MX51_PAD_EIM_D16 = 1,
-       MX51_PAD_EIM_D17 = 2,
-       MX51_PAD_EIM_D18 = 3,
-       MX51_PAD_EIM_D19 = 4,
-       MX51_PAD_EIM_D20 = 5,
-       MX51_PAD_EIM_D21 = 6,
-       MX51_PAD_EIM_D22 = 7,
-       MX51_PAD_EIM_D23 = 8,
-       MX51_PAD_EIM_D24 = 9,
-       MX51_PAD_EIM_D25 = 10,
-       MX51_PAD_EIM_D26 = 11,
-       MX51_PAD_EIM_D27 = 12,
-       MX51_PAD_EIM_D28 = 13,
-       MX51_PAD_EIM_D29 = 14,
-       MX51_PAD_EIM_D30 = 15,
-       MX51_PAD_EIM_D31 = 16,
-       MX51_PAD_EIM_A16 = 17,
-       MX51_PAD_EIM_A17 = 18,
-       MX51_PAD_EIM_A18 = 19,
-       MX51_PAD_EIM_A19 = 20,
-       MX51_PAD_EIM_A20 = 21,
-       MX51_PAD_EIM_A21 = 22,
-       MX51_PAD_EIM_A22 = 23,
-       MX51_PAD_EIM_A23 = 24,
-       MX51_PAD_EIM_A24 = 25,
-       MX51_PAD_EIM_A25 = 26,
-       MX51_PAD_EIM_A26 = 27,
-       MX51_PAD_EIM_A27 = 28,
-       MX51_PAD_EIM_EB0 = 29,
-       MX51_PAD_EIM_EB1 = 30,
-       MX51_PAD_EIM_EB2 = 31,
-       MX51_PAD_EIM_EB3 = 32,
-       MX51_PAD_EIM_OE = 33,
-       MX51_PAD_EIM_CS0 = 34,
-       MX51_PAD_EIM_CS1 = 35,
-       MX51_PAD_EIM_CS2 = 36,
-       MX51_PAD_EIM_CS3 = 37,
-       MX51_PAD_EIM_CS4 = 38,
-       MX51_PAD_EIM_CS5 = 39,
-       MX51_PAD_EIM_DTACK = 40,
-       MX51_PAD_EIM_LBA = 41,
-       MX51_PAD_EIM_CRE = 42,
-       MX51_PAD_DRAM_CS1 = 43,
-       MX51_PAD_NANDF_WE_B = 44,
-       MX51_PAD_NANDF_RE_B = 45,
-       MX51_PAD_NANDF_ALE = 46,
-       MX51_PAD_NANDF_CLE = 47,
-       MX51_PAD_NANDF_WP_B = 48,
-       MX51_PAD_NANDF_RB0 = 49,
-       MX51_PAD_NANDF_RB1 = 50,
-       MX51_PAD_NANDF_RB2 = 51,
-       MX51_PAD_NANDF_RB3 = 52,
-       MX51_PAD_GPIO_NAND = 53,
-       MX51_PAD_NANDF_CS0 = 54,
-       MX51_PAD_NANDF_CS1 = 55,
-       MX51_PAD_NANDF_CS2 = 56,
-       MX51_PAD_NANDF_CS3 = 57,
-       MX51_PAD_NANDF_CS4 = 58,
-       MX51_PAD_NANDF_CS5 = 59,
-       MX51_PAD_NANDF_CS6 = 60,
-       MX51_PAD_NANDF_CS7 = 61,
-       MX51_PAD_NANDF_RDY_INT = 62,
-       MX51_PAD_NANDF_D15 = 63,
-       MX51_PAD_NANDF_D14 = 64,
-       MX51_PAD_NANDF_D13 = 65,
-       MX51_PAD_NANDF_D12 = 66,
-       MX51_PAD_NANDF_D11 = 67,
-       MX51_PAD_NANDF_D10 = 68,
-       MX51_PAD_NANDF_D9 = 69,
-       MX51_PAD_NANDF_D8 = 70,
-       MX51_PAD_NANDF_D7 = 71,
-       MX51_PAD_NANDF_D6 = 72,
-       MX51_PAD_NANDF_D5 = 73,
-       MX51_PAD_NANDF_D4 = 74,
-       MX51_PAD_NANDF_D3 = 75,
-       MX51_PAD_NANDF_D2 = 76,
-       MX51_PAD_NANDF_D1 = 77,
-       MX51_PAD_NANDF_D0 = 78,
-       MX51_PAD_CSI1_D8 = 79,
-       MX51_PAD_CSI1_D9 = 80,
-       MX51_PAD_CSI1_D10 = 81,
-       MX51_PAD_CSI1_D11 = 82,
-       MX51_PAD_CSI1_D12 = 83,
-       MX51_PAD_CSI1_D13 = 84,
-       MX51_PAD_CSI1_D14 = 85,
-       MX51_PAD_CSI1_D15 = 86,
-       MX51_PAD_CSI1_D16 = 87,
-       MX51_PAD_CSI1_D17 = 88,
-       MX51_PAD_CSI1_D18 = 89,
-       MX51_PAD_CSI1_D19 = 90,
-       MX51_PAD_CSI1_VSYNC = 91,
-       MX51_PAD_CSI1_HSYNC = 92,
-       MX51_PAD_CSI1_PIXCLK = 93,
-       MX51_PAD_CSI1_MCLK = 94,
-       MX51_PAD_CSI2_D12 = 95,
-       MX51_PAD_CSI2_D13 = 96,
-       MX51_PAD_CSI2_D14 = 97,
-       MX51_PAD_CSI2_D15 = 98,
-       MX51_PAD_CSI2_D16 = 99,
-       MX51_PAD_CSI2_D17 = 100,
-       MX51_PAD_CSI2_D18 = 101,
-       MX51_PAD_CSI2_D19 = 102,
-       MX51_PAD_CSI2_VSYNC = 103,
-       MX51_PAD_CSI2_HSYNC = 104,
-       MX51_PAD_CSI2_PIXCLK = 105,
-       MX51_PAD_I2C1_CLK = 106,
-       MX51_PAD_I2C1_DAT = 107,
-       MX51_PAD_AUD3_BB_TXD = 108,
-       MX51_PAD_AUD3_BB_RXD = 109,
-       MX51_PAD_AUD3_BB_CK = 110,
-       MX51_PAD_AUD3_BB_FS = 111,
-       MX51_PAD_CSPI1_MOSI = 112,
-       MX51_PAD_CSPI1_MISO = 113,
-       MX51_PAD_CSPI1_SS0 = 114,
-       MX51_PAD_CSPI1_SS1 = 115,
-       MX51_PAD_CSPI1_RDY = 116,
-       MX51_PAD_CSPI1_SCLK = 117,
-       MX51_PAD_UART1_RXD = 118,
-       MX51_PAD_UART1_TXD = 119,
-       MX51_PAD_UART1_RTS = 120,
-       MX51_PAD_UART1_CTS = 121,
-       MX51_PAD_UART2_RXD = 122,
-       MX51_PAD_UART2_TXD = 123,
-       MX51_PAD_UART3_RXD = 124,
-       MX51_PAD_UART3_TXD = 125,
-       MX51_PAD_OWIRE_LINE = 126,
-       MX51_PAD_KEY_ROW0 = 127,
-       MX51_PAD_KEY_ROW1 = 128,
-       MX51_PAD_KEY_ROW2 = 129,
-       MX51_PAD_KEY_ROW3 = 130,
-       MX51_PAD_KEY_COL0 = 131,
-       MX51_PAD_KEY_COL1 = 132,
-       MX51_PAD_KEY_COL2 = 133,
-       MX51_PAD_KEY_COL3 = 134,
-       MX51_PAD_KEY_COL4 = 135,
-       MX51_PAD_KEY_COL5 = 136,
-       MX51_PAD_USBH1_CLK = 137,
-       MX51_PAD_USBH1_DIR = 138,
-       MX51_PAD_USBH1_STP = 139,
-       MX51_PAD_USBH1_NXT = 140,
-       MX51_PAD_USBH1_DATA0 = 141,
-       MX51_PAD_USBH1_DATA1 = 142,
-       MX51_PAD_USBH1_DATA2 = 143,
-       MX51_PAD_USBH1_DATA3 = 144,
-       MX51_PAD_USBH1_DATA4 = 145,
-       MX51_PAD_USBH1_DATA5 = 146,
-       MX51_PAD_USBH1_DATA6 = 147,
-       MX51_PAD_USBH1_DATA7 = 148,
-       MX51_PAD_DI1_PIN11 = 149,
-       MX51_PAD_DI1_PIN12 = 150,
-       MX51_PAD_DI1_PIN13 = 151,
-       MX51_PAD_DI1_D0_CS = 152,
-       MX51_PAD_DI1_D1_CS = 153,
-       MX51_PAD_DISPB2_SER_DIN = 154,
-       MX51_PAD_DISPB2_SER_DIO = 155,
-       MX51_PAD_DISPB2_SER_CLK = 156,
-       MX51_PAD_DISPB2_SER_RS = 157,
-       MX51_PAD_DISP1_DAT0 = 158,
-       MX51_PAD_DISP1_DAT1 = 159,
-       MX51_PAD_DISP1_DAT2 = 160,
-       MX51_PAD_DISP1_DAT3 = 161,
-       MX51_PAD_DISP1_DAT4 = 162,
-       MX51_PAD_DISP1_DAT5 = 163,
-       MX51_PAD_DISP1_DAT6 = 164,
-       MX51_PAD_DISP1_DAT7 = 165,
-       MX51_PAD_DISP1_DAT8 = 166,
-       MX51_PAD_DISP1_DAT9 = 167,
-       MX51_PAD_DISP1_DAT10 = 168,
-       MX51_PAD_DISP1_DAT11 = 169,
-       MX51_PAD_DISP1_DAT12 = 170,
-       MX51_PAD_DISP1_DAT13 = 171,
-       MX51_PAD_DISP1_DAT14 = 172,
-       MX51_PAD_DISP1_DAT15 = 173,
-       MX51_PAD_DISP1_DAT16 = 174,
-       MX51_PAD_DISP1_DAT17 = 175,
-       MX51_PAD_DISP1_DAT18 = 176,
-       MX51_PAD_DISP1_DAT19 = 177,
-       MX51_PAD_DISP1_DAT20 = 178,
-       MX51_PAD_DISP1_DAT21 = 179,
-       MX51_PAD_DISP1_DAT22 = 180,
-       MX51_PAD_DISP1_DAT23 = 181,
-       MX51_PAD_DI1_PIN3 = 182,
-       MX51_PAD_DI1_PIN2 = 183,
-       MX51_PAD_DI_GP2 = 184,
-       MX51_PAD_DI_GP3 = 185,
-       MX51_PAD_DI2_PIN4 = 186,
-       MX51_PAD_DI2_PIN2 = 187,
-       MX51_PAD_DI2_PIN3 = 188,
-       MX51_PAD_DI2_DISP_CLK = 189,
-       MX51_PAD_DI_GP4 = 190,
-       MX51_PAD_DISP2_DAT0 = 191,
-       MX51_PAD_DISP2_DAT1 = 192,
-       MX51_PAD_DISP2_DAT2 = 193,
-       MX51_PAD_DISP2_DAT3 = 194,
-       MX51_PAD_DISP2_DAT4 = 195,
-       MX51_PAD_DISP2_DAT5 = 196,
-       MX51_PAD_DISP2_DAT6 = 197,
-       MX51_PAD_DISP2_DAT7 = 198,
-       MX51_PAD_DISP2_DAT8 = 199,
-       MX51_PAD_DISP2_DAT9 = 200,
-       MX51_PAD_DISP2_DAT10 = 201,
-       MX51_PAD_DISP2_DAT11 = 202,
-       MX51_PAD_DISP2_DAT12 = 203,
-       MX51_PAD_DISP2_DAT13 = 204,
-       MX51_PAD_DISP2_DAT14 = 205,
-       MX51_PAD_DISP2_DAT15 = 206,
-       MX51_PAD_SD1_CMD = 207,
-       MX51_PAD_SD1_CLK = 208,
-       MX51_PAD_SD1_DATA0 = 209,
-       MX51_PAD_EIM_DA0 = 210,
-       MX51_PAD_EIM_DA1 = 211,
-       MX51_PAD_EIM_DA2 = 212,
-       MX51_PAD_EIM_DA3 = 213,
-       MX51_PAD_SD1_DATA1 = 214,
-       MX51_PAD_EIM_DA4 = 215,
-       MX51_PAD_EIM_DA5 = 216,
-       MX51_PAD_EIM_DA6 = 217,
-       MX51_PAD_EIM_DA7 = 218,
-       MX51_PAD_SD1_DATA2 = 219,
-       MX51_PAD_EIM_DA10 = 220,
-       MX51_PAD_EIM_DA11 = 221,
-       MX51_PAD_EIM_DA8 = 222,
-       MX51_PAD_EIM_DA9 = 223,
-       MX51_PAD_SD1_DATA3 = 224,
-       MX51_PAD_GPIO1_0 = 225,
-       MX51_PAD_GPIO1_1 = 226,
-       MX51_PAD_EIM_DA12 = 227,
-       MX51_PAD_EIM_DA13 = 228,
-       MX51_PAD_EIM_DA14 = 229,
-       MX51_PAD_EIM_DA15 = 230,
-       MX51_PAD_SD2_CMD = 231,
-       MX51_PAD_SD2_CLK = 232,
-       MX51_PAD_SD2_DATA0 = 233,
-       MX51_PAD_SD2_DATA1 = 234,
-       MX51_PAD_SD2_DATA2 = 235,
-       MX51_PAD_SD2_DATA3 = 236,
-       MX51_PAD_GPIO1_2 = 237,
-       MX51_PAD_GPIO1_3 = 238,
-       MX51_PAD_PMIC_INT_REQ = 239,
-       MX51_PAD_GPIO1_4 = 240,
-       MX51_PAD_GPIO1_5 = 241,
-       MX51_PAD_GPIO1_6 = 242,
-       MX51_PAD_GPIO1_7 = 243,
-       MX51_PAD_GPIO1_8 = 244,
-       MX51_PAD_GPIO1_9 = 245,
+       MX51_PAD_EIM_D16 = 0,
+       MX51_PAD_EIM_D17 = 1,
+       MX51_PAD_EIM_D18 = 2,
+       MX51_PAD_EIM_D19 = 3,
+       MX51_PAD_EIM_D20 = 4,
+       MX51_PAD_EIM_D21 = 5,
+       MX51_PAD_EIM_D22 = 6,
+       MX51_PAD_EIM_D23 = 7,
+       MX51_PAD_EIM_D24 = 8,
+       MX51_PAD_EIM_D25 = 9,
+       MX51_PAD_EIM_D26 = 10,
+       MX51_PAD_EIM_D27 = 11,
+       MX51_PAD_EIM_D28 = 12,
+       MX51_PAD_EIM_D29 = 13,
+       MX51_PAD_EIM_D30 = 14,
+       MX51_PAD_EIM_D31 = 15,
+       MX51_PAD_EIM_A16 = 16,
+       MX51_PAD_EIM_A17 = 17,
+       MX51_PAD_EIM_A18 = 18,
+       MX51_PAD_EIM_A19 = 19,
+       MX51_PAD_EIM_A20 = 20,
+       MX51_PAD_EIM_A21 = 21,
+       MX51_PAD_EIM_A22 = 22,
+       MX51_PAD_EIM_A23 = 23,
+       MX51_PAD_EIM_A24 = 24,
+       MX51_PAD_EIM_A25 = 25,
+       MX51_PAD_EIM_A26 = 26,
+       MX51_PAD_EIM_A27 = 27,
+       MX51_PAD_EIM_EB0 = 28,
+       MX51_PAD_EIM_EB1 = 29,
+       MX51_PAD_EIM_EB2 = 30,
+       MX51_PAD_EIM_EB3 = 31,
+       MX51_PAD_EIM_OE = 32,
+       MX51_PAD_EIM_CS0 = 33,
+       MX51_PAD_EIM_CS1 = 34,
+       MX51_PAD_EIM_CS2 = 35,
+       MX51_PAD_EIM_CS3 = 36,
+       MX51_PAD_EIM_CS4 = 37,
+       MX51_PAD_EIM_CS5 = 38,
+       MX51_PAD_EIM_DTACK = 39,
+       MX51_PAD_EIM_LBA = 40,
+       MX51_PAD_EIM_CRE = 41,
+       MX51_PAD_DRAM_CS1 = 42,
+       MX51_PAD_NANDF_WE_B = 43,
+       MX51_PAD_NANDF_RE_B = 44,
+       MX51_PAD_NANDF_ALE = 45,
+       MX51_PAD_NANDF_CLE = 46,
+       MX51_PAD_NANDF_WP_B = 47,
+       MX51_PAD_NANDF_RB0 = 48,
+       MX51_PAD_NANDF_RB1 = 49,
+       MX51_PAD_NANDF_RB2 = 50,
+       MX51_PAD_NANDF_RB3 = 51,
+       MX51_PAD_GPIO_NAND = 52,
+       MX51_PAD_NANDF_CS0 = 53,
+       MX51_PAD_NANDF_CS1 = 54,
+       MX51_PAD_NANDF_CS2 = 55,
+       MX51_PAD_NANDF_CS3 = 56,
+       MX51_PAD_NANDF_CS4 = 57,
+       MX51_PAD_NANDF_CS5 = 58,
+       MX51_PAD_NANDF_CS6 = 59,
+       MX51_PAD_NANDF_CS7 = 60,
+       MX51_PAD_NANDF_RDY_INT = 61,
+       MX51_PAD_NANDF_D15 = 62,
+       MX51_PAD_NANDF_D14 = 63,
+       MX51_PAD_NANDF_D13 = 64,
+       MX51_PAD_NANDF_D12 = 65,
+       MX51_PAD_NANDF_D11 = 66,
+       MX51_PAD_NANDF_D10 = 67,
+       MX51_PAD_NANDF_D9 = 68,
+       MX51_PAD_NANDF_D8 = 69,
+       MX51_PAD_NANDF_D7 = 70,
+       MX51_PAD_NANDF_D6 = 71,
+       MX51_PAD_NANDF_D5 = 72,
+       MX51_PAD_NANDF_D4 = 73,
+       MX51_PAD_NANDF_D3 = 74,
+       MX51_PAD_NANDF_D2 = 75,
+       MX51_PAD_NANDF_D1 = 76,
+       MX51_PAD_NANDF_D0 = 77,
+       MX51_PAD_CSI1_D8 = 78,
+       MX51_PAD_CSI1_D9 = 79,
+       MX51_PAD_CSI1_D10 = 80,
+       MX51_PAD_CSI1_D11 = 81,
+       MX51_PAD_CSI1_D12 = 82,
+       MX51_PAD_CSI1_D13 = 83,
+       MX51_PAD_CSI1_D14 = 84,
+       MX51_PAD_CSI1_D15 = 85,
+       MX51_PAD_CSI1_D16 = 86,
+       MX51_PAD_CSI1_D17 = 87,
+       MX51_PAD_CSI1_D18 = 88,
+       MX51_PAD_CSI1_D19 = 89,
+       MX51_PAD_CSI1_VSYNC = 90,
+       MX51_PAD_CSI1_HSYNC = 91,
+       MX51_PAD_CSI1_PIXCLK = 92,
+       MX51_PAD_CSI1_MCLK = 93,
+       MX51_PAD_CSI2_D12 = 94,
+       MX51_PAD_CSI2_D13 = 95,
+       MX51_PAD_CSI2_D14 = 96,
+       MX51_PAD_CSI2_D15 = 97,
+       MX51_PAD_CSI2_D16 = 98,
+       MX51_PAD_CSI2_D17 = 99,
+       MX51_PAD_CSI2_D18 = 100,
+       MX51_PAD_CSI2_D19 = 101,
+       MX51_PAD_CSI2_VSYNC = 102,
+       MX51_PAD_CSI2_HSYNC = 103,
+       MX51_PAD_CSI2_PIXCLK = 104,
+       MX51_PAD_I2C1_CLK = 105,
+       MX51_PAD_I2C1_DAT = 106,
+       MX51_PAD_AUD3_BB_TXD = 107,
+       MX51_PAD_AUD3_BB_RXD = 108,
+       MX51_PAD_AUD3_BB_CK = 109,
+       MX51_PAD_AUD3_BB_FS = 110,
+       MX51_PAD_CSPI1_MOSI = 111,
+       MX51_PAD_CSPI1_MISO = 112,
+       MX51_PAD_CSPI1_SS0 = 113,
+       MX51_PAD_CSPI1_SS1 = 114,
+       MX51_PAD_CSPI1_RDY = 115,
+       MX51_PAD_CSPI1_SCLK = 116,
+       MX51_PAD_UART1_RXD = 117,
+       MX51_PAD_UART1_TXD = 118,
+       MX51_PAD_UART1_RTS = 119,
+       MX51_PAD_UART1_CTS = 120,
+       MX51_PAD_UART2_RXD = 121,
+       MX51_PAD_UART2_TXD = 122,
+       MX51_PAD_UART3_RXD = 123,
+       MX51_PAD_UART3_TXD = 124,
+       MX51_PAD_OWIRE_LINE = 125,
+       MX51_PAD_KEY_ROW0 = 126,
+       MX51_PAD_KEY_ROW1 = 127,
+       MX51_PAD_KEY_ROW2 = 128,
+       MX51_PAD_KEY_ROW3 = 129,
+       MX51_PAD_KEY_COL0 = 130,
+       MX51_PAD_KEY_COL1 = 131,
+       MX51_PAD_KEY_COL2 = 132,
+       MX51_PAD_KEY_COL3 = 133,
+       MX51_PAD_KEY_COL4 = 134,
+       MX51_PAD_KEY_COL5 = 135,
+       MX51_PAD_USBH1_CLK = 136,
+       MX51_PAD_USBH1_DIR = 137,
+       MX51_PAD_USBH1_STP = 138,
+       MX51_PAD_USBH1_NXT = 139,
+       MX51_PAD_USBH1_DATA0 = 140,
+       MX51_PAD_USBH1_DATA1 = 141,
+       MX51_PAD_USBH1_DATA2 = 142,
+       MX51_PAD_USBH1_DATA3 = 143,
+       MX51_PAD_USBH1_DATA4 = 144,
+       MX51_PAD_USBH1_DATA5 = 145,
+       MX51_PAD_USBH1_DATA6 = 146,
+       MX51_PAD_USBH1_DATA7 = 147,
+       MX51_PAD_DI1_PIN11 = 148,
+       MX51_PAD_DI1_PIN12 = 149,
+       MX51_PAD_DI1_PIN13 = 150,
+       MX51_PAD_DI1_D0_CS = 151,
+       MX51_PAD_DI1_D1_CS = 152,
+       MX51_PAD_DISPB2_SER_DIN = 153,
+       MX51_PAD_DISPB2_SER_DIO = 154,
+       MX51_PAD_DISPB2_SER_CLK = 155,
+       MX51_PAD_DISPB2_SER_RS = 156,
+       MX51_PAD_DISP1_DAT0 = 157,
+       MX51_PAD_DISP1_DAT1 = 158,
+       MX51_PAD_DISP1_DAT2 = 159,
+       MX51_PAD_DISP1_DAT3 = 160,
+       MX51_PAD_DISP1_DAT4 = 161,
+       MX51_PAD_DISP1_DAT5 = 162,
+       MX51_PAD_DISP1_DAT6 = 163,
+       MX51_PAD_DISP1_DAT7 = 164,
+       MX51_PAD_DISP1_DAT8 = 165,
+       MX51_PAD_DISP1_DAT9 = 166,
+       MX51_PAD_DISP1_DAT10 = 167,
+       MX51_PAD_DISP1_DAT11 = 168,
+       MX51_PAD_DISP1_DAT12 = 169,
+       MX51_PAD_DISP1_DAT13 = 170,
+       MX51_PAD_DISP1_DAT14 = 171,
+       MX51_PAD_DISP1_DAT15 = 172,
+       MX51_PAD_DISP1_DAT16 = 173,
+       MX51_PAD_DISP1_DAT17 = 174,
+       MX51_PAD_DISP1_DAT18 = 175,
+       MX51_PAD_DISP1_DAT19 = 176,
+       MX51_PAD_DISP1_DAT20 = 177,
+       MX51_PAD_DISP1_DAT21 = 178,
+       MX51_PAD_DISP1_DAT22 = 179,
+       MX51_PAD_DISP1_DAT23 = 180,
+       MX51_PAD_DI1_PIN3 = 181,
+       MX51_PAD_DI1_PIN2 = 182,
+       MX51_PAD_DI_GP2 = 183,
+       MX51_PAD_DI_GP3 = 184,
+       MX51_PAD_DI2_PIN4 = 185,
+       MX51_PAD_DI2_PIN2 = 186,
+       MX51_PAD_DI2_PIN3 = 187,
+       MX51_PAD_DI2_DISP_CLK = 188,
+       MX51_PAD_DI_GP4 = 189,
+       MX51_PAD_DISP2_DAT0 = 190,
+       MX51_PAD_DISP2_DAT1 = 191,
+       MX51_PAD_DISP2_DAT2 = 192,
+       MX51_PAD_DISP2_DAT3 = 193,
+       MX51_PAD_DISP2_DAT4 = 194,
+       MX51_PAD_DISP2_DAT5 = 195,
+       MX51_PAD_DISP2_DAT6 = 196,
+       MX51_PAD_DISP2_DAT7 = 197,
+       MX51_PAD_DISP2_DAT8 = 198,
+       MX51_PAD_DISP2_DAT9 = 199,
+       MX51_PAD_DISP2_DAT10 = 200,
+       MX51_PAD_DISP2_DAT11 = 201,
+       MX51_PAD_DISP2_DAT12 = 202,
+       MX51_PAD_DISP2_DAT13 = 203,
+       MX51_PAD_DISP2_DAT14 = 204,
+       MX51_PAD_DISP2_DAT15 = 205,
+       MX51_PAD_SD1_CMD = 206,
+       MX51_PAD_SD1_CLK = 207,
+       MX51_PAD_SD1_DATA0 = 208,
+       MX51_PAD_EIM_DA0 = 209,
+       MX51_PAD_EIM_DA1 = 210,
+       MX51_PAD_EIM_DA2 = 211,
+       MX51_PAD_EIM_DA3 = 212,
+       MX51_PAD_SD1_DATA1 = 213,
+       MX51_PAD_EIM_DA4 = 214,
+       MX51_PAD_EIM_DA5 = 215,
+       MX51_PAD_EIM_DA6 = 216,
+       MX51_PAD_EIM_DA7 = 217,
+       MX51_PAD_SD1_DATA2 = 218,
+       MX51_PAD_EIM_DA10 = 219,
+       MX51_PAD_EIM_DA11 = 220,
+       MX51_PAD_EIM_DA8 = 221,
+       MX51_PAD_EIM_DA9 = 222,
+       MX51_PAD_SD1_DATA3 = 223,
+       MX51_PAD_GPIO1_0 = 224,
+       MX51_PAD_GPIO1_1 = 225,
+       MX51_PAD_EIM_DA12 = 226,
+       MX51_PAD_EIM_DA13 = 227,
+       MX51_PAD_EIM_DA14 = 228,
+       MX51_PAD_EIM_DA15 = 229,
+       MX51_PAD_SD2_CMD = 230,
+       MX51_PAD_SD2_CLK = 231,
+       MX51_PAD_SD2_DATA0 = 232,
+       MX51_PAD_SD2_DATA1 = 233,
+       MX51_PAD_SD2_DATA2 = 234,
+       MX51_PAD_SD2_DATA3 = 235,
+       MX51_PAD_GPIO1_2 = 236,
+       MX51_PAD_GPIO1_3 = 237,
+       MX51_PAD_PMIC_INT_REQ = 238,
+       MX51_PAD_GPIO1_4 = 239,
+       MX51_PAD_GPIO1_5 = 240,
+       MX51_PAD_GPIO1_6 = 241,
+       MX51_PAD_GPIO1_7 = 242,
+       MX51_PAD_GPIO1_8 = 243,
+       MX51_PAD_GPIO1_9 = 244,
 };
 
 /* imx51 register maps */
@@ -974,7 +974,7 @@ static struct imx_pin_reg imx51_pin_regs[] = {
        IMX_PIN_REG(MX51_PAD_EIM_DA13, NO_PAD, 0x050, 0, 0x000, 0), /* MX51_PAD_EIM_DA13__EIM_DA13 */
        IMX_PIN_REG(MX51_PAD_EIM_DA14, NO_PAD, 0x054, 0, 0x000, 0), /* MX51_PAD_EIM_DA14__EIM_DA14 */
        IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /* MX51_PAD_EIM_DA15__EIM_DA15 */
-       IMX_PIN_REG(MX51_PAD_SD2_CMD, NO_PAD, 0x3b4, 2, 0x91c, 3), /* MX51_PAD_SD2_CMD__CSPI_MOSI */
+       IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 2, 0x91c, 3), /* MX51_PAD_SD2_CMD__CSPI_MOSI */
        IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 1, 0x9b0, 2), /* MX51_PAD_SD2_CMD__I2C1_SCL */
        IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 0, 0x000, 0), /* MX51_PAD_SD2_CMD__SD2_CMD */
        IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 2, 0x914, 3), /* MX51_PAD_SD2_CLK__CSPI_SCLK */

diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/pinctrl-imx53.c
index 1f49e16a9bcd6afd31fe5282b267404f2d6ee22a..783feb1ce064ef50bfc498f29045b5589498c7de 100644 (file)
--- a/drivers/pinctrl/pinctrl-imx53.c
+++ b/drivers/pinctrl/pinctrl-imx53.c
@@ -23,207 +23,207 @@
 #include "pinctrl-imx.h"
 
 enum imx53_pads {
-       MX53_PAD_GPIO_19 = 1,
-       MX53_PAD_KEY_COL0 = 2,
-       MX53_PAD_KEY_ROW0 = 3,
-       MX53_PAD_KEY_COL1 = 4,
-       MX53_PAD_KEY_ROW1 = 5,
-       MX53_PAD_KEY_COL2 = 6,
-       MX53_PAD_KEY_ROW2 = 7,
-       MX53_PAD_KEY_COL3 = 8,
-       MX53_PAD_KEY_ROW3 = 9,
-       MX53_PAD_KEY_COL4 = 10,
-       MX53_PAD_KEY_ROW4 = 11,
-       MX53_PAD_DI0_DISP_CLK = 12,
-       MX53_PAD_DI0_PIN15 = 13,
-       MX53_PAD_DI0_PIN2 = 14,
-       MX53_PAD_DI0_PIN3 = 15,
-       MX53_PAD_DI0_PIN4 = 16,
-       MX53_PAD_DISP0_DAT0 = 17,
-       MX53_PAD_DISP0_DAT1 = 18,
-       MX53_PAD_DISP0_DAT2 = 19,
-       MX53_PAD_DISP0_DAT3 = 20,
-       MX53_PAD_DISP0_DAT4 = 21,
-       MX53_PAD_DISP0_DAT5 = 22,
-       MX53_PAD_DISP0_DAT6 = 23,
-       MX53_PAD_DISP0_DAT7 = 24,
-       MX53_PAD_DISP0_DAT8 = 25,
-       MX53_PAD_DISP0_DAT9 = 26,
-       MX53_PAD_DISP0_DAT10 = 27,
-       MX53_PAD_DISP0_DAT11 = 28,
-       MX53_PAD_DISP0_DAT12 = 29,
-       MX53_PAD_DISP0_DAT13 = 30,
-       MX53_PAD_DISP0_DAT14 = 31,
-       MX53_PAD_DISP0_DAT15 = 32,
-       MX53_PAD_DISP0_DAT16 = 33,
-       MX53_PAD_DISP0_DAT17 = 34,
-       MX53_PAD_DISP0_DAT18 = 35,
-       MX53_PAD_DISP0_DAT19 = 36,
-       MX53_PAD_DISP0_DAT20 = 37,
-       MX53_PAD_DISP0_DAT21 = 38,
-       MX53_PAD_DISP0_DAT22 = 39,
-       MX53_PAD_DISP0_DAT23 = 40,
-       MX53_PAD_CSI0_PIXCLK = 41,
-       MX53_PAD_CSI0_MCLK = 42,
-       MX53_PAD_CSI0_DATA_EN = 43,
-       MX53_PAD_CSI0_VSYNC = 44,
-       MX53_PAD_CSI0_DAT4 = 45,
-       MX53_PAD_CSI0_DAT5 = 46,
-       MX53_PAD_CSI0_DAT6 = 47,
-       MX53_PAD_CSI0_DAT7 = 48,
-       MX53_PAD_CSI0_DAT8 = 49,
-       MX53_PAD_CSI0_DAT9 = 50,
-       MX53_PAD_CSI0_DAT10 = 51,
-       MX53_PAD_CSI0_DAT11 = 52,
-       MX53_PAD_CSI0_DAT12 = 53,
-       MX53_PAD_CSI0_DAT13 = 54,
-       MX53_PAD_CSI0_DAT14 = 55,
-       MX53_PAD_CSI0_DAT15 = 56,
-       MX53_PAD_CSI0_DAT16 = 57,
-       MX53_PAD_CSI0_DAT17 = 58,
-       MX53_PAD_CSI0_DAT18 = 59,
-       MX53_PAD_CSI0_DAT19 = 60,
-       MX53_PAD_EIM_A25 = 61,
-       MX53_PAD_EIM_EB2 = 62,
-       MX53_PAD_EIM_D16 = 63,
-       MX53_PAD_EIM_D17 = 64,
-       MX53_PAD_EIM_D18 = 65,
-       MX53_PAD_EIM_D19 = 66,
-       MX53_PAD_EIM_D20 = 67,
-       MX53_PAD_EIM_D21 = 68,
-       MX53_PAD_EIM_D22 = 69,
-       MX53_PAD_EIM_D23 = 70,
-       MX53_PAD_EIM_EB3 = 71,
-       MX53_PAD_EIM_D24 = 72,
-       MX53_PAD_EIM_D25 = 73,
-       MX53_PAD_EIM_D26 = 74,
-       MX53_PAD_EIM_D27 = 75,
-       MX53_PAD_EIM_D28 = 76,
-       MX53_PAD_EIM_D29 = 77,
-       MX53_PAD_EIM_D30 = 78,
-       MX53_PAD_EIM_D31 = 79,
-       MX53_PAD_EIM_A24 = 80,
-       MX53_PAD_EIM_A23 = 81,
-       MX53_PAD_EIM_A22 = 82,
-       MX53_PAD_EIM_A21 = 83,
-       MX53_PAD_EIM_A20 = 84,
-       MX53_PAD_EIM_A19 = 85,
-       MX53_PAD_EIM_A18 = 86,
-       MX53_PAD_EIM_A17 = 87,
-       MX53_PAD_EIM_A16 = 88,
-       MX53_PAD_EIM_CS0 = 89,
-       MX53_PAD_EIM_CS1 = 90,
-       MX53_PAD_EIM_OE = 91,
-       MX53_PAD_EIM_RW = 92,
-       MX53_PAD_EIM_LBA = 93,
-       MX53_PAD_EIM_EB0 = 94,
-       MX53_PAD_EIM_EB1 = 95,
-       MX53_PAD_EIM_DA0 = 96,
-       MX53_PAD_EIM_DA1 = 97,
-       MX53_PAD_EIM_DA2 = 98,
-       MX53_PAD_EIM_DA3 = 99,
-       MX53_PAD_EIM_DA4 = 100,
-       MX53_PAD_EIM_DA5 = 101,
-       MX53_PAD_EIM_DA6 = 102,
-       MX53_PAD_EIM_DA7 = 103,
-       MX53_PAD_EIM_DA8 = 104,
-       MX53_PAD_EIM_DA9 = 105,
-       MX53_PAD_EIM_DA10 = 106,
-       MX53_PAD_EIM_DA11 = 107,
-       MX53_PAD_EIM_DA12 = 108,
-       MX53_PAD_EIM_DA13 = 109,
-       MX53_PAD_EIM_DA14 = 110,
-       MX53_PAD_EIM_DA15 = 111,
-       MX53_PAD_NANDF_WE_B = 112,
-       MX53_PAD_NANDF_RE_B = 113,
-       MX53_PAD_EIM_WAIT = 114,
-       MX53_PAD_LVDS1_TX3_P = 115,
-       MX53_PAD_LVDS1_TX2_P = 116,
-       MX53_PAD_LVDS1_CLK_P = 117,
-       MX53_PAD_LVDS1_TX1_P = 118,
-       MX53_PAD_LVDS1_TX0_P = 119,
-       MX53_PAD_LVDS0_TX3_P = 120,
-       MX53_PAD_LVDS0_CLK_P = 121,
-       MX53_PAD_LVDS0_TX2_P = 122,
-       MX53_PAD_LVDS0_TX1_P = 123,
-       MX53_PAD_LVDS0_TX0_P = 124,
-       MX53_PAD_GPIO_10 = 125,
-       MX53_PAD_GPIO_11 = 126,
-       MX53_PAD_GPIO_12 = 127,
-       MX53_PAD_GPIO_13 = 128,
-       MX53_PAD_GPIO_14 = 129,
-       MX53_PAD_NANDF_CLE = 130,
-       MX53_PAD_NANDF_ALE = 131,
-       MX53_PAD_NANDF_WP_B = 132,
-       MX53_PAD_NANDF_RB0 = 133,
-       MX53_PAD_NANDF_CS0 = 134,
-       MX53_PAD_NANDF_CS1 = 135,
-       MX53_PAD_NANDF_CS2 = 136,
-       MX53_PAD_NANDF_CS3 = 137,
-       MX53_PAD_FEC_MDIO = 138,
-       MX53_PAD_FEC_REF_CLK = 139,
-       MX53_PAD_FEC_RX_ER = 140,
-       MX53_PAD_FEC_CRS_DV = 141,
-       MX53_PAD_FEC_RXD1 = 142,
-       MX53_PAD_FEC_RXD0 = 143,
-       MX53_PAD_FEC_TX_EN = 144,
-       MX53_PAD_FEC_TXD1 = 145,
-       MX53_PAD_FEC_TXD0 = 146,
-       MX53_PAD_FEC_MDC = 147,
-       MX53_PAD_PATA_DIOW = 148,
-       MX53_PAD_PATA_DMACK = 149,
-       MX53_PAD_PATA_DMARQ = 150,
-       MX53_PAD_PATA_BUFFER_EN = 151,
-       MX53_PAD_PATA_INTRQ = 152,
-       MX53_PAD_PATA_DIOR = 153,
-       MX53_PAD_PATA_RESET_B = 154,
-       MX53_PAD_PATA_IORDY = 155,
-       MX53_PAD_PATA_DA_0 = 156,
-       MX53_PAD_PATA_DA_1 = 157,
-       MX53_PAD_PATA_DA_2 = 158,
-       MX53_PAD_PATA_CS_0 = 159,
-       MX53_PAD_PATA_CS_1 = 160,
-       MX53_PAD_PATA_DATA0 = 161,
-       MX53_PAD_PATA_DATA1 = 162,
-       MX53_PAD_PATA_DATA2 = 163,
-       MX53_PAD_PATA_DATA3 = 164,
-       MX53_PAD_PATA_DATA4 = 165,
-       MX53_PAD_PATA_DATA5 = 166,
-       MX53_PAD_PATA_DATA6 = 167,
-       MX53_PAD_PATA_DATA7 = 168,
-       MX53_PAD_PATA_DATA8 = 169,
-       MX53_PAD_PATA_DATA9 = 170,
-       MX53_PAD_PATA_DATA10 = 171,
-       MX53_PAD_PATA_DATA11 = 172,
-       MX53_PAD_PATA_DATA12 = 173,
-       MX53_PAD_PATA_DATA13 = 174,
-       MX53_PAD_PATA_DATA14 = 175,
-       MX53_PAD_PATA_DATA15 = 176,
-       MX53_PAD_SD1_DATA0 = 177,
-       MX53_PAD_SD1_DATA1 = 178,
-       MX53_PAD_SD1_CMD = 179,
-       MX53_PAD_SD1_DATA2 = 180,
-       MX53_PAD_SD1_CLK = 181,
-       MX53_PAD_SD1_DATA3 = 182,
-       MX53_PAD_SD2_CLK = 183,
-       MX53_PAD_SD2_CMD = 184,
-       MX53_PAD_SD2_DATA3 = 185,
-       MX53_PAD_SD2_DATA2 = 186,
-       MX53_PAD_SD2_DATA1 = 187,
-       MX53_PAD_SD2_DATA0 = 188,
-       MX53_PAD_GPIO_0 = 189,
-       MX53_PAD_GPIO_1 = 190,
-       MX53_PAD_GPIO_9 = 191,
-       MX53_PAD_GPIO_3 = 192,
-       MX53_PAD_GPIO_6 = 193,
-       MX53_PAD_GPIO_2 = 194,
-       MX53_PAD_GPIO_4 = 195,
-       MX53_PAD_GPIO_5 = 196,
-       MX53_PAD_GPIO_7 = 197,
-       MX53_PAD_GPIO_8 = 198,
-       MX53_PAD_GPIO_16 = 199,
-       MX53_PAD_GPIO_17 = 200,
-       MX53_PAD_GPIO_18 = 201,
+       MX53_PAD_GPIO_19 = 0,
+       MX53_PAD_KEY_COL0 = 1,
+       MX53_PAD_KEY_ROW0 = 2,
+       MX53_PAD_KEY_COL1 = 3,
+       MX53_PAD_KEY_ROW1 = 4,
+       MX53_PAD_KEY_COL2 = 5,
+       MX53_PAD_KEY_ROW2 = 6,
+       MX53_PAD_KEY_COL3 = 7,
+       MX53_PAD_KEY_ROW3 = 8,
+       MX53_PAD_KEY_COL4 = 9,
+       MX53_PAD_KEY_ROW4 = 10,
+       MX53_PAD_DI0_DISP_CLK = 11,
+       MX53_PAD_DI0_PIN15 = 12,
+       MX53_PAD_DI0_PIN2 = 13,
+       MX53_PAD_DI0_PIN3 = 14,
+       MX53_PAD_DI0_PIN4 = 15,
+       MX53_PAD_DISP0_DAT0 = 16,
+       MX53_PAD_DISP0_DAT1 = 17,
+       MX53_PAD_DISP0_DAT2 = 18,
+       MX53_PAD_DISP0_DAT3 = 19,
+       MX53_PAD_DISP0_DAT4 = 20,
+       MX53_PAD_DISP0_DAT5 = 21,
+       MX53_PAD_DISP0_DAT6 = 22,
+       MX53_PAD_DISP0_DAT7 = 23,
+       MX53_PAD_DISP0_DAT8 = 24,
+       MX53_PAD_DISP0_DAT9 = 25,
+       MX53_PAD_DISP0_DAT10 = 26,
+       MX53_PAD_DISP0_DAT11 = 27,
+       MX53_PAD_DISP0_DAT12 = 28,
+       MX53_PAD_DISP0_DAT13 = 29,
+       MX53_PAD_DISP0_DAT14 = 30,
+       MX53_PAD_DISP0_DAT15 = 31,
+       MX53_PAD_DISP0_DAT16 = 32,
+       MX53_PAD_DISP0_DAT17 = 33,
+       MX53_PAD_DISP0_DAT18 = 34,
+       MX53_PAD_DISP0_DAT19 = 35,
+       MX53_PAD_DISP0_DAT20 = 36,
+       MX53_PAD_DISP0_DAT21 = 37,
+       MX53_PAD_DISP0_DAT22 = 38,
+       MX53_PAD_DISP0_DAT23 = 39,
+       MX53_PAD_CSI0_PIXCLK = 40,
+       MX53_PAD_CSI0_MCLK = 41,
+       MX53_PAD_CSI0_DATA_EN = 42,
+       MX53_PAD_CSI0_VSYNC = 43,
+       MX53_PAD_CSI0_DAT4 = 44,
+       MX53_PAD_CSI0_DAT5 = 45,
+       MX53_PAD_CSI0_DAT6 = 46,
+       MX53_PAD_CSI0_DAT7 = 47,
+       MX53_PAD_CSI0_DAT8 = 48,
+       MX53_PAD_CSI0_DAT9 = 49,
+       MX53_PAD_CSI0_DAT10 = 50,
+       MX53_PAD_CSI0_DAT11 = 51,
+       MX53_PAD_CSI0_DAT12 = 52,
+       MX53_PAD_CSI0_DAT13 = 53,
+       MX53_PAD_CSI0_DAT14 = 54,
+       MX53_PAD_CSI0_DAT15 = 55,
+       MX53_PAD_CSI0_DAT16 = 56,
+       MX53_PAD_CSI0_DAT17 = 57,
+       MX53_PAD_CSI0_DAT18 = 58,
+       MX53_PAD_CSI0_DAT19 = 59,
+       MX53_PAD_EIM_A25 = 60,
+       MX53_PAD_EIM_EB2 = 61,
+       MX53_PAD_EIM_D16 = 62,
+       MX53_PAD_EIM_D17 = 63,
+       MX53_PAD_EIM_D18 = 64,
+       MX53_PAD_EIM_D19 = 65,
+       MX53_PAD_EIM_D20 = 66,
+       MX53_PAD_EIM_D21 = 67,
+       MX53_PAD_EIM_D22 = 68,
+       MX53_PAD_EIM_D23 = 69,
+       MX53_PAD_EIM_EB3 = 70,
+       MX53_PAD_EIM_D24 = 71,
+       MX53_PAD_EIM_D25 = 72,
+       MX53_PAD_EIM_D26 = 73,
+       MX53_PAD_EIM_D27 = 74,
+       MX53_PAD_EIM_D28 = 75,
+       MX53_PAD_EIM_D29 = 76,
+       MX53_PAD_EIM_D30 = 77,
+       MX53_PAD_EIM_D31 = 78,
+       MX53_PAD_EIM_A24 = 79,
+       MX53_PAD_EIM_A23 = 80,
+       MX53_PAD_EIM_A22 = 81,
+       MX53_PAD_EIM_A21 = 82,
+       MX53_PAD_EIM_A20 = 83,
+       MX53_PAD_EIM_A19 = 84,
+       MX53_PAD_EIM_A18 = 85,
+       MX53_PAD_EIM_A17 = 86,
+       MX53_PAD_EIM_A16 = 87,
+       MX53_PAD_EIM_CS0 = 88,
+       MX53_PAD_EIM_CS1 = 89,
+       MX53_PAD_EIM_OE = 90,
+       MX53_PAD_EIM_RW = 91,
+       MX53_PAD_EIM_LBA = 92,
+       MX53_PAD_EIM_EB0 = 93,
+       MX53_PAD_EIM_EB1 = 94,
+       MX53_PAD_EIM_DA0 = 95,
+       MX53_PAD_EIM_DA1 = 96,
+       MX53_PAD_EIM_DA2 = 97,
+       MX53_PAD_EIM_DA3 = 98,
+       MX53_PAD_EIM_DA4 = 99,
+       MX53_PAD_EIM_DA5 = 100,
+       MX53_PAD_EIM_DA6 = 101,
+       MX53_PAD_EIM_DA7 = 102,
+       MX53_PAD_EIM_DA8 = 103,
+       MX53_PAD_EIM_DA9 = 104,
+       MX53_PAD_EIM_DA10 = 105,
+       MX53_PAD_EIM_DA11 = 106,
+       MX53_PAD_EIM_DA12 = 107,
+       MX53_PAD_EIM_DA13 = 108,
+       MX53_PAD_EIM_DA14 = 109,
+       MX53_PAD_EIM_DA15 = 110,
+       MX53_PAD_NANDF_WE_B = 111,
+       MX53_PAD_NANDF_RE_B = 112,
+       MX53_PAD_EIM_WAIT = 113,
+       MX53_PAD_LVDS1_TX3_P = 114,
+       MX53_PAD_LVDS1_TX2_P = 115,
+       MX53_PAD_LVDS1_CLK_P = 116,
+       MX53_PAD_LVDS1_TX1_P = 117,
+       MX53_PAD_LVDS1_TX0_P = 118,
+       MX53_PAD_LVDS0_TX3_P = 119,
+       MX53_PAD_LVDS0_CLK_P = 120,
+       MX53_PAD_LVDS0_TX2_P = 121,
+       MX53_PAD_LVDS0_TX1_P = 122,
+       MX53_PAD_LVDS0_TX0_P = 123,
+       MX53_PAD_GPIO_10 = 124,
+       MX53_PAD_GPIO_11 = 125,
+       MX53_PAD_GPIO_12 = 126,
+       MX53_PAD_GPIO_13 = 127,
+       MX53_PAD_GPIO_14 = 128,
+       MX53_PAD_NANDF_CLE = 129,
+       MX53_PAD_NANDF_ALE = 130,
+       MX53_PAD_NANDF_WP_B = 131,
+       MX53_PAD_NANDF_RB0 = 132,
+       MX53_PAD_NANDF_CS0 = 133,
+       MX53_PAD_NANDF_CS1 = 134,
+       MX53_PAD_NANDF_CS2 = 135,
+       MX53_PAD_NANDF_CS3 = 136,
+       MX53_PAD_FEC_MDIO = 137,
+       MX53_PAD_FEC_REF_CLK = 138,
+       MX53_PAD_FEC_RX_ER = 139,
+       MX53_PAD_FEC_CRS_DV = 140,
+       MX53_PAD_FEC_RXD1 = 141,
+       MX53_PAD_FEC_RXD0 = 142,
+       MX53_PAD_FEC_TX_EN = 143,
+       MX53_PAD_FEC_TXD1 = 144,
+       MX53_PAD_FEC_TXD0 = 145,
+       MX53_PAD_FEC_MDC = 146,
+       MX53_PAD_PATA_DIOW = 147,
+       MX53_PAD_PATA_DMACK = 148,
+       MX53_PAD_PATA_DMARQ = 149,
+       MX53_PAD_PATA_BUFFER_EN = 150,
+       MX53_PAD_PATA_INTRQ = 151,
+       MX53_PAD_PATA_DIOR = 152,
+       MX53_PAD_PATA_RESET_B = 153,
+       MX53_PAD_PATA_IORDY = 154,
+       MX53_PAD_PATA_DA_0 = 155,
+       MX53_PAD_PATA_DA_1 = 156,
+       MX53_PAD_PATA_DA_2 = 157,
+       MX53_PAD_PATA_CS_0 = 158,
+       MX53_PAD_PATA_CS_1 = 159,
+       MX53_PAD_PATA_DATA0 = 160,
+       MX53_PAD_PATA_DATA1 = 161,
+       MX53_PAD_PATA_DATA2 = 162,
+       MX53_PAD_PATA_DATA3 = 163,
+       MX53_PAD_PATA_DATA4 = 164,
+       MX53_PAD_PATA_DATA5 = 165,
+       MX53_PAD_PATA_DATA6 = 166,
+       MX53_PAD_PATA_DATA7 = 167,
+       MX53_PAD_PATA_DATA8 = 168,
+       MX53_PAD_PATA_DATA9 = 169,
+       MX53_PAD_PATA_DATA10 = 170,
+       MX53_PAD_PATA_DATA11 = 171,
+       MX53_PAD_PATA_DATA12 = 172,
+       MX53_PAD_PATA_DATA13 = 173,
+       MX53_PAD_PATA_DATA14 = 174,
+       MX53_PAD_PATA_DATA15 = 175,
+       MX53_PAD_SD1_DATA0 = 176,
+       MX53_PAD_SD1_DATA1 = 177,
+       MX53_PAD_SD1_CMD = 178,
+       MX53_PAD_SD1_DATA2 = 179,
+       MX53_PAD_SD1_CLK = 180,
+       MX53_PAD_SD1_DATA3 = 181,
+       MX53_PAD_SD2_CLK = 182,
+       MX53_PAD_SD2_CMD = 183,
+       MX53_PAD_SD2_DATA3 = 184,
+       MX53_PAD_SD2_DATA2 = 185,
+       MX53_PAD_SD2_DATA1 = 186,
+       MX53_PAD_SD2_DATA0 = 187,
+       MX53_PAD_GPIO_0 = 188,
+       MX53_PAD_GPIO_1 = 189,
+       MX53_PAD_GPIO_9 = 190,
+       MX53_PAD_GPIO_3 = 191,
+       MX53_PAD_GPIO_6 = 192,
+       MX53_PAD_GPIO_2 = 193,
+       MX53_PAD_GPIO_4 = 194,
+       MX53_PAD_GPIO_5 = 195,
+       MX53_PAD_GPIO_7 = 196,
+       MX53_PAD_GPIO_8 = 197,
+       MX53_PAD_GPIO_16 = 198,
+       MX53_PAD_GPIO_17 = 199,
+       MX53_PAD_GPIO_18 = 200,
 };
 
 /* imx53 register maps */

diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c
index 5f3e9d0221e11c641e01ed300d673be0807f5d00..a39fb7a6fc5142b86a65630bd5a208c84b94cd9a 100644 (file)
--- a/drivers/pinctrl/pinctrl-nomadik-db8500.c
+++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c
@@ -505,6 +505,8 @@ static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
        DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1,
        DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2,
        DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 };
+static const unsigned kp_b_2_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
+       DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_F4, DB8500_PIN_E3};
 static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
        DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
        DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
@@ -662,6 +664,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
        DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B),
        DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
        DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
+       DB8500_PIN_GROUP(kp_b_2, NMK_GPIO_ALT_B),
        DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
        DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
        DB8500_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B),
@@ -751,7 +754,7 @@ DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1");
 DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1");
 DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1",
        "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1");
-DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
+DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_b_2", "kp_c_1", "kp_oc1_1");
 DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
 DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1");
 DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1");

diff --git a/drivers/pinctrl/pinctrl-nomadik-db8540.c b/drivers/pinctrl/pinctrl-nomadik-db8540.c
new file mode 100644 (file)
index 0000000..3daf665
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik-db8540.c
@@ -0,0 +1,999 @@
+#include <linux/kernel.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-nomadik.h"
+
+/* All the pins that can be used for GPIO and some other functions */
+#define _GPIO(offset)          (offset)
+
+#define DB8540_PIN_AH6         _GPIO(0)
+#define DB8540_PIN_AG7         _GPIO(1)
+#define DB8540_PIN_AF2         _GPIO(2)
+#define DB8540_PIN_AD3         _GPIO(3)
+#define DB8540_PIN_AF6         _GPIO(4)
+#define DB8540_PIN_AG6         _GPIO(5)
+#define DB8540_PIN_AD5         _GPIO(6)
+#define DB8540_PIN_AF7         _GPIO(7)
+#define DB8540_PIN_AG5         _GPIO(8)
+#define DB8540_PIN_AH5         _GPIO(9)
+#define DB8540_PIN_AE4         _GPIO(10)
+#define DB8540_PIN_AD1         _GPIO(11)
+#define DB8540_PIN_AD2         _GPIO(12)
+#define DB8540_PIN_AC2         _GPIO(13)
+#define DB8540_PIN_AC4         _GPIO(14)
+#define DB8540_PIN_AC3         _GPIO(15)
+#define DB8540_PIN_AH7         _GPIO(16)
+#define DB8540_PIN_AE7         _GPIO(17)
+/* Hole */
+#define DB8540_PIN_AF8         _GPIO(22)
+#define DB8540_PIN_AH11                _GPIO(23)
+#define DB8540_PIN_AG11                _GPIO(24)
+#define DB8540_PIN_AF11                _GPIO(25)
+#define DB8540_PIN_AH10                _GPIO(26)
+#define DB8540_PIN_AG10                _GPIO(27)
+#define DB8540_PIN_AF10                _GPIO(28)
+/* Hole */
+#define DB8540_PIN_AD4         _GPIO(33)
+#define DB8540_PIN_AF3         _GPIO(34)
+#define DB8540_PIN_AF5         _GPIO(35)
+#define DB8540_PIN_AG4         _GPIO(36)
+#define DB8540_PIN_AF9         _GPIO(37)
+#define DB8540_PIN_AE8         _GPIO(38)
+/* Hole */
+#define DB8540_PIN_M26         _GPIO(64)
+#define DB8540_PIN_M25         _GPIO(65)
+#define DB8540_PIN_M27         _GPIO(66)
+#define DB8540_PIN_N25         _GPIO(67)
+/* Hole */
+#define DB8540_PIN_M28         _GPIO(70)
+#define DB8540_PIN_N26         _GPIO(71)
+#define DB8540_PIN_M22         _GPIO(72)
+#define DB8540_PIN_N22         _GPIO(73)
+#define DB8540_PIN_N27         _GPIO(74)
+#define DB8540_PIN_N28         _GPIO(75)
+#define DB8540_PIN_P22         _GPIO(76)
+#define DB8540_PIN_P28         _GPIO(77)
+#define DB8540_PIN_P26         _GPIO(78)
+#define DB8540_PIN_T22         _GPIO(79)
+#define DB8540_PIN_R27         _GPIO(80)
+#define DB8540_PIN_P27         _GPIO(81)
+#define DB8540_PIN_R26         _GPIO(82)
+#define DB8540_PIN_R25         _GPIO(83)
+#define DB8540_PIN_U22         _GPIO(84)
+#define DB8540_PIN_T27         _GPIO(85)
+#define DB8540_PIN_T25         _GPIO(86)
+#define DB8540_PIN_T26         _GPIO(87)
+/* Hole */
+#define DB8540_PIN_AF20                _GPIO(116)
+#define DB8540_PIN_AG21                _GPIO(117)
+#define DB8540_PIN_AH19                _GPIO(118)
+#define DB8540_PIN_AE19                _GPIO(119)
+#define DB8540_PIN_AG18                _GPIO(120)
+#define DB8540_PIN_AH17                _GPIO(121)
+#define DB8540_PIN_AF19                _GPIO(122)
+#define DB8540_PIN_AF18                _GPIO(123)
+#define DB8540_PIN_AE18                _GPIO(124)
+#define DB8540_PIN_AG17                _GPIO(125)
+#define DB8540_PIN_AF17                _GPIO(126)
+#define DB8540_PIN_AE17                _GPIO(127)
+#define DB8540_PIN_AC27                _GPIO(128)
+#define DB8540_PIN_AD27                _GPIO(129)
+#define DB8540_PIN_AE28                _GPIO(130)
+#define DB8540_PIN_AG26                _GPIO(131)
+#define DB8540_PIN_AF25                _GPIO(132)
+#define DB8540_PIN_AE27                _GPIO(133)
+#define DB8540_PIN_AF27                _GPIO(134)
+#define DB8540_PIN_AG28                _GPIO(135)
+#define DB8540_PIN_AF28                _GPIO(136)
+#define DB8540_PIN_AG25                _GPIO(137)
+#define DB8540_PIN_AG24                _GPIO(138)
+#define DB8540_PIN_AD25                _GPIO(139)
+#define DB8540_PIN_AH25                _GPIO(140)
+#define DB8540_PIN_AF26                _GPIO(141)
+#define DB8540_PIN_AF23                _GPIO(142)
+#define DB8540_PIN_AG23                _GPIO(143)
+#define DB8540_PIN_AE25                _GPIO(144)
+#define DB8540_PIN_AH24                _GPIO(145)
+#define DB8540_PIN_AJ25                _GPIO(146)
+#define DB8540_PIN_AG27                _GPIO(147)
+#define DB8540_PIN_AH23                _GPIO(148)
+#define DB8540_PIN_AE26                _GPIO(149)
+#define DB8540_PIN_AE24                _GPIO(150)
+#define DB8540_PIN_AJ24                _GPIO(151)
+#define DB8540_PIN_AE21                _GPIO(152)
+#define DB8540_PIN_AG22                _GPIO(153)
+#define DB8540_PIN_AF21                _GPIO(154)
+#define DB8540_PIN_AF24                _GPIO(155)
+#define DB8540_PIN_AH22                _GPIO(156)
+#define DB8540_PIN_AJ23                _GPIO(157)
+#define DB8540_PIN_AH21                _GPIO(158)
+#define DB8540_PIN_AG20                _GPIO(159)
+#define DB8540_PIN_AE23                _GPIO(160)
+#define DB8540_PIN_AH20                _GPIO(161)
+#define DB8540_PIN_AG19                _GPIO(162)
+#define DB8540_PIN_AF22                _GPIO(163)
+#define DB8540_PIN_AJ21                _GPIO(164)
+#define DB8540_PIN_AD26                _GPIO(165)
+#define DB8540_PIN_AD28                _GPIO(166)
+#define DB8540_PIN_AC28                _GPIO(167)
+#define DB8540_PIN_AC26                _GPIO(168)
+/* Hole */
+#define DB8540_PIN_J3          _GPIO(192)
+#define DB8540_PIN_H1          _GPIO(193)
+#define DB8540_PIN_J2          _GPIO(194)
+#define DB8540_PIN_H2          _GPIO(195)
+#define DB8540_PIN_H3          _GPIO(196)
+#define DB8540_PIN_H4          _GPIO(197)
+#define DB8540_PIN_G2          _GPIO(198)
+#define DB8540_PIN_G3          _GPIO(199)
+#define DB8540_PIN_G4          _GPIO(200)
+#define DB8540_PIN_F2          _GPIO(201)
+#define DB8540_PIN_C6          _GPIO(202)
+#define DB8540_PIN_B6          _GPIO(203)
+#define DB8540_PIN_B7          _GPIO(204)
+#define DB8540_PIN_A7          _GPIO(205)
+#define DB8540_PIN_D7          _GPIO(206)
+#define DB8540_PIN_D8          _GPIO(207)
+#define DB8540_PIN_F3          _GPIO(208)
+#define DB8540_PIN_E2          _GPIO(209)
+#define DB8540_PIN_C7          _GPIO(210)
+#define DB8540_PIN_B8          _GPIO(211)
+#define DB8540_PIN_C10         _GPIO(212)
+#define DB8540_PIN_C8          _GPIO(213)
+#define DB8540_PIN_C9          _GPIO(214)
+/* Hole */
+#define DB8540_PIN_B9          _GPIO(219)
+#define DB8540_PIN_A10         _GPIO(220)
+#define DB8540_PIN_D9          _GPIO(221)
+#define DB8540_PIN_B11         _GPIO(222)
+#define DB8540_PIN_B10         _GPIO(223)
+#define DB8540_PIN_E10         _GPIO(224)
+#define DB8540_PIN_B12         _GPIO(225)
+#define DB8540_PIN_D10         _GPIO(226)
+#define DB8540_PIN_D11         _GPIO(227)
+#define DB8540_PIN_AJ6         _GPIO(228)
+#define DB8540_PIN_B13         _GPIO(229)
+#define DB8540_PIN_C12         _GPIO(230)
+#define DB8540_PIN_B14         _GPIO(231)
+#define DB8540_PIN_E11         _GPIO(232)
+/* Hole */
+#define DB8540_PIN_D12         _GPIO(256)
+#define DB8540_PIN_D15         _GPIO(257)
+#define DB8540_PIN_C13         _GPIO(258)
+#define DB8540_PIN_C14         _GPIO(259)
+#define DB8540_PIN_C18         _GPIO(260)
+#define DB8540_PIN_C16         _GPIO(261)
+#define DB8540_PIN_B16         _GPIO(262)
+#define DB8540_PIN_D18         _GPIO(263)
+#define DB8540_PIN_C15         _GPIO(264)
+#define DB8540_PIN_C17         _GPIO(265)
+#define DB8540_PIN_B17         _GPIO(266)
+#define DB8540_PIN_D17         _GPIO(267)
+
+/*
+ * The names of the pins are denoted by GPIO number and ball name, even
+ * though they can be used for other things than GPIO, this is the first
+ * column in the table of the data sheet and often used on schematics and
+ * such.
+ */
+static const struct pinctrl_pin_desc nmk_db8540_pins[] = {
+       PINCTRL_PIN(DB8540_PIN_AH6, "GPIO0_AH6"),
+       PINCTRL_PIN(DB8540_PIN_AG7, "GPIO1_AG7"),
+       PINCTRL_PIN(DB8540_PIN_AF2, "GPIO2_AF2"),
+       PINCTRL_PIN(DB8540_PIN_AD3, "GPIO3_AD3"),
+       PINCTRL_PIN(DB8540_PIN_AF6, "GPIO4_AF6"),
+       PINCTRL_PIN(DB8540_PIN_AG6, "GPIO5_AG6"),
+       PINCTRL_PIN(DB8540_PIN_AD5, "GPIO6_AD5"),
+       PINCTRL_PIN(DB8540_PIN_AF7, "GPIO7_AF7"),
+       PINCTRL_PIN(DB8540_PIN_AG5, "GPIO8_AG5"),
+       PINCTRL_PIN(DB8540_PIN_AH5, "GPIO9_AH5"),
+       PINCTRL_PIN(DB8540_PIN_AE4, "GPIO10_AE4"),
+       PINCTRL_PIN(DB8540_PIN_AD1, "GPIO11_AD1"),
+       PINCTRL_PIN(DB8540_PIN_AD2, "GPIO12_AD2"),
+       PINCTRL_PIN(DB8540_PIN_AC2, "GPIO13_AC2"),
+       PINCTRL_PIN(DB8540_PIN_AC4, "GPIO14_AC4"),
+       PINCTRL_PIN(DB8540_PIN_AC3, "GPIO15_AC3"),
+       PINCTRL_PIN(DB8540_PIN_AH7, "GPIO16_AH7"),
+       PINCTRL_PIN(DB8540_PIN_AE7, "GPIO17_AE7"),
+       /* Hole */
+       PINCTRL_PIN(DB8540_PIN_AF8, "GPIO22_AF8"),
+       PINCTRL_PIN(DB8540_PIN_AH11, "GPIO23_AH11"),
+       PINCTRL_PIN(DB8540_PIN_AG11, "GPIO24_AG11"),
+       PINCTRL_PIN(DB8540_PIN_AF11, "GPIO25_AF11"),
+       PINCTRL_PIN(DB8540_PIN_AH10, "GPIO26_AH10"),
+       PINCTRL_PIN(DB8540_PIN_AG10, "GPIO27_AG10"),
+       PINCTRL_PIN(DB8540_PIN_AF10, "GPIO28_AF10"),
+       /* Hole */
+       PINCTRL_PIN(DB8540_PIN_AD4, "GPIO33_AD4"),
+       PINCTRL_PIN(DB8540_PIN_AF3, "GPIO34_AF3"),
+       PINCTRL_PIN(DB8540_PIN_AF5, "GPIO35_AF5"),
+       PINCTRL_PIN(DB8540_PIN_AG4, "GPIO36_AG4"),
+       PINCTRL_PIN(DB8540_PIN_AF9, "GPIO37_AF9"),
+       PINCTRL_PIN(DB8540_PIN_AE8, "GPIO38_AE8"),
+       /* Hole */
+       PINCTRL_PIN(DB8540_PIN_M26, "GPIO64_M26"),
+       PINCTRL_PIN(DB8540_PIN_M25, "GPIO65_M25"),
+       PINCTRL_PIN(DB8540_PIN_M27, "GPIO66_M27"),
+       PINCTRL_PIN(DB8540_PIN_N25, "GPIO67_N25"),
+       /* Hole */
+       PINCTRL_PIN(DB8540_PIN_M28, "GPIO70_M28"),
+       PINCTRL_PIN(DB8540_PIN_N26, "GPIO71_N26"),
+       PINCTRL_PIN(DB8540_PIN_M22, "GPIO72_M22"),
+       PINCTRL_PIN(DB8540_PIN_N22, "GPIO73_N22"),
+       PINCTRL_PIN(DB8540_PIN_N27, "GPIO74_N27"),
+       PINCTRL_PIN(DB8540_PIN_N28, "GPIO75_N28"),
+       PINCTRL_PIN(DB8540_PIN_P22, "GPIO76_P22"),
+       PINCTRL_PIN(DB8540_PIN_P28, "GPIO77_P28"),
+       PINCTRL_PIN(DB8540_PIN_P26, "GPIO78_P26"),
+       PINCTRL_PIN(DB8540_PIN_T22, "GPIO79_T22"),
+       PINCTRL_PIN(DB8540_PIN_R27, "GPIO80_R27"),
+       PINCTRL_PIN(DB8540_PIN_P27, "GPIO81_P27"),
+       PINCTRL_PIN(DB8540_PIN_R26, "GPIO82_R26"),
+       PINCTRL_PIN(DB8540_PIN_R25, "GPIO83_R25"),
+       PINCTRL_PIN(DB8540_PIN_U22, "GPIO84_U22"),
+       PINCTRL_PIN(DB8540_PIN_T27, "GPIO85_T27"),
+       PINCTRL_PIN(DB8540_PIN_T25, "GPIO86_T25"),
+       PINCTRL_PIN(DB8540_PIN_T26, "GPIO87_T26"),
+       /* Hole */
+       PINCTRL_PIN(DB8540_PIN_AF20, "GPIO116_AF20"),
+       PINCTRL_PIN(DB8540_PIN_AG21, "GPIO117_AG21"),
+       PINCTRL_PIN(DB8540_PIN_AH19, "GPIO118_AH19"),
+       PINCTRL_PIN(DB8540_PIN_AE19, "GPIO119_AE19"),
+       PINCTRL_PIN(DB8540_PIN_AG18, "GPIO120_AG18"),
+       PINCTRL_PIN(DB8540_PIN_AH17, "GPIO121_AH17"),
+       PINCTRL_PIN(DB8540_PIN_AF19, "GPIO122_AF19"),
+       PINCTRL_PIN(DB8540_PIN_AF18, "GPIO123_AF18"),
+       PINCTRL_PIN(DB8540_PIN_AE18, "GPIO124_AE18"),
+       PINCTRL_PIN(DB8540_PIN_AG17, "GPIO125_AG17"),
+       PINCTRL_PIN(DB8540_PIN_AF17, "GPIO126_AF17"),
+       PINCTRL_PIN(DB8540_PIN_AE17, "GPIO127_AE17"),
+       PINCTRL_PIN(DB8540_PIN_AC27, "GPIO128_AC27"),
+       PINCTRL_PIN(DB8540_PIN_AD27, "GPIO129_AD27"),
+       PINCTRL_PIN(DB8540_PIN_AE28, "GPIO130_AE28"),
+       PINCTRL_PIN(DB8540_PIN_AG26, "GPIO131_AG26"),
+       PINCTRL_PIN(DB8540_PIN_AF25, "GPIO132_AF25"),
+       PINCTRL_PIN(DB8540_PIN_AE27, "GPIO133_AE27"),
+       PINCTRL_PIN(DB8540_PIN_AF27, "GPIO134_AF27"),
+       PINCTRL_PIN(DB8540_PIN_AG28, "GPIO135_AG28"),
+       PINCTRL_PIN(DB8540_PIN_AF28, "GPIO136_AF28"),
+       PINCTRL_PIN(DB8540_PIN_AG25, "GPIO137_AG25"),
+       PINCTRL_PIN(DB8540_PIN_AG24, "GPIO138_AG24"),
+       PINCTRL_PIN(DB8540_PIN_AD25, "GPIO139_AD25"),
+       PINCTRL_PIN(DB8540_PIN_AH25, "GPIO140_AH25"),
+       PINCTRL_PIN(DB8540_PIN_AF26, "GPIO141_AF26"),
+       PINCTRL_PIN(DB8540_PIN_AF23, "GPIO142_AF23"),
+       PINCTRL_PIN(DB8540_PIN_AG23, "GPIO143_AG23"),
+       PINCTRL_PIN(DB8540_PIN_AE25, "GPIO144_AE25"),
+       PINCTRL_PIN(DB8540_PIN_AH24, "GPIO145_AH24"),
+       PINCTRL_PIN(DB8540_PIN_AJ25, "GPIO146_AJ25"),
+       PINCTRL_PIN(DB8540_PIN_AG27, "GPIO147_AG27"),
+       PINCTRL_PIN(DB8540_PIN_AH23, "GPIO148_AH23"),
+       PINCTRL_PIN(DB8540_PIN_AE26, "GPIO149_AE26"),
+       PINCTRL_PIN(DB8540_PIN_AE24, "GPIO150_AE24"),
+       PINCTRL_PIN(DB8540_PIN_AJ24, "GPIO151_AJ24"),
+       PINCTRL_PIN(DB8540_PIN_AE21, "GPIO152_AE21"),
+       PINCTRL_PIN(DB8540_PIN_AG22, "GPIO153_AG22"),
+       PINCTRL_PIN(DB8540_PIN_AF21, "GPIO154_AF21"),
+       PINCTRL_PIN(DB8540_PIN_AF24, "GPIO155_AF24"),
+       PINCTRL_PIN(DB8540_PIN_AH22, "GPIO156_AH22"),
+       PINCTRL_PIN(DB8540_PIN_AJ23, "GPIO157_AJ23"),
+       PINCTRL_PIN(DB8540_PIN_AH21, "GPIO158_AH21"),
+       PINCTRL_PIN(DB8540_PIN_AG20, "GPIO159_AG20"),
+       PINCTRL_PIN(DB8540_PIN_AE23, "GPIO160_AE23"),
+       PINCTRL_PIN(DB8540_PIN_AH20, "GPIO161_AH20"),
+       PINCTRL_PIN(DB8540_PIN_AG19, "GPIO162_AG19"),
+       PINCTRL_PIN(DB8540_PIN_AF22, "GPIO163_AF22"),
+       PINCTRL_PIN(DB8540_PIN_AJ21, "GPIO164_AJ21"),
+       PINCTRL_PIN(DB8540_PIN_AD26, "GPIO165_AD26"),
+       PINCTRL_PIN(DB8540_PIN_AD28, "GPIO166_AD28"),
+       PINCTRL_PIN(DB8540_PIN_AC28, "GPIO167_AC28"),
+       PINCTRL_PIN(DB8540_PIN_AC26, "GPIO168_AC26"),
+       /* Hole */
+       PINCTRL_PIN(DB8540_PIN_J3, "GPIO192_J3"),
+       PINCTRL_PIN(DB8540_PIN_H1, "GPIO193_H1"),
+       PINCTRL_PIN(DB8540_PIN_J2, "GPIO194_J2"),
+       PINCTRL_PIN(DB8540_PIN_H2, "GPIO195_H2"),
+       PINCTRL_PIN(DB8540_PIN_H3, "GPIO196_H3"),
+       PINCTRL_PIN(DB8540_PIN_H4, "GPIO197_H4"),
+       PINCTRL_PIN(DB8540_PIN_G2, "GPIO198_G2"),
+       PINCTRL_PIN(DB8540_PIN_G3, "GPIO199_G3"),
+       PINCTRL_PIN(DB8540_PIN_G4, "GPIO200_G4"),
+       PINCTRL_PIN(DB8540_PIN_F2, "GPIO201_F2"),
+       PINCTRL_PIN(DB8540_PIN_C6, "GPIO202_C6"),
+       PINCTRL_PIN(DB8540_PIN_B6, "GPIO203_B6"),
+       PINCTRL_PIN(DB8540_PIN_B7, "GPIO204_B7"),
+       PINCTRL_PIN(DB8540_PIN_A7, "GPIO205_A7"),
+       PINCTRL_PIN(DB8540_PIN_D7, "GPIO206_D7"),
+       PINCTRL_PIN(DB8540_PIN_D8, "GPIO207_D8"),
+       PINCTRL_PIN(DB8540_PIN_F3, "GPIO208_F3"),
+       PINCTRL_PIN(DB8540_PIN_E2, "GPIO209_E2"),
+       PINCTRL_PIN(DB8540_PIN_C7, "GPIO210_C7"),
+       PINCTRL_PIN(DB8540_PIN_B8, "GPIO211_B8"),
+       PINCTRL_PIN(DB8540_PIN_C10, "GPIO212_C10"),
+       PINCTRL_PIN(DB8540_PIN_C8, "GPIO213_C8"),
+       PINCTRL_PIN(DB8540_PIN_C9, "GPIO214_C9"),
+       /* Hole */
+       PINCTRL_PIN(DB8540_PIN_B9, "GPIO219_B9"),
+       PINCTRL_PIN(DB8540_PIN_A10, "GPIO220_A10"),
+       PINCTRL_PIN(DB8540_PIN_D9, "GPIO221_D9"),
+       PINCTRL_PIN(DB8540_PIN_B11, "GPIO222_B11"),
+       PINCTRL_PIN(DB8540_PIN_B10, "GPIO223_B10"),
+       PINCTRL_PIN(DB8540_PIN_E10, "GPIO224_E10"),
+       PINCTRL_PIN(DB8540_PIN_B12, "GPIO225_B12"),
+       PINCTRL_PIN(DB8540_PIN_D10, "GPIO226_D10"),
+       PINCTRL_PIN(DB8540_PIN_D11, "GPIO227_D11"),
+       PINCTRL_PIN(DB8540_PIN_AJ6, "GPIO228_AJ6"),
+       PINCTRL_PIN(DB8540_PIN_B13, "GPIO229_B13"),
+       PINCTRL_PIN(DB8540_PIN_C12, "GPIO230_C12"),
+       PINCTRL_PIN(DB8540_PIN_B14, "GPIO231_B14"),
+       PINCTRL_PIN(DB8540_PIN_E11, "GPIO232_E11"),
+       /* Hole */
+       PINCTRL_PIN(DB8540_PIN_D12, "GPIO256_D12"),
+       PINCTRL_PIN(DB8540_PIN_D15, "GPIO257_D15"),
+       PINCTRL_PIN(DB8540_PIN_C13, "GPIO258_C13"),
+       PINCTRL_PIN(DB8540_PIN_C14, "GPIO259_C14"),
+       PINCTRL_PIN(DB8540_PIN_C18, "GPIO260_C18"),
+       PINCTRL_PIN(DB8540_PIN_C16, "GPIO261_C16"),
+       PINCTRL_PIN(DB8540_PIN_B16, "GPIO262_B16"),
+       PINCTRL_PIN(DB8540_PIN_D18, "GPIO263_D18"),
+       PINCTRL_PIN(DB8540_PIN_C15, "GPIO264_C15"),
+       PINCTRL_PIN(DB8540_PIN_C17, "GPIO265_C17"),
+       PINCTRL_PIN(DB8540_PIN_B17, "GPIO266_B17"),
+       PINCTRL_PIN(DB8540_PIN_D17, "GPIO267_D17"),
+};
+
+#define DB8540_GPIO_RANGE(a, b, c) { .name = "db8540", .id = a, .base = b, \
+                       .pin_base = b, .npins = c }
+
+/*
+ * This matches the 32-pin gpio chips registered by the GPIO portion. This
+ * cannot be const since we assign the struct gpio_chip * pointer at runtime.
+ */
+static struct pinctrl_gpio_range nmk_db8540_ranges[] = {
+       DB8540_GPIO_RANGE(0, 0, 18),
+       DB8540_GPIO_RANGE(0, 22, 7),
+       DB8540_GPIO_RANGE(1, 33, 6),
+       DB8540_GPIO_RANGE(2, 64, 4),
+       DB8540_GPIO_RANGE(2, 70, 18),
+       DB8540_GPIO_RANGE(3, 116, 12),
+       DB8540_GPIO_RANGE(4, 128, 32),
+       DB8540_GPIO_RANGE(5, 160, 9),
+       DB8540_GPIO_RANGE(6, 192, 23),
+       DB8540_GPIO_RANGE(6, 219, 5),
+       DB8540_GPIO_RANGE(7, 224, 9),
+       DB8540_GPIO_RANGE(8, 256, 12),
+};
+
+/*
+ * Read the pin group names like this:
+ * u0_a_1    = first groups of pins for uart0 on alt function a
+ * i2c2_b_2  = second group of pins for i2c2 on alt function b
+ *
+ * The groups are arranged as sets per altfunction column, so we can
+ * mux in one group at a time by selecting the same altfunction for them
+ * all. When functions require pins on different altfunctions, you need
+ * to combine several groups.
+ */
+
+/* Altfunction A column */
+static const unsigned u0_a_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7,
+                                       DB8540_PIN_AF2, DB8540_PIN_AD3 };
+static const unsigned u1rxtx_a_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 };
+static const unsigned u1ctsrts_a_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 };
+/* Image processor I2C line, this is driven by image processor firmware */
+static const unsigned ipi2c_a_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 };
+static const unsigned ipi2c_a_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 };
+/* MSP0 can only be on these pins, but TXD and RXD can be flipped */
+static const unsigned msp0txrx_a_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 };
+static const unsigned msp0tfstck_a_1_pins[] = { DB8540_PIN_AC2,
+       DB8540_PIN_AC4 };
+static const unsigned msp0rfsrck_a_1_pins[] = { DB8540_PIN_AH7,
+       DB8540_PIN_AE7 };
+/* Basic pins of the MMC/SD card 0 interface */
+static const unsigned mc0_a_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11,
+       DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10};
+/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
+static const unsigned msp1txrx_a_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 };
+static const unsigned msp1_a_1_pins[] = { DB8540_PIN_AF3, DB8540_PIN_AF5 };
+
+static const unsigned modobsclk_a_1_pins[] = { DB8540_PIN_AF9 };
+static const unsigned clkoutreq_a_1_pins[] = { DB8540_PIN_AE8 };
+/* LCD interface */
+static const unsigned lcdb_a_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
+       DB8540_PIN_M27, DB8540_PIN_N25 };
+static const unsigned lcdvsi0_a_1_pins[] = { DB8540_PIN_AJ24 };
+static const unsigned lcdvsi1_a_1_pins[] = { DB8540_PIN_AE21 };
+static const unsigned lcd_d0_d7_a_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
+       DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
+       DB8540_PIN_P22, DB8540_PIN_P28 };
+/* D8 thru D11 often used as TVOUT lines */
+static const unsigned lcd_d8_d11_a_1_pins[] = { DB8540_PIN_P26, DB8540_PIN_T22,
+       DB8540_PIN_R27, DB8540_PIN_P27 };
+static const unsigned lcd_d12_d23_a_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25,
+       DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21,
+       DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+       DB8540_PIN_AG20, DB8540_PIN_AE23 };
+static const unsigned kp_a_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
+       DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 };
+/* MC2 has 8 data lines and no direction control, so only for (e)MMC */
+static const unsigned mc2_a_1_pins[] = { DB8540_PIN_AC27, DB8540_PIN_AD27,
+       DB8540_PIN_AE28, DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27,
+       DB8540_PIN_AF27, DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25,
+       DB8540_PIN_AG24 };
+static const unsigned ssp1_a_1_pins[] = {  DB8540_PIN_AD25, DB8540_PIN_AH25,
+       DB8540_PIN_AF26, DB8540_PIN_AF23 };
+static const unsigned ssp0_a_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25,
+       DB8540_PIN_AH24, DB8540_PIN_AJ25 };
+static const unsigned i2c0_a_1_pins[] = { DB8540_PIN_AG27, DB8540_PIN_AH23 };
+/*
+ * Image processor GPIO pins are named "ipgpio" and have their own
+ * numberspace
+ */
+static const unsigned ipgpio0_a_1_pins[] = { DB8540_PIN_AE26 };
+static const unsigned ipgpio1_a_1_pins[] = { DB8540_PIN_AE24 };
+/* modem i2s interface */
+static const unsigned modi2s_a_1_pins[] = { DB8540_PIN_AD26, DB8540_PIN_AD28,
+       DB8540_PIN_AC28, DB8540_PIN_AC26 };
+static const unsigned spi2_a_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21,
+       DB8540_PIN_AH19, DB8540_PIN_AE19 };
+static const unsigned u2txrx_a_1_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 };
+static const unsigned u2ctsrts_a_1_pins[] = { DB8540_PIN_AF19,
+       DB8540_PIN_AF18 };
+static const unsigned modsmb_a_1_pins[] = { DB8540_PIN_AF17, DB8540_PIN_AE17 };
+static const unsigned msp2sck_a_1_pins[] = { DB8540_PIN_J3 };
+static const unsigned msp2txdtcktfs_a_1_pins[] = { DB8540_PIN_H1, DB8540_PIN_J2,
+       DB8540_PIN_H2 };
+static const unsigned msp2rxd_a_1_pins[] = { DB8540_PIN_H3 };
+static const unsigned mc4_a_1_pins[] = { DB8540_PIN_H4, DB8540_PIN_G2,
+       DB8540_PIN_G3, DB8540_PIN_G4, DB8540_PIN_F2, DB8540_PIN_C6,
+       DB8540_PIN_B6, DB8540_PIN_B7, DB8540_PIN_A7, DB8540_PIN_D7,
+       DB8540_PIN_D8 };
+static const unsigned mc1_a_1_pins[] = { DB8540_PIN_F3, DB8540_PIN_E2,
+       DB8540_PIN_C7, DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8,
+       DB8540_PIN_C9 };
+/* mc1_a_2_pins exclude MC1_FBCLK */
+static const unsigned mc1_a_2_pins[] = { DB8540_PIN_F3,        DB8540_PIN_C7,
+       DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8,
+       DB8540_PIN_C9 };
+static const unsigned hsir_a_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10,
+       DB8540_PIN_D9 };
+static const unsigned hsit_a_1_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10,
+       DB8540_PIN_E10, DB8540_PIN_B12, DB8540_PIN_D10 };
+static const unsigned hsit_a_2_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10,
+       DB8540_PIN_E10, DB8540_PIN_B12 };
+static const unsigned clkout_a_1_pins[] = { DB8540_PIN_D11, DB8540_PIN_AJ6 };
+static const unsigned clkout_a_2_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 };
+static const unsigned msp4_a_1_pins[] = { DB8540_PIN_B14, DB8540_PIN_E11 };
+static const unsigned usb_a_1_pins[] = { DB8540_PIN_D12, DB8540_PIN_D15,
+       DB8540_PIN_C13, DB8540_PIN_C14, DB8540_PIN_C18, DB8540_PIN_C16,
+       DB8540_PIN_B16, DB8540_PIN_D18, DB8540_PIN_C15, DB8540_PIN_C17,
+       DB8540_PIN_B17, DB8540_PIN_D17 };
+/* Altfunction B colum */
+static const unsigned apetrig_b_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7 };
+static const unsigned modtrig_b_1_pins[] = { DB8540_PIN_AF2, DB8540_PIN_AD3 };
+static const unsigned i2c4_b_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 };
+static const unsigned i2c1_b_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 };
+static const unsigned i2c2_b_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 };
+static const unsigned i2c2_b_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 };
+static const unsigned msp0txrx_b_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 };
+static const unsigned i2c1_b_2_pins[] = { DB8540_PIN_AH7, DB8540_PIN_AE7 };
+static const unsigned stmmod_b_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11,
+       DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
+static const unsigned moduartstmmux_b_1_pins[] = { DB8540_PIN_AG11 };
+static const unsigned msp1txrx_b_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 };
+static const unsigned kp_b_1_pins[] = { DB8540_PIN_AJ24, DB8540_PIN_AE21,
+       DB8540_PIN_M26, DB8540_PIN_M25, DB8540_PIN_M27, DB8540_PIN_N25,
+       DB8540_PIN_M28, DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22,
+       DB8540_PIN_N27, DB8540_PIN_N28, DB8540_PIN_P22, DB8540_PIN_P28,
+       DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27,
+       DB8540_PIN_R26, DB8540_PIN_R25 };
+static const unsigned u2txrx_b_1_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27 };
+static const unsigned sm_b_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
+       DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+       DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22,
+       DB8540_PIN_AJ21, DB8540_PIN_AC27, DB8540_PIN_AD27, DB8540_PIN_AE28,
+       DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27, DB8540_PIN_AF27,
+       DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25, DB8540_PIN_AG24,
+       DB8540_PIN_AD25 };
+static const unsigned smcs0_b_1_pins[] = { DB8540_PIN_AG19 };
+static const unsigned smcs1_b_1_pins[] = { DB8540_PIN_AE26 };
+static const unsigned ipgpio7_b_1_pins[] = { DB8540_PIN_AH25 };
+static const unsigned ipgpio2_b_1_pins[] = { DB8540_PIN_AF26 };
+static const unsigned ipgpio3_b_1_pins[] = { DB8540_PIN_AF23 };
+static const unsigned i2c6_b_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25 };
+static const unsigned i2c5_b_1_pins[] = { DB8540_PIN_AH24, DB8540_PIN_AJ25 };
+static const unsigned u3txrx_b_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21 };
+static const unsigned u3ctsrts_b_1_pins[] = { DB8540_PIN_AH19,
+       DB8540_PIN_AE19 };
+static const unsigned i2c5_b_2_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 };
+static const unsigned i2c4_b_2_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 };
+static const unsigned u4txrx_b_1_pins[] = { DB8540_PIN_AE18, DB8540_PIN_AG17 };
+static const unsigned u4ctsrts_b_1_pins[] = { DB8540_PIN_AF17,
+       DB8540_PIN_AE17 };
+static const unsigned ddrtrig_b_1_pins[] = { DB8540_PIN_J3 };
+static const unsigned msp4_b_1_pins[] = { DB8540_PIN_H3 };
+static const unsigned pwl_b_1_pins[] = { DB8540_PIN_C6 };
+static const unsigned spi1_b_1_pins[] = { DB8540_PIN_E2, DB8540_PIN_C10,
+       DB8540_PIN_C8, DB8540_PIN_C9 };
+static const unsigned mc3_b_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10,
+       DB8540_PIN_D9, DB8540_PIN_B11, DB8540_PIN_B10, DB8540_PIN_E10,
+       DB8540_PIN_B12 };
+static const unsigned pwl_b_2_pins[] = { DB8540_PIN_D10 };
+static const unsigned pwl_b_3_pins[] = { DB8540_PIN_B13 };
+static const unsigned pwl_b_4_pins[] = { DB8540_PIN_C12 };
+static const unsigned u2txrx_b_2_pins[] = { DB8540_PIN_B17, DB8540_PIN_D17 };
+
+/* Altfunction C column */
+static const unsigned ipgpio6_c_1_pins[] = { DB8540_PIN_AG6 };
+static const unsigned ipgpio0_c_1_pins[] = { DB8540_PIN_AD5 };
+static const unsigned ipgpio1_c_1_pins[] = { DB8540_PIN_AF7 };
+static const unsigned ipgpio3_c_1_pins[] = { DB8540_PIN_AE4 };
+static const unsigned ipgpio2_c_1_pins[] = { DB8540_PIN_AD1 };
+static const unsigned u0_c_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AF3,
+       DB8540_PIN_AF5, DB8540_PIN_AG4 };
+static const unsigned smcleale_c_1_pins[] = { DB8540_PIN_AJ24,
+       DB8540_PIN_AE21 };
+static const unsigned ipgpio4_c_1_pins[] = { DB8540_PIN_M26 };
+static const unsigned ipgpio5_c_1_pins[] = { DB8540_PIN_M25 };
+static const unsigned ipgpio6_c_2_pins[] = { DB8540_PIN_M27 };
+static const unsigned ipgpio7_c_1_pins[] = { DB8540_PIN_N25 };
+static const unsigned stmape_c_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
+       DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 };
+static const unsigned u2rxtx_c_1_pins[] = { DB8540_PIN_N28, DB8540_PIN_P22 };
+static const unsigned modobsresout_c_1_pins[] = { DB8540_PIN_P28 };
+static const unsigned ipgpio2_c_2_pins[] = { DB8540_PIN_P26 };
+static const unsigned ipgpio3_c_2_pins[] = { DB8540_PIN_T22 };
+static const unsigned ipgpio4_c_2_pins[] = { DB8540_PIN_R27 };
+static const unsigned ipgpio5_c_2_pins[] = { DB8540_PIN_P27 };
+static const unsigned modaccgpo_c_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25,
+       DB8540_PIN_U22 };
+static const unsigned modobspwrrst_c_1_pins[] = { DB8540_PIN_T27 };
+static const unsigned mc5_c_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
+       DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+       DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22,
+       DB8540_PIN_AJ21};
+static const unsigned smps0_c_1_pins[] = { DB8540_PIN_AG19 };
+static const unsigned moduart1_c_1_pins[] = { DB8540_PIN_T25, DB8540_PIN_T26 };
+static const unsigned mc2rstn_c_1_pins[] = { DB8540_PIN_AE28 };
+static const unsigned i2c5_c_1_pins[] = { DB8540_PIN_AG28, DB8540_PIN_AF28 };
+static const unsigned ipgpio0_c_2_pins[] = { DB8540_PIN_AG25 };
+static const unsigned ipgpio1_c_2_pins[] = { DB8540_PIN_AG24 };
+static const unsigned kp_c_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
+       DB8540_PIN_AF26, DB8540_PIN_AF23 };
+static const unsigned modrf_c_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25,
+       DB8540_PIN_AH24 };
+static const unsigned smps1_c_1_pins[] = { DB8540_PIN_AE26 };
+static const unsigned i2c5_c_2_pins[] = { DB8540_PIN_AH19, DB8540_PIN_AE19 };
+static const unsigned u4ctsrts_c_1_pins[] = { DB8540_PIN_AG18,
+       DB8540_PIN_AH17 };
+static const unsigned u3rxtx_c_1_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 };
+static const unsigned msp4_c_1_pins[] = { DB8540_PIN_J3 };
+static const unsigned mc4rstn_c_1_pins[] = { DB8540_PIN_C6 };
+static const unsigned spi0_c_1_pins[] = { DB8540_PIN_A10, DB8540_PIN_B10,
+       DB8540_PIN_E10, DB8540_PIN_B12 };
+static const unsigned i2c3_c_1_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 };
+
+/* Other alt C1 column */
+static const unsigned spi3_oc1_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5,
+       DB8540_PIN_AE4, DB8540_PIN_AD1 };
+static const unsigned stmape_oc1_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11,
+       DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
+static const unsigned u2_oc1_1_pins[] = { DB8540_PIN_AG11 };
+static const unsigned remap0_oc1_1_pins[] = { DB8540_PIN_AJ24 };
+static const unsigned remap1_oc1_1_pins[] = { DB8540_PIN_AE21 };
+static const unsigned modobsrefclk_oc1_1_pins[] = { DB8540_PIN_M26 };
+static const unsigned modobspwrctrl_oc1_1_pins[] = { DB8540_PIN_M25 };
+static const unsigned modobsclkout_oc1_1_pins[] = { DB8540_PIN_M27 };
+static const unsigned moduart1_oc1_1_pins[] = { DB8540_PIN_N25 };
+static const unsigned modprcmudbg_oc1_1_pins[] = { DB8540_PIN_M28,
+       DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27,
+       DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
+       DB8540_PIN_R26, DB8540_PIN_R25, DB8540_PIN_U22, DB8540_PIN_T27,
+       DB8540_PIN_AH20, DB8540_PIN_AG19, DB8540_PIN_AF22, DB8540_PIN_AJ21,
+       DB8540_PIN_T25};
+static const unsigned modobsresout_oc1_1_pins[] = { DB8540_PIN_N28 };
+static const unsigned modaccgpo_oc1_1_pins[] = { DB8540_PIN_R27, DB8540_PIN_P27,
+       DB8540_PIN_T26 };
+static const unsigned kp_oc1_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
+       DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+       DB8540_PIN_AG20, DB8540_PIN_AE23 };
+static const unsigned modxmip_oc1_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
+       DB8540_PIN_AG23, DB8540_PIN_AE25 };
+static const unsigned i2c6_oc1_1_pins[] = { DB8540_PIN_AE26, DB8540_PIN_AE24 };
+static const unsigned u2txrx_oc1_1_pins[] = { DB8540_PIN_B7, DB8540_PIN_A7 };
+static const unsigned u2ctsrts_oc1_1_pins[] = { DB8540_PIN_D7, DB8540_PIN_D8 };
+
+/* Other alt C2 column */
+static const unsigned sbag_oc2_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11,
+       DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
+static const unsigned hxclk_oc2_1_pins[] = { DB8540_PIN_M25 };
+static const unsigned modaccuart_oc2_1_pins[] = { DB8540_PIN_N25 };
+static const unsigned stmmod_oc2_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
+       DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 };
+static const unsigned moduartstmmux_oc2_1_pins[] = { DB8540_PIN_N28 };
+static const unsigned hxgpio_oc2_1_pins[] = { DB8540_PIN_P22, DB8540_PIN_P28,
+       DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27,
+       DB8540_PIN_R26, DB8540_PIN_R25 };
+static const unsigned sbag_oc2_2_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27,
+       DB8540_PIN_AG22, DB8540_PIN_AF21, DB8540_PIN_AF24, DB8540_PIN_AH22 };
+static const unsigned modobsservice_oc2_1_pins[] = { DB8540_PIN_AJ23 };
+static const unsigned moduart0_oc2_1_pins[] = { DB8540_PIN_AG20,
+       DB8540_PIN_AE23 };
+static const unsigned stmape_oc2_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
+       DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 };
+static const unsigned u2_oc2_1_pins[] = { DB8540_PIN_T26, DB8540_PIN_AH21 };
+static const unsigned modxmip_oc2_1_pins[] = { DB8540_PIN_AE26,
+       DB8540_PIN_AE24 };
+
+/* Other alt C3 column */
+static const unsigned modaccgpo_oc3_1_pins[] = { DB8540_PIN_AG11 };
+static const unsigned tpui_oc3_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
+       DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26,
+       DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
+       DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
+       DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25,
+       DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21,
+       DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+       DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AG19,
+       DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 };
+
+/* Other alt C4 column */
+static const unsigned hwobs_oc4_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
+       DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26,
+       DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
+       DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
+       DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25 };
+static const unsigned moduart1txrx_oc4_1_pins[] = { DB8540_PIN_U22,
+       DB8540_PIN_T27 };
+static const unsigned moduart1rtscts_oc4_1_pins[] = { DB8540_PIN_AG22,
+       DB8540_PIN_AF21 };
+static const unsigned modaccuarttxrx_oc4_1_pins[] = { DB8540_PIN_AF24,
+       DB8540_PIN_AH22 };
+static const unsigned modaccuartrtscts_oc4_1_pins[] = { DB8540_PIN_AJ23,
+       DB8540_PIN_AH21 };
+static const unsigned stmmod_oc4_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
+       DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 };
+static const unsigned moduartstmmux_oc4_1_pins[] = { DB8540_PIN_T26 };
+
+#define DB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins,         \
+                       .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
+
+static const struct nmk_pingroup nmk_db8540_groups[] = {
+       /* Altfunction A column */
+       DB8540_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(modobsclk_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(clkoutreq_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(modi2s_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(spi2_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(u2txrx_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(u2ctsrts_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(modsmb_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(msp2txdtcktfs_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(msp2rxd_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(msp4_a_1, NMK_GPIO_ALT_A),
+       DB8540_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
+       /* Altfunction B column */
+       DB8540_PIN_GROUP(apetrig_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(modtrig_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(moduartstmmux_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(u2txrx_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(i2c6_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(i2c5_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(u3txrx_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(u3ctsrts_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(i2c5_b_2, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(i2c4_b_2, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(u4txrx_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(u4ctsrts_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(msp4_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
+       DB8540_PIN_GROUP(u2txrx_b_2, NMK_GPIO_ALT_B),
+       /* Altfunction C column */
+       DB8540_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modobsresout_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modaccgpo_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modobspwrrst_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(moduart1_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(i2c5_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio0_c_2, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(ipgpio1_c_2, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modrf_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(i2c5_c_2, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(u4ctsrts_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(u3rxtx_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(msp4_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
+
+       /* Other alt C1 column, these are still configured as alt C */
+       DB8540_PIN_GROUP(spi3_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(u2_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modobsrefclk_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modobspwrctrl_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modobsclkout_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(moduart1_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modprcmudbg_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modobsresout_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modaccgpo_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modxmip_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(i2c6_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(u2txrx_oc1_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(u2ctsrts_oc1_1, NMK_GPIO_ALT_C),
+
+       /* Other alt C2 column, these are still configured as alt C */
+       DB8540_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(hxclk_oc2_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modaccuart_oc2_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(stmmod_oc2_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(moduartstmmux_oc2_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(hxgpio_oc2_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(sbag_oc2_2, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modobsservice_oc2_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(moduart0_oc2_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(stmape_oc2_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(u2_oc2_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modxmip_oc2_1, NMK_GPIO_ALT_C),
+
+       /* Other alt C3 column, these are still configured as alt C */
+       DB8540_PIN_GROUP(modaccgpo_oc3_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(tpui_oc3_1, NMK_GPIO_ALT_C),
+
+       /* Other alt C4 column, these are still configured as alt C */
+       DB8540_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(moduart1txrx_oc4_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(moduart1rtscts_oc4_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modaccuarttxrx_oc4_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(modaccuartrtscts_oc4_1, NMK_GPIO_ALT_C),
+       DB8540_PIN_GROUP(stmmod_oc4_1, NMK_GPIO_ALT_C),
+
+};
+
+/* We use this macro to define the groups applicable to a function */
+#define DB8540_FUNC_GROUPS(a, b...)       \
+static const char * const a##_groups[] = { b };
+
+DB8540_FUNC_GROUPS(apetrig, "apetrig_b_1");
+DB8540_FUNC_GROUPS(clkout, "clkoutreq_a_1", "clkout_a_1", "clkout_a_2");
+DB8540_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
+DB8540_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
+DB8540_FUNC_GROUPS(hwobs, "hwobs_oc4_1");
+DB8540_FUNC_GROUPS(hx, "hxclk_oc2_1", "hxgpio_oc2_1");
+DB8540_FUNC_GROUPS(i2c0, "i2c0_a_1");
+DB8540_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
+DB8540_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
+DB8540_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c4_b_1");
+DB8540_FUNC_GROUPS(i2c4, "i2c4_b_2");
+DB8540_FUNC_GROUPS(i2c5, "i2c5_b_1", "i2c5_b_2", "i2c5_c_1", "i2c5_c_2");
+DB8540_FUNC_GROUPS(i2c6, "i2c6_b_1", "i2c6_oc1_1");
+/* The image processor has 8 GPIO pins that can be muxed out */
+DB8540_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio0_c_1", "ipgpio0_c_2",
+               "ipgpio1_a_1", "ipgpio1_c_1", "ipgpio1_c_2",
+               "ipgpio2_b_1", "ipgpio2_c_1", "ipgpio2_c_2",
+               "ipgpio3_b_1", "ipgpio3_c_1", "ipgpio3_c_2",
+               "ipgpio4_c_1", "ipgpio4_c_2",
+               "ipgpio5_c_1", "ipgpio5_c_2",
+               "ipgpio6_c_1", "ipgpio6_c_2",
+               "ipgpio7_b_1", "ipgpio7_c_1");
+DB8540_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
+DB8540_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
+DB8540_FUNC_GROUPS(lcd, "lcd_d0_d7_a_1", "lcd_d12_d23_a_1", "lcd_d8_d11_a_1",
+               "lcdvsi0_a_1", "lcdvsi1_a_1");
+DB8540_FUNC_GROUPS(lcdb, "lcdb_a_1");
+DB8540_FUNC_GROUPS(mc0, "mc0_a_1");
+DB8540_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2");
+DB8540_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
+DB8540_FUNC_GROUPS(mc3, "mc3_b_1");
+DB8540_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
+DB8540_FUNC_GROUPS(mc5, "mc5_c_1");
+DB8540_FUNC_GROUPS(modaccgpo, "modaccgpo_c_1", "modaccgpo_oc1_1",
+               "modaccgpo_oc3_1");
+DB8540_FUNC_GROUPS(modaccuart, "modaccuart_oc2_1", "modaccuarttxrx_oc4_1",
+               "modaccuartrtccts_oc4_1");
+DB8540_FUNC_GROUPS(modi2s, "modi2s_a_1");
+DB8540_FUNC_GROUPS(modobs, "modobsclk_a_1", "modobsclkout_oc1_1",
+               "modobspwrctrl_oc1_1", "modobspwrrst_c_1",
+               "modobsrefclk_oc1_1", "modobsresout_c_1",
+               "modobsresout_oc1_1", "modobsservice_oc2_1");
+DB8540_FUNC_GROUPS(modprcmudbg, "modprcmudbg_oc1_1");
+DB8540_FUNC_GROUPS(modrf, "modrf_c_1");
+DB8540_FUNC_GROUPS(modsmb, "modsmb_a_1");
+DB8540_FUNC_GROUPS(modtrig, "modtrig_b_1");
+DB8540_FUNC_GROUPS(moduart, "moduart1_c_1", "moduart1_oc1_1",
+               "moduart1txrx_oc4_1", "moduart1rtscts_oc4_1", "moduart0_oc2_1");
+DB8540_FUNC_GROUPS(moduartstmmux, "moduartstmmux_b_1", "moduartstmmux_oc2_1",
+               "moduartstmmux_oc4_1");
+DB8540_FUNC_GROUPS(modxmip, "modxmip_oc1_1", "modxmip_oc2_1");
+/*
+ * MSP0 can only be on a certain set of pins, but the TX/RX pins can be
+ * switched around by selecting the altfunction A or B.
+ */
+DB8540_FUNC_GROUPS(msp0, "msp0rfsrck_a_1", "msp0tfstck_a_1", "msp0txrx_a_1",
+               "msp0txrx_b_1");
+DB8540_FUNC_GROUPS(msp1, "msp1_a_1", "msp1txrx_a_1", "msp1txrx_b_1");
+DB8540_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2txdtcktfs_a_1", "msp2rxd_a_1");
+DB8540_FUNC_GROUPS(msp4, "msp4_a_1", "msp4_b_1", "msp4_c_1");
+DB8540_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
+DB8540_FUNC_GROUPS(remap, "remap0_oc1_1", "remap1_oc1_1");
+DB8540_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc2_2");
+/* Select between CS0 on alt B or PS1 on alt C */
+DB8540_FUNC_GROUPS(sm, "sm_b_1", "smcleale_c_1", "smcs0_b_1", "smcs1_b_1",
+               "smps0_c_1", "smps1_c_1");
+DB8540_FUNC_GROUPS(spi0, "spi0_c_1");
+DB8540_FUNC_GROUPS(spi1, "spi1_b_1");
+DB8540_FUNC_GROUPS(spi2, "spi2_a_1");
+DB8540_FUNC_GROUPS(spi3, "spi3_oc1_1");
+DB8540_FUNC_GROUPS(ssp0, "ssp0_a_1");
+DB8540_FUNC_GROUPS(ssp1, "ssp1_a_1");
+DB8540_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_oc1_1", "stmape_oc2_1");
+DB8540_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_oc2_1", "stmmod_oc4_1");
+DB8540_FUNC_GROUPS(tpui, "tpui_oc3_1");
+DB8540_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
+DB8540_FUNC_GROUPS(u1, "u1ctsrts_a_1", "u1rxtx_a_1");
+DB8540_FUNC_GROUPS(u2, "u2_oc1_1", "u2_oc2_1", "u2ctsrts_a_1", "u2ctsrts_oc1_1",
+               "u2rxtx_c_1", "u2txrx_a_1", "u2txrx_b_1", "u2txrx_b_2",
+               "u2txrx_oc1_1");
+DB8540_FUNC_GROUPS(u3, "u3ctsrts_b_1", "u3rxtx_c_1", "u3txrxa_b_1");
+DB8540_FUNC_GROUPS(u4, "u4ctsrts_b_1", "u4ctsrts_c_1", "u4txrx_b_1");
+DB8540_FUNC_GROUPS(usb, "usb_a_1");
+
+
+#define FUNCTION(fname)                                        \
+       {                                               \
+               .name = #fname,                         \
+               .groups = fname##_groups,               \
+               .ngroups = ARRAY_SIZE(fname##_groups),  \
+       }
+
+static const struct nmk_function nmk_db8540_functions[] = {
+       FUNCTION(apetrig),
+       FUNCTION(clkout),
+       FUNCTION(ddrtrig),
+       FUNCTION(hsi),
+       FUNCTION(hwobs),
+       FUNCTION(hx),
+       FUNCTION(i2c0),
+       FUNCTION(i2c1),
+       FUNCTION(i2c2),
+       FUNCTION(i2c3),
+       FUNCTION(i2c4),
+       FUNCTION(i2c5),
+       FUNCTION(i2c6),
+       FUNCTION(ipgpio),
+       FUNCTION(ipi2c),
+       FUNCTION(kp),
+       FUNCTION(lcd),
+       FUNCTION(lcdb),
+       FUNCTION(mc0),
+       FUNCTION(mc1),
+       FUNCTION(mc2),
+       FUNCTION(mc3),
+       FUNCTION(mc4),
+       FUNCTION(mc5),
+       FUNCTION(modaccgpo),
+       FUNCTION(modaccuart),
+       FUNCTION(modi2s),
+       FUNCTION(modobs),
+       FUNCTION(modprcmudbg),
+       FUNCTION(modrf),
+       FUNCTION(modsmb),
+       FUNCTION(modtrig),
+       FUNCTION(moduart),
+       FUNCTION(modxmip),
+       FUNCTION(msp0),
+       FUNCTION(msp1),
+       FUNCTION(msp2),
+       FUNCTION(msp4),
+       FUNCTION(pwl),
+       FUNCTION(remap),
+       FUNCTION(sbag),
+       FUNCTION(sm),
+       FUNCTION(spi0),
+       FUNCTION(spi1),
+       FUNCTION(spi2),
+       FUNCTION(spi3),
+       FUNCTION(ssp0),
+       FUNCTION(ssp1),
+       FUNCTION(stmape),
+       FUNCTION(stmmod),
+       FUNCTION(tpui),
+       FUNCTION(u0),
+       FUNCTION(u1),
+       FUNCTION(u2),
+       FUNCTION(u3),
+       FUNCTION(u4),
+       FUNCTION(usb)
+};
+
+static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
+       .gpio_ranges = nmk_db8540_ranges,
+       .gpio_num_ranges = ARRAY_SIZE(nmk_db8540_ranges),
+       .pins = nmk_db8540_pins,
+       .npins = ARRAY_SIZE(nmk_db8540_pins),
+       .functions = nmk_db8540_functions,
+       .nfunctions = ARRAY_SIZE(nmk_db8540_functions),
+       .groups = nmk_db8540_groups,
+       .ngroups = ARRAY_SIZE(nmk_db8540_groups),
+};
+
+void __devinit
+nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
+{
+       *soc = &nmk_db8540_soc;
+}

diff --git a/drivers/pinctrl/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/pinctrl-nomadik-stn8815.c
new file mode 100644 (file)
index 0000000..7d432c3
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik-stn8815.c
@@ -0,0 +1,357 @@
+#include <linux/kernel.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-nomadik.h"
+
+/* All the pins that can be used for GPIO and some other functions */
+#define _GPIO(offset)          (offset)
+
+#define STN8815_PIN_B4         _GPIO(0)
+#define STN8815_PIN_D5         _GPIO(1)
+#define STN8815_PIN_C5         _GPIO(2)
+#define STN8815_PIN_A4         _GPIO(3)
+#define STN8815_PIN_B5         _GPIO(4)
+#define STN8815_PIN_D6         _GPIO(5)
+#define STN8815_PIN_C6         _GPIO(6)
+#define STN8815_PIN_B6         _GPIO(7)
+#define STN8815_PIN_B10                _GPIO(8)
+#define STN8815_PIN_A10                _GPIO(9)
+#define STN8815_PIN_C11                _GPIO(10)
+#define STN8815_PIN_B11                _GPIO(11)
+#define STN8815_PIN_A11                _GPIO(12)
+#define STN8815_PIN_C12                _GPIO(13)
+#define STN8815_PIN_B12                _GPIO(14)
+#define STN8815_PIN_A12                _GPIO(15)
+#define STN8815_PIN_C13                _GPIO(16)
+#define STN8815_PIN_B13                _GPIO(17)
+#define STN8815_PIN_A13                _GPIO(18)
+#define STN8815_PIN_D13                _GPIO(19)
+#define STN8815_PIN_C14                _GPIO(20)
+#define STN8815_PIN_B14                _GPIO(21)
+#define STN8815_PIN_A14                _GPIO(22)
+#define STN8815_PIN_D15                _GPIO(23)
+#define STN8815_PIN_C15                _GPIO(24)
+#define STN8815_PIN_B15                _GPIO(25)
+#define STN8815_PIN_A15                _GPIO(26)
+#define STN8815_PIN_C16                _GPIO(27)
+#define STN8815_PIN_B16                _GPIO(28)
+#define STN8815_PIN_A16                _GPIO(29)
+#define STN8815_PIN_D17                _GPIO(30)
+#define STN8815_PIN_C17                _GPIO(31)
+#define STN8815_PIN_AB6                _GPIO(32)
+#define STN8815_PIN_AA6                _GPIO(33)
+#define STN8815_PIN_Y6         _GPIO(34)
+#define STN8815_PIN_Y5         _GPIO(35)
+#define STN8815_PIN_AA5                _GPIO(36)
+#define STN8815_PIN_AB5                _GPIO(37)
+#define STN8815_PIN_AB4                _GPIO(38)
+#define STN8815_PIN_Y4         _GPIO(39)
+#define STN8815_PIN_R1         _GPIO(40)
+#define STN8815_PIN_R2         _GPIO(41)
+#define STN8815_PIN_R3         _GPIO(42)
+#define STN8815_PIN_P1         _GPIO(43)
+#define STN8815_PIN_P2         _GPIO(44)
+#define STN8815_PIN_P3         _GPIO(45)
+#define STN8815_PIN_N1         _GPIO(46)
+#define STN8815_PIN_N2         _GPIO(47)
+#define STN8815_PIN_N3         _GPIO(48)
+#define STN8815_PIN_M1         _GPIO(49)
+#define STN8815_PIN_M3         _GPIO(50)
+#define STN8815_PIN_M2         _GPIO(51)
+#define STN8815_PIN_L1         _GPIO(52)
+#define STN8815_PIN_L4         _GPIO(53)
+#define STN8815_PIN_L3         _GPIO(54)
+#define STN8815_PIN_L2         _GPIO(55)
+#define STN8815_PIN_F3         _GPIO(56)
+#define STN8815_PIN_F2         _GPIO(57)
+#define STN8815_PIN_E1         _GPIO(58)
+#define STN8815_PIN_E3         _GPIO(59)
+#define STN8815_PIN_E2         _GPIO(60)
+#define STN8815_PIN_E4         _GPIO(61)
+#define STN8815_PIN_D3         _GPIO(62)
+#define STN8815_PIN_D2         _GPIO(63)
+#define STN8815_PIN_F21                _GPIO(64)
+#define STN8815_PIN_F20                _GPIO(65)
+#define STN8815_PIN_E22                _GPIO(66)
+#define STN8815_PIN_D22                _GPIO(67)
+#define STN8815_PIN_E21                _GPIO(68)
+#define STN8815_PIN_E20                _GPIO(69)
+#define STN8815_PIN_C22                _GPIO(70)
+#define STN8815_PIN_D21                _GPIO(71)
+#define STN8815_PIN_D20                _GPIO(72)
+#define STN8815_PIN_C21                _GPIO(73)
+#define STN8815_PIN_C20                _GPIO(74)
+#define STN8815_PIN_C19                _GPIO(75)
+#define STN8815_PIN_B20                _GPIO(76)
+#define STN8815_PIN_B8         _GPIO(77)
+#define STN8815_PIN_A8         _GPIO(78)
+#define STN8815_PIN_C9         _GPIO(79)
+#define STN8815_PIN_B9         _GPIO(80)
+#define STN8815_PIN_A9         _GPIO(81)
+#define STN8815_PIN_C10                _GPIO(82)
+#define STN8815_PIN_K1         _GPIO(83)
+#define STN8815_PIN_K3         _GPIO(84)
+#define STN8815_PIN_K2         _GPIO(85)
+#define STN8815_PIN_J1         _GPIO(86)
+#define STN8815_PIN_J3         _GPIO(87)
+#define STN8815_PIN_J2         _GPIO(88)
+#define STN8815_PIN_H1         _GPIO(89)
+#define STN8815_PIN_H3         _GPIO(90)
+#define STN8815_PIN_H2         _GPIO(91)
+#define STN8815_PIN_G1         _GPIO(92)
+#define STN8815_PIN_G3         _GPIO(93)
+#define STN8815_PIN_G2         _GPIO(94)
+#define STN8815_PIN_F1         _GPIO(95)
+#define STN8815_PIN_T20                _GPIO(96)
+#define STN8815_PIN_R21                _GPIO(97)
+#define STN8815_PIN_R20                _GPIO(98)
+#define STN8815_PIN_U22                _GPIO(99)
+#define STN8815_PIN_N21                _GPIO(100)
+#define STN8815_PIN_N20                _GPIO(101)
+#define STN8815_PIN_P22                _GPIO(102)
+#define STN8815_PIN_N22                _GPIO(103)
+#define STN8815_PIN_V22                _GPIO(104)
+#define STN8815_PIN_V21                _GPIO(105)
+#define STN8815_PIN_K22                _GPIO(106)
+#define STN8815_PIN_K21                _GPIO(107)
+#define STN8815_PIN_H20                _GPIO(108)
+#define STN8815_PIN_G20                _GPIO(109)
+#define STN8815_PIN_L21                _GPIO(110)
+#define STN8815_PIN_H21                _GPIO(111)
+#define STN8815_PIN_J21                _GPIO(112)
+#define STN8815_PIN_H22                _GPIO(113)
+#define STN8815_PIN_K20                _GPIO(114)
+#define STN8815_PIN_L22                _GPIO(115)
+#define STN8815_PIN_G21                _GPIO(116)
+#define STN8815_PIN_J20                _GPIO(117)
+#define STN8815_PIN_G22                _GPIO(118)
+#define STN8815_PIN_U19                _GPIO(119)
+#define STN8815_PIN_G19                _GPIO(120)
+#define STN8815_PIN_M22                _GPIO(121)
+#define STN8815_PIN_M19                _GPIO(122)
+#define STN8815_PIN_J22                _GPIO(123)
+/* GPIOs 124-127 not routed to pins */
+
+/*
+ * The names of the pins are denoted by GPIO number and ball name, even
+ * though they can be used for other things than GPIO, this is the first
+ * column in the table of the data sheet and often used on schematics and
+ * such.
+ */
+static const struct pinctrl_pin_desc nmk_stn8815_pins[] = {
+       PINCTRL_PIN(STN8815_PIN_B4, "GPIO0_B4"),
+       PINCTRL_PIN(STN8815_PIN_D5, "GPIO1_D5"),
+       PINCTRL_PIN(STN8815_PIN_C5, "GPIO2_C5"),
+       PINCTRL_PIN(STN8815_PIN_A4, "GPIO3_A4"),
+       PINCTRL_PIN(STN8815_PIN_B5, "GPIO4_B5"),
+       PINCTRL_PIN(STN8815_PIN_D6, "GPIO5_D6"),
+       PINCTRL_PIN(STN8815_PIN_C6, "GPIO6_C6"),
+       PINCTRL_PIN(STN8815_PIN_B6, "GPIO7_B6"),
+       PINCTRL_PIN(STN8815_PIN_B10, "GPIO8_B10"),
+       PINCTRL_PIN(STN8815_PIN_A10, "GPIO9_A10"),
+       PINCTRL_PIN(STN8815_PIN_C11, "GPIO10_C11"),
+       PINCTRL_PIN(STN8815_PIN_B11, "GPIO11_B11"),
+       PINCTRL_PIN(STN8815_PIN_A11, "GPIO12_A11"),
+       PINCTRL_PIN(STN8815_PIN_C12, "GPIO13_C12"),
+       PINCTRL_PIN(STN8815_PIN_B12, "GPIO14_B12"),
+       PINCTRL_PIN(STN8815_PIN_A12, "GPIO15_A12"),
+       PINCTRL_PIN(STN8815_PIN_C13, "GPIO16_C13"),
+       PINCTRL_PIN(STN8815_PIN_B13, "GPIO17_B13"),
+       PINCTRL_PIN(STN8815_PIN_A13, "GPIO18_A13"),
+       PINCTRL_PIN(STN8815_PIN_D13, "GPIO19_D13"),
+       PINCTRL_PIN(STN8815_PIN_C14, "GPIO20_C14"),
+       PINCTRL_PIN(STN8815_PIN_B14, "GPIO21_B14"),
+       PINCTRL_PIN(STN8815_PIN_A14, "GPIO22_A14"),
+       PINCTRL_PIN(STN8815_PIN_D15, "GPIO23_D15"),
+       PINCTRL_PIN(STN8815_PIN_C15, "GPIO24_C15"),
+       PINCTRL_PIN(STN8815_PIN_B15, "GPIO25_B15"),
+       PINCTRL_PIN(STN8815_PIN_A15, "GPIO26_A15"),
+       PINCTRL_PIN(STN8815_PIN_C16, "GPIO27_C16"),
+       PINCTRL_PIN(STN8815_PIN_B16, "GPIO28_B16"),
+       PINCTRL_PIN(STN8815_PIN_A16, "GPIO29_A16"),
+       PINCTRL_PIN(STN8815_PIN_D17, "GPIO30_D17"),
+       PINCTRL_PIN(STN8815_PIN_C17, "GPIO31_C17"),
+       PINCTRL_PIN(STN8815_PIN_AB6, "GPIO32_AB6"),
+       PINCTRL_PIN(STN8815_PIN_AA6, "GPIO33_AA6"),
+       PINCTRL_PIN(STN8815_PIN_Y6, "GPIO34_Y6"),
+       PINCTRL_PIN(STN8815_PIN_Y5, "GPIO35_Y5"),
+       PINCTRL_PIN(STN8815_PIN_AA5, "GPIO36_AA5"),
+       PINCTRL_PIN(STN8815_PIN_AB5, "GPIO37_AB5"),
+       PINCTRL_PIN(STN8815_PIN_AB4, "GPIO38_AB4"),
+       PINCTRL_PIN(STN8815_PIN_Y4, "GPIO39_Y4"),
+       PINCTRL_PIN(STN8815_PIN_R1, "GPIO40_R1"),
+       PINCTRL_PIN(STN8815_PIN_R2, "GPIO41_R2"),
+       PINCTRL_PIN(STN8815_PIN_R3, "GPIO42_R3"),
+       PINCTRL_PIN(STN8815_PIN_P1, "GPIO43_P1"),
+       PINCTRL_PIN(STN8815_PIN_P2, "GPIO44_P2"),
+       PINCTRL_PIN(STN8815_PIN_P3, "GPIO45_P3"),
+       PINCTRL_PIN(STN8815_PIN_N1, "GPIO46_N1"),
+       PINCTRL_PIN(STN8815_PIN_N2, "GPIO47_N2"),
+       PINCTRL_PIN(STN8815_PIN_N3, "GPIO48_N3"),
+       PINCTRL_PIN(STN8815_PIN_M1, "GPIO49_M1"),
+       PINCTRL_PIN(STN8815_PIN_M3, "GPIO50_M3"),
+       PINCTRL_PIN(STN8815_PIN_M2, "GPIO51_M2"),
+       PINCTRL_PIN(STN8815_PIN_L1, "GPIO52_L1"),
+       PINCTRL_PIN(STN8815_PIN_L4, "GPIO53_L4"),
+       PINCTRL_PIN(STN8815_PIN_L3, "GPIO54_L3"),
+       PINCTRL_PIN(STN8815_PIN_L2, "GPIO55_L2"),
+       PINCTRL_PIN(STN8815_PIN_F3, "GPIO56_F3"),
+       PINCTRL_PIN(STN8815_PIN_F2, "GPIO57_F2"),
+       PINCTRL_PIN(STN8815_PIN_E1, "GPIO58_E1"),
+       PINCTRL_PIN(STN8815_PIN_E3, "GPIO59_E3"),
+       PINCTRL_PIN(STN8815_PIN_E2, "GPIO60_E2"),
+       PINCTRL_PIN(STN8815_PIN_E4, "GPIO61_E4"),
+       PINCTRL_PIN(STN8815_PIN_D3, "GPIO62_D3"),
+       PINCTRL_PIN(STN8815_PIN_D2, "GPIO63_D2"),
+       PINCTRL_PIN(STN8815_PIN_F21, "GPIO64_F21"),
+       PINCTRL_PIN(STN8815_PIN_F20, "GPIO65_F20"),
+       PINCTRL_PIN(STN8815_PIN_E22, "GPIO66_E22"),
+       PINCTRL_PIN(STN8815_PIN_D22, "GPIO67_D22"),
+       PINCTRL_PIN(STN8815_PIN_E21, "GPIO68_E21"),
+       PINCTRL_PIN(STN8815_PIN_E20, "GPIO69_E20"),
+       PINCTRL_PIN(STN8815_PIN_C22, "GPIO70_C22"),
+       PINCTRL_PIN(STN8815_PIN_D21, "GPIO71_D21"),
+       PINCTRL_PIN(STN8815_PIN_D20, "GPIO72_D20"),
+       PINCTRL_PIN(STN8815_PIN_C21, "GPIO73_C21"),
+       PINCTRL_PIN(STN8815_PIN_C20, "GPIO74_C20"),
+       PINCTRL_PIN(STN8815_PIN_C19, "GPIO75_C19"),
+       PINCTRL_PIN(STN8815_PIN_B20, "GPIO76_B20"),
+       PINCTRL_PIN(STN8815_PIN_B8, "GPIO77_B8"),
+       PINCTRL_PIN(STN8815_PIN_A8, "GPIO78_A8"),
+       PINCTRL_PIN(STN8815_PIN_C9, "GPIO79_C9"),
+       PINCTRL_PIN(STN8815_PIN_B9, "GPIO80_B9"),
+       PINCTRL_PIN(STN8815_PIN_A9, "GPIO81_A9"),
+       PINCTRL_PIN(STN8815_PIN_C10, "GPIO82_C10"),
+       PINCTRL_PIN(STN8815_PIN_K1, "GPIO83_K1"),
+       PINCTRL_PIN(STN8815_PIN_K3, "GPIO84_K3"),
+       PINCTRL_PIN(STN8815_PIN_K2, "GPIO85_K2"),
+       PINCTRL_PIN(STN8815_PIN_J1, "GPIO86_J1"),
+       PINCTRL_PIN(STN8815_PIN_J3, "GPIO87_J3"),
+       PINCTRL_PIN(STN8815_PIN_J2, "GPIO88_J2"),
+       PINCTRL_PIN(STN8815_PIN_H1, "GPIO89_H1"),
+       PINCTRL_PIN(STN8815_PIN_H3, "GPIO90_H3"),
+       PINCTRL_PIN(STN8815_PIN_H2, "GPIO91_H2"),
+       PINCTRL_PIN(STN8815_PIN_G1, "GPIO92_G1"),
+       PINCTRL_PIN(STN8815_PIN_G3, "GPIO93_G3"),
+       PINCTRL_PIN(STN8815_PIN_G2, "GPIO94_G2"),
+       PINCTRL_PIN(STN8815_PIN_F1, "GPIO95_F1"),
+       PINCTRL_PIN(STN8815_PIN_T20, "GPIO96_T20"),
+       PINCTRL_PIN(STN8815_PIN_R21, "GPIO97_R21"),
+       PINCTRL_PIN(STN8815_PIN_R20, "GPIO98_R20"),
+       PINCTRL_PIN(STN8815_PIN_U22, "GPIO99_U22"),
+       PINCTRL_PIN(STN8815_PIN_N21, "GPIO100_N21"),
+       PINCTRL_PIN(STN8815_PIN_N20, "GPIO101_N20"),
+       PINCTRL_PIN(STN8815_PIN_P22, "GPIO102_P22"),
+       PINCTRL_PIN(STN8815_PIN_N22, "GPIO103_N22"),
+       PINCTRL_PIN(STN8815_PIN_V22, "GPIO104_V22"),
+       PINCTRL_PIN(STN8815_PIN_V21, "GPIO105_V21"),
+       PINCTRL_PIN(STN8815_PIN_K22, "GPIO106_K22"),
+       PINCTRL_PIN(STN8815_PIN_K21, "GPIO107_K21"),
+       PINCTRL_PIN(STN8815_PIN_H20, "GPIO108_H20"),
+       PINCTRL_PIN(STN8815_PIN_G20, "GPIO109_G20"),
+       PINCTRL_PIN(STN8815_PIN_L21, "GPIO110_L21"),
+       PINCTRL_PIN(STN8815_PIN_H21, "GPIO111_H21"),
+       PINCTRL_PIN(STN8815_PIN_J21, "GPIO112_J21"),
+       PINCTRL_PIN(STN8815_PIN_H22, "GPIO113_H22"),
+       PINCTRL_PIN(STN8815_PIN_K20, "GPIO114_K20"),
+       PINCTRL_PIN(STN8815_PIN_L22, "GPIO115_L22"),
+       PINCTRL_PIN(STN8815_PIN_G21, "GPIO116_G21"),
+       PINCTRL_PIN(STN8815_PIN_J20, "GPIO117_J20"),
+       PINCTRL_PIN(STN8815_PIN_G22, "GPIO118_G22"),
+       PINCTRL_PIN(STN8815_PIN_U19, "GPIO119_U19"),
+       PINCTRL_PIN(STN8815_PIN_G19, "GPIO120_G19"),
+       PINCTRL_PIN(STN8815_PIN_M22, "GPIO121_M22"),
+       PINCTRL_PIN(STN8815_PIN_M19, "GPIO122_M19"),
+       PINCTRL_PIN(STN8815_PIN_J22, "GPIO123_J22"),
+};
+
+#define STN8815_GPIO_RANGE(a, b, c) { .name = "STN8815", .id = a, .base = b, \
+                       .pin_base = b, .npins = c }
+
+/*
+ * This matches the 32-pin gpio chips registered by the GPIO portion. This
+ * cannot be const since we assign the struct gpio_chip * pointer at runtime.
+ */
+static struct pinctrl_gpio_range nmk_stn8815_ranges[] = {
+       STN8815_GPIO_RANGE(0, 0, 32),
+       STN8815_GPIO_RANGE(1, 32, 32),
+       STN8815_GPIO_RANGE(2, 64, 32),
+       STN8815_GPIO_RANGE(3, 96, 28),
+};
+
+/*
+ * Read the pin group names like this:
+ * u0_a_1    = first groups of pins for uart0 on alt function a
+ * i2c2_b_2  = second group of pins for i2c2 on alt function b
+ */
+
+/* Altfunction A */
+static const unsigned u0_a_1_pins[] = { STN8815_PIN_B4, STN8815_PIN_D5,
+       STN8815_PIN_C5, STN8815_PIN_A4, STN8815_PIN_B5, STN8815_PIN_D6,
+       STN8815_PIN_C6, STN8815_PIN_B6 };
+static const unsigned mmcsd_a_1_pins[] = { STN8815_PIN_B10, STN8815_PIN_A10,
+       STN8815_PIN_C11, STN8815_PIN_B11, STN8815_PIN_A11, STN8815_PIN_C12,
+       STN8815_PIN_B12, STN8815_PIN_A12, STN8815_PIN_C13, STN8815_PIN_C15 };
+static const unsigned u1_a_1_pins[] = { STN8815_PIN_M2, STN8815_PIN_L1,
+                                       STN8815_PIN_F3, STN8815_PIN_F2 };
+static const unsigned i2c1_a_1_pins[] = { STN8815_PIN_L4, STN8815_PIN_L3 };
+static const unsigned i2c0_a_1_pins[] = { STN8815_PIN_D3, STN8815_PIN_D2 };
+/* Altfunction B */
+static const unsigned u1_b_1_pins[] = { STN8815_PIN_B16, STN8815_PIN_A16 };
+static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 };
+
+#define STN8815_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins,         \
+                       .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
+
+static const struct nmk_pingroup nmk_stn8815_groups[] = {
+       STN8815_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
+       STN8815_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A),
+       STN8815_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A),
+       STN8815_PIN_GROUP(i2c1_a_1, NMK_GPIO_ALT_A),
+       STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
+       STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
+       STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
+};
+
+/* We use this macro to define the groups applicable to a function */
+#define STN8815_FUNC_GROUPS(a, b...)      \
+static const char * const a##_groups[] = { b };
+
+STN8815_FUNC_GROUPS(u0, "u0_a_1");
+STN8815_FUNC_GROUPS(mmcsd, "mmcsd_a_1");
+STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1");
+STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1");
+STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1");
+STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1");
+
+#define FUNCTION(fname)                                        \
+       {                                               \
+               .name = #fname,                         \
+               .groups = fname##_groups,               \
+               .ngroups = ARRAY_SIZE(fname##_groups),  \
+       }
+
+static const struct nmk_function nmk_stn8815_functions[] = {
+       FUNCTION(u0),
+       FUNCTION(mmcsd),
+       FUNCTION(u1),
+       FUNCTION(i2c1),
+       FUNCTION(i2c0),
+       FUNCTION(i2cusb),
+};
+
+static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {
+       .gpio_ranges = nmk_stn8815_ranges,
+       .gpio_num_ranges = ARRAY_SIZE(nmk_stn8815_ranges),
+       .pins = nmk_stn8815_pins,
+       .npins = ARRAY_SIZE(nmk_stn8815_pins),
+       .functions = nmk_stn8815_functions,
+       .nfunctions = ARRAY_SIZE(nmk_stn8815_functions),
+       .groups = nmk_stn8815_groups,
+       .ngroups = ARRAY_SIZE(nmk_stn8815_groups),
+};
+
+void __devinit
+nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
+{
+       *soc = &nmk_stn8815_soc;
+}

diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index ec6ac501b23a077559f303adc7fb1e07bf68698c..d12df0227561d8f3de347dc57c4f9f171938c32a 100644 (file)
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -1292,7 +1292,7 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
                                                NOMADIK_GPIO_TO_IRQ(pdata->first_gpio),
                                                0, &nmk_gpio_irq_simple_ops, nmk_chip);
        if (!nmk_chip->domain) {
-               pr_err("%s: Failed to create irqdomain\n", np->full_name);
+               dev_err(&dev->dev, "failed to create irqdomain\n");
                ret = -ENOSYS;
                goto out;
        }
@@ -1720,8 +1720,12 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
                        of_match_device(nmk_pinctrl_match, &pdev->dev)->data;
 
        /* Poke in other ASIC variants here */
+       if (version == PINCTRL_NMK_STN8815)
+               nmk_pinctrl_stn8815_init(&npct->soc);
        if (version == PINCTRL_NMK_DB8500)
                nmk_pinctrl_db8500_init(&npct->soc);
+       if (version == PINCTRL_NMK_DB8540)
+               nmk_pinctrl_db8540_init(&npct->soc);
 
        /*
         * We need all the GPIO drivers to probe FIRST, or we will not be able
@@ -1772,6 +1776,7 @@ static struct platform_driver nmk_gpio_driver = {
 static const struct platform_device_id nmk_pinctrl_id[] = {
        { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
        { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
+       { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
 };
 
 static struct platform_driver nmk_pinctrl_driver = {

diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
index bc91aed7185db0bb46d731523819d6fa0dcbf8e6..5c99f1c62dfd1a1524f3d833b37d36c83c96a3c1 100644 (file)
--- a/drivers/pinctrl/pinctrl-nomadik.h
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -6,6 +6,7 @@
 /* Package definitions */
 #define PINCTRL_NMK_STN8815    0
 #define PINCTRL_NMK_DB8500     1
+#define PINCTRL_NMK_DB8540     2
 
 /**
  * struct nmk_function - Nomadik pinctrl mux function
@@ -61,6 +62,19 @@ struct nmk_pinctrl_soc_data {
        unsigned ngroups;
 };
 
+#ifdef CONFIG_PINCTRL_STN8815
+
+void nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc);
+
+#else
+
+static inline void
+nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
+{
+}
+
+#endif
+
 #ifdef CONFIG_PINCTRL_DB8500
 
 void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
@@ -74,4 +88,17 @@ nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
 
 #endif
 
+#ifdef CONFIG_PINCTRL_DB8540
+
+void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc);
+
+#else
+
+static inline void
+nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
+{
+}
+
+#endif
+
 #endif /* PINCTRL_PINCTRL_NOMADIK_H */

diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h
index 6dd96fb45482b00b0ede76c92f83fc6bd76f0f2f..d2816454c2633fb6b68bc576dc053eea27fd0920 100644 (file)
--- a/include/linux/pinctrl/consumer.h
+++ b/include/linux/pinctrl/consumer.h
@@ -20,6 +20,7 @@
 /* This struct is private to the core and should be regarded as a cookie */
 struct pinctrl;
 struct pinctrl_state;
+struct device;
 
 #ifdef CONFIG_PINCTRL
 
@@ -139,7 +140,7 @@ static inline struct pinctrl * __must_check devm_pinctrl_get_select(
        s = pinctrl_lookup_state(p, name);
        if (IS_ERR(s)) {
                devm_pinctrl_put(p);
-               return ERR_PTR(PTR_ERR(s));
+               return ERR_CAST(s);
        }
 
        ret = pinctrl_select_state(p, s);