ARM: SAMSUNG: Add adc registers for S3C2443/S3C2416

The adc blocks of the S3C2443 and S3C2416 define some
additional registers and bits.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h
index 035e8c38d69cc31cce19c06e7ca1205ecd5ba674..70612100120fb0b0694dbd872f983d9bad55d492 100644 (file)
--- a/arch/arm/plat-samsung/include/plat/regs-adc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
@@ -20,6 +20,7 @@
 #define S3C2410_ADCDAT0           S3C2410_ADCREG(0x0C)
 #define S3C2410_ADCDAT1           S3C2410_ADCREG(0x10)
 #define S3C64XX_ADCUPDN                S3C2410_ADCREG(0x14)
+#define S3C2443_ADCMUX         S3C2410_ADCREG(0x18)
 #define S3C64XX_ADCCLRINT      S3C2410_ADCREG(0x18)
 #define S5P_ADCMUX             S3C2410_ADCREG(0x1C)
 #define S3C64XX_ADCCLRINTPNDNUP        S3C2410_ADCREG(0x20)
@@ -33,6 +34,7 @@
 #define S3C2410_ADCCON_PRSCVLMASK      (0xFF<<6)
 #define S3C2410_ADCCON_SELMUX(x)       (((x)&0x7)<<3)
 #define S3C2410_ADCCON_MUXMASK         (0x7<<3)
+#define S3C2416_ADCCON_RESSEL          (1 << 3)
 #define S3C2410_ADCCON_STDBM           (1<<2)
 #define S3C2410_ADCCON_READ_START      (1<<1)
 #define S3C2410_ADCCON_ENABLE_START    (1<<0)
@@ -40,6 +42,7 @@
 
 
 /* ADCTSC Register Bits */
+#define S3C2443_ADCTSC_UD_SEN          (1 << 8)
 #define S3C2410_ADCTSC_YM_SEN          (1<<7)
 #define S3C2410_ADCTSC_YP_SEN          (1<<6)
 #define S3C2410_ADCTSC_XM_SEN          (1<<5)