ENGR00240987: ARM: imx6q: initialize clocks for IPU

This is a fast-forward porting from 3.5.7 kernel.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 8e795dea02ece013f4bb0dc9caa1bda63bc5ffc1..c05b3952376697b4689c0604845a10d9bea242df 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -476,6 +476,26 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                clk_prepare_enable(clk[usbphy2_gate]);
        }
 
+       /* ipu clock initialization */
+       clk_set_parent(clk[ldb_di0_sel], clk[pll2_pfd0_352m]);
+       clk_set_parent(clk[ldb_di1_sel], clk[pll2_pfd0_352m]);
+       clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
+       clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
+       clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
+       clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
+       clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
+       clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
+       clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
+       clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
+       if (cpu_is_imx6dl()) {
+               clk_set_rate(clk[pll3_pfd1_540m], 540000000);
+               clk_set_parent(clk[ipu1_sel], clk[pll3_pfd1_540m]);
+               clk_set_parent(clk[axi_sel], clk[pll3_pfd1_540m]);
+       } else if (cpu_is_imx6q()) {
+               clk_set_parent(clk[ipu1_sel], clk[mmdc_ch0_axi]);
+               clk_set_parent(clk[ipu2_sel], clk[mmdc_ch0_axi]);
+       }
+
        /*
         * Let's initially set up CLKO with OSC24M, since this configuration
         * is widely used by imx6q board designs to clock audio codec.