ARM: BCM5301X: Add DT entry for SPI controller and NOR flash

Controller is present on every BCM4708* board but only few devices have
serial flash attached so mark it as disabled by default.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
index c973f768dd14ec8914b41081ea3f9cf47df8d24e..1c7e53d60aa40ee8029594d4be166c054a1e770a 100644 (file)
--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
@@ -59,3 +59,7 @@
 &uart0 {
        status = "okay";
 };
+
+&spi_nor {
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
index 4d610ff40e1b20ae4cd6c966467a77509554a0a8..8b0c440b2e71985426ff75694e9659d09c5068f8 100644 (file)
--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
@@ -122,3 +122,7 @@
 &uart0 {
        status = "okay";
 };
+
+&spi_nor {
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 9c06d91e0c8aede9dd18af0441507a282a7a304e..7d4d29bf0ed35376b55a301a7fe93f7f04de8877 100644 (file)
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -225,6 +225,20 @@
                        #address-cells = <1>;
                        #size-cells = <1>;
                };
+
+               spi@29000 {
+                       reg = <0x00029000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       spi_nor: spi-nor@0 {
+                               compatible = "jedec,spi-nor";
+                               reg = <0>;
+                               spi-max-frequency = <20000000>;
+                               linux,part-probe = "ofpart", "bcm47xxpart";
+                               status = "disabled";
+                       };
+               };
        };
 
        lcpll0: lcpll0@1800c100 {