fixup! ARM: LPAE: MMU setup for the 3-level page table format

Fix non-LPAE boot regression.

It was introduced by  407f8b4cb07cbc5c1c7cc386f231224e2524ccea
ARM: LPAE: MMU setup for the 3-level page table format

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 0bdafc4351bf1b1b0739a16a41d2277e5f3c4278..1b6aa00131a6f2b684ef31d14b33cb8e7210dabe 100644 (file)
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -206,7 +206,7 @@ __create_page_tables:
 1:     orr     r3, r7, r5, lsl #SECTION_SHIFT  @ flags + kernel base
        str     r3, [r4, r5, lsl #PMD_ORDER]    @ identity mapping
        cmp     r5, r6
-       addlo   r5, r5, #SECTION_SHIFT >> 20    @ next section
+       addlo   r5, r5, #1                      @ next section
        blo     1b
 
        /*