pll3 and pll7 have opposite power down bit definition comparing
with other plls.
so reverse the bit when setting these two plls
Signed-off-by: Tony Lin <tony.lin@freescale.com>
reg &= ~ANADIG_PLL_ENABLE;
reg |= ANADIG_PLL_BYPASS;
reg |= ANADIG_PLL_POWER_DOWN;
- if (clk == &pll3_usb_otg_main_clk)
+
+ /* The 480MHz PLLs, pll3 & pll7, have the opposite
+ * definition for power bit.
+ */
+ if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
reg &= ~ANADIG_PLL_POWER_DOWN;
__raw_writel(reg, pllbase);
}