MLK-9678 arm: imx6: switch to analog bypass before entering DSM

this patch implements the workaround for ERR005852:

ERR005852 Analog: Transition from Deep Sleep Mode to LDO Bypass
Mode may cause the slow response of the VDDARM_CAP output.

    Normally, the VDDARM_CAP supply takes only approximately 40 us
    to raise to the correct voltage when exiting from Deep Sleep(DSM)
    mode, if the LDO is enabled. If the LDO bypass mode is selected,
    the VDDARM_CAP supply voltage will drop to approximately 0V when
    entering and when exiting from DSM,even though the VDDARM_IN
    supply is already stable, the VDDARM_CAP supply will take about
    2 ms to rise to the correct voltage.

software workaround:

if internal LDO bypass, switch to analog bypass mode(0x1E), prior
to entering DSM, and then, revert to the normal bypass mode, when
exiting from DSM.

Signed-off-by: Bai Ping <b51503@freescale.com>

diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index fdfd9cd5732e068519eb697c0bcc7933122a7cb8..5bff81ac29567f6abe48c4a0228d620ee25f0d1c 100644 (file)
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -209,6 +209,7 @@ struct imx6_cpu_pm_info {
        struct imx6_pm_base ccm_base;
        struct imx6_pm_base gpc_base;
        struct imx6_pm_base l2_base;
+       struct imx6_pm_base anatop_base;
        u32 ttbr1; /* Store TTBR1 */
        u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
        u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
@@ -597,6 +598,10 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
        pm_info->l2_base.vbase = (void __iomem *)
                                  IMX_IO_P2V(MX6Q_L2_BASE_ADDR);
 
+       pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR;
+       pm_info->anatop_base.vbase = (void __iomem *)
+                                 IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR);
+
        pm_info->cpu_type = socdata->cpu_type;
        pm_info->mmdc_io_num = socdata->mmdc_io_num;
        mmdc_offset_array = socdata->mmdc_io_offset;

diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index 3a21c1c92af4d431d4ff17a076d2546fcf73f675..989b5e65939a823801e028dec1f43f74bc21a21c 100644 (file)
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -58,9 +58,11 @@
 #define PM_INFO_MX6Q_GPC_V_OFFSET              0x34
 #define PM_INFO_MX6Q_L2_P_OFFSET               0x38
 #define PM_INFO_MX6Q_L2_V_OFFSET               0x3C
-#define PM_INFO_MX6Q_TTBR1_V_OFFSET            0x40
-#define PM_INFO_MMDC_IO_NUM_OFFSET             0x44
-#define PM_INFO_MMDC_IO_VAL_OFFSET             0x48
+#define PM_INFO_MX6Q_ANATOP_P_OFFSET           0x40
+#define PM_INFO_MX6Q_ANATOP_V_OFFSET           0x44
+#define PM_INFO_MX6Q_TTBR1_V_OFFSET            0x48
+#define PM_INFO_MMDC_IO_NUM_OFFSET             0x4c
+#define PM_INFO_MMDC_IO_VAL_OFFSET             0x50
 
 #define MX6Q_SRC_GPR1  0x20
 #define MX6Q_SRC_GPR2  0x24
@@ -71,6 +73,7 @@
 #define MX6Q_GPC_IMR3  0x10
 #define MX6Q_GPC_IMR4  0x14
 #define MX6Q_CCM_CCR   0x0
+#define MX6Q_ANATOP_CORE       0x140
 
        .align 3
 
@@ -391,6 +394,27 @@ rbc_loop:
        subs    r6, r6, #0x1
        bne     rbc_loop
 
+       /*
+        * ERR005852 Analog: Transition from Deep Sleep Mode to
+        * LDO Bypass Mode may cause the slow response of the
+        * VDDARM_CAP output.
+        *
+        * Software workaround:
+        * if internal ldo(VDDARM) bypassed, switch to analog bypass
+        * mode (0x1E), prio to entering DSM, and then, revert to the
+        * normal bypass mode, when exiting from DSM.
+        */
+       ldr     r11, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET]
+       ldr     r10, [r11, #MX6Q_ANATOP_CORE]
+       and     r10, r10, #0x1f
+       cmp     r10, #0x1f
+       bne     ldo_check_done1
+ldo_analog_bypass:
+       ldr     r10, [r11, #MX6Q_ANATOP_CORE]
+       bic     r10, r10, #0x1f
+       orr     r10, r10, #0x1e
+       str     r10, [r11, #MX6Q_ANATOP_CORE]
+ldo_check_done1:
        /* Zzz, enter stop mode */
        wfi
        nop
@@ -403,6 +427,16 @@ rbc_loop:
         * wakeup source, system should auto
         * resume, we need to restore MMDC IO first
         */
+       /* restore it with 0x1f if use ldo bypass mode.*/
+       ldr     r10, [r11, #MX6Q_ANATOP_CORE]
+       and     r10, r10, #0x1f
+       cmp     r10, #0x1e
+       bne     ldo_check_done2
+ldo_bypass_restore:
+       ldr     r10, [r11, #MX6Q_ANATOP_CORE]
+       orr     r10, r10, #0x1f
+       str     r10, [r11, #MX6Q_ANATOP_CORE]
+ldo_check_done2:
        mov     r5, #0x0
        resume_mmdc
 
@@ -422,6 +456,16 @@ resume:
        mcr     p15, 0, r6, c1, c0, 0
        isb
 
+       /* restore it with 0x1f if use ldo bypass mode.*/
+       ldr     r11, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET]
+       ldr     r7, [r11, #MX6Q_ANATOP_CORE]
+       and     r7, r7, #0x1f
+       cmp     r7, #0x1e
+       bne     ldo_check_done3
+       ldr     r7, [r11, #MX6Q_ANATOP_CORE]
+       orr     r7, r7, #0x1f
+       str     r7, [r11, #MX6Q_ANATOP_CORE]
+ldo_check_done3:
        /* get physical resume address from pm_info. */
        ldr     lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
        /* clear core0's entry and parameter */