]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
ARM: S5PV210: Add DMC map_desc table for supporting DMC access
authorJaecheol Lee <jc.lee@samsung.com>
Wed, 15 Sep 2010 06:57:37 +0000 (15:57 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Wed, 20 Oct 2010 22:52:17 +0000 (07:52 +0900)
This patch adds DMC(DRAM Memory Controller) map_desc table.
Because some driver such as CPUFREQ need to access DMC register.

Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
arch/arm/mach-s5pv210/cpu.c
arch/arm/mach-s5pv210/include/mach/map.h
arch/arm/plat-s5p/include/plat/map-s5p.h

index 2f16bfc0a116cd4bde8298b8c83ed4f076145080..3347a23074b4f28778a54b579206ee6a565679b6 100644 (file)
@@ -85,6 +85,16 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
                .pfn            = __phys_to_pfn(S5PV210_PA_SROMC),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_DMC0,
+               .pfn            = __phys_to_pfn(S5PV210_PA_DMC0),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_DMC1,
+               .pfn            = __phys_to_pfn(S5PV210_PA_DMC1),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
        }
 };
 
index bd9afd52466ad2cb787ed90ba394cc1f73870cb0..3e89c22412a3337c1155991ca4c1d3db4f88c35f 100644 (file)
@@ -96,6 +96,9 @@
 
 #define S5PV210_PA_ADC         (0xE1700000)
 
+#define S5PV210_PA_DMC0                (0xF0000000)
+#define S5PV210_PA_DMC1                (0xF1400000)
+
 /* compatibiltiy defines. */
 #define S3C_PA_UART            S5PV210_PA_UART
 #define S3C_PA_HSMMC0          S5PV210_PA_HSMMC(0)
index c4ff88bf6477d2797b6ba578c768b0edadaba073..24728947682daaac4731dc81a79ef9371b42c23b 100644 (file)
@@ -18,6 +18,8 @@
 #define S5P_VA_SYSTIMER                S3C_ADDR(0x01200000)
 #define S5P_VA_SROMC           S3C_ADDR(0x01100000)
 #define S5P_VA_SYSRAM          S3C_ADDR(0x01180000)
+#define S5P_VA_DMC0            S3C_ADDR(0x00A00000)
+#define S5P_VA_DMC1            S3C_ADDR(0x00A80000)
 
 #define S5P_VA_COMBINER_BASE   S3C_ADDR(0x00600000)
 #define S5P_VA_COMBINER(x)     (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)