value);
}
+static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
+{
+ int ret = -EINVAL, reg;
+ u8 uval;
+ s8 sval;
+ switch (mask) {
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ if (val > 255 || val < -256)
+ return -EINVAL;
+ sval = val;
+ reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
+ ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, (u8 *)&sval);
+ break;
+ case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
+ if (val & ~0xFF)
+ return -EINVAL;
+ uval = val;
+ reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
+ ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, &uval);
+ break;
+ }
+ return ret;
+}
+
static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
st->help.indio_dev->channels = lis3l02dq_channels;
st->help.indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
st->help.indio_dev->read_raw = &lis3l02dq_read_raw;
+ st->help.indio_dev->write_raw = &lis3l02dq_write_raw;
st->help.indio_dev->read_event_value = &lis3l02dq_read_thresh;
st->help.indio_dev->write_event_value = &lis3l02dq_write_thresh;
st->help.indio_dev->write_event_config = &lis3l02dq_write_event_config;