drm/amd/powerplay: enable set lowest mclk clock on baffin.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 446ed72feb02664f20eaa4dc9224c254abefee41..b77d7aa0f4120b59a7fdcc139c30961a89c3e8ba 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -3136,7 +3136,7 @@ static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
                                                            (1 << level));
 
        }
-/* uvd is enabled, can't set mclk low right now
+
        if (!data->mclk_dpm_key_disabled) {
                if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
                        level = phm_get_lowest_enabled_level(hwmgr,
@@ -3146,7 +3146,7 @@ static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
                                                            (1 << level));
                }
        }
-*/
+
        if (!data->pcie_dpm_key_disabled) {
                if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
                        level = phm_get_lowest_enabled_level(hwmgr,