mtd: fsl_ifc_nand: set NAND_NO_SUBPAGE_WRITE

This controller only does ECC on full-page accesses, even though the
ECC consists of multiple steps.  fsl_elbc_nand can get away with this
because the ECC of an all-0xff region will be all-0xff, but this is not
true with the ECC algorithms used by IFC.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 180bfa798e1325efec660367a76b26773320b4df..317a771f1587c94f3fd57c45c8e140deeb08b982 100644 (file)
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -823,7 +823,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 
        /* set up nand options */
        chip->bbt_options = NAND_BBT_USE_FLASH;
-
+       chip->options = NAND_NO_SUBPAGE_WRITE;
 
        if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
                chip->read_byte = fsl_ifc_read_byte16;