clk: samsung: exynos5260: fix typo in clock name

The parent name added in parent list as
mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, is different
than the defined parent due to typo.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Chander Kashyap <k.chander@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c
index ce3de97e5f11299fd1d852f8ec4f1d6612cbf571..2527e39aadcfbfafab2a0b5c97d4aab2e4809458 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -1581,7 +1581,7 @@ struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {
        FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
                        NULL, CLK_IS_ROOT, 125000000),
        FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
-                       "phyclk_mipi_dphy_4l_m_txbyteclkhs" , NULL,
+                       "phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
                        CLK_IS_ROOT, 187500000),
        FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
                        NULL, CLK_IS_ROOT, 24000000),