The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia
applications where system performance and cost are essential ingredients. The
integration of multimedia, human interface, and connectivity peripherals combined
with increased system bandwidth and on-chip memory provides customers a platform to
design the most demanding applications.
Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers
such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will
be submitted later.
Please enjoy the show.
Signed-off-by: Roy Huang <roy.huang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
config IRQCHIP_DEMUX_GPIO
bool
+ depends on (BF53x || BF561)
default y
source "init/Kconfig"
help
BF537 Processor Support.
+config BF542
+ bool "BF542"
+ help
+ BF542 Processor Support.
+
+config BF544
+ bool "BF544"
+ help
+ BF544 Processor Support.
+
+config BF548
+ bool "BF548"
+ help
+ BF548 Processor Support.
+
+config BF549
+ bool "BF549"
+ help
+ BF549 Processor Support.
+
config BF561
bool "BF561"
help
prompt "Silicon Rev"
default BF_REV_0_2 if BF537
default BF_REV_0_3 if BF533
+ default BF_REV_0_0 if BF549
+
+config BF_REV_0_0
+ bool "0.0"
+ depends on (BF549)
config BF_REV_0_2
bool "0.2"
endchoice
+config BF53x
+ bool
+ depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
+ default y
+
+config BF54x
+ bool
+ depends on (BF542 || BF544 || BF548 || BF549)
+ default y
+
config BFIN_DUAL_CORE
bool
depends on (BF561)
help
CM-BF537 support for EVAL- and DEV-Board.
+config BFIN548_EZKIT
+ bool "BF548-EZKIT"
+ depends on (BF548 || BF549)
+ help
+ BFIN548-EZKIT board Support.
+
config BFIN561_BLUETECHNIX_CM
bool "Bluetechnix CM-BF561"
depends on (BF561)
source "arch/blackfin/mach-bf533/Kconfig"
source "arch/blackfin/mach-bf561/Kconfig"
source "arch/blackfin/mach-bf537/Kconfig"
+source "arch/blackfin/mach-bf548/Kconfig"
menu "Board customizations"
config BFIN_DMA_5XX
bool "Enable DMA Support"
- depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561)
+ depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561 || BF54x)
default y
help
DMA driver for BF5xx.
endmenu
-if (BF537 || BF533)
+if (BF537 || BF533 || BF54x)
menu "CPU Frequency scaling"
machine-$(CONFIG_BF534) := bf537
machine-$(CONFIG_BF536) := bf537
machine-$(CONFIG_BF537) := bf537
+machine-$(CONFIG_BF548) := bf548
+machine-$(CONFIG_BF549) := bf548
machine-$(CONFIG_BF561) := bf561
MACHINE := $(machine-y)
export MACHINE
obj-y := \
entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
- sys_bfin.o time.o traps.o irqchip.o dma-mapping.o bfin_gpio.o \
- flat.o
+ sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o
+obj-$(CONFIG_BF53x) += bfin_gpio.o
+obj-$(CONFIG_BF561) += bfin_gpio.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o
obj-$(CONFIG_DUAL_CORE_TEST_MODULE) += dualcore_test.o
#include <linux/kernel.h>
#include <linux/param.h>
+#include <asm/blackfin.h>
#include <asm/dma.h>
#include <asm/cacheflush.h>
***************************************************************************/
static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
-#if defined (CONFIG_BF561)
-static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
- (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
-};
-#else
-static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
-#endif
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-#endif
/*------------------------------------------------------------------------------
* Set the Buffer Clear bit in the Configuration register of specific DMA
arch_initcall(blackfin_dma_init);
-/*
- * Form the channel find the irq number for that channel.
- */
-#if !defined(CONFIG_BF561)
-
-static int bf533_channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-#endif
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART_RX:
- ret_irq = IRQ_UART_RX;
- break;
-
- case CH_UART_TX:
- ret_irq = IRQ_UART_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
-
-# define channel2irq(channel) bf533_channel2irq(channel)
-
-#else
-
-static int bf561_channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI0:
- ret_irq = IRQ_PPI0;
- break;
- case CH_PPI1:
- ret_irq = IRQ_PPI1;
- break;
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
- case CH_UART_RX:
- ret_irq = IRQ_UART_RX;
- break;
- case CH_UART_TX:
- ret_irq = IRQ_UART_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MEM_DMA2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MEM_DMA3;
- break;
-
- case CH_IMEM_STREAM0_SRC:
- case CH_IMEM_STREAM0_DEST:
- ret_irq = IRQ_IMEM_DMA0;
- break;
- case CH_IMEM_STREAM1_SRC:
- case CH_IMEM_STREAM1_DEST:
- ret_irq = IRQ_IMEM_DMA1;
- break;
- }
- return ret_irq;
-}
-
-# define channel2irq(channel) bf561_channel2irq(channel)
-
-#endif
-
/*------------------------------------------------------------------------------
* Request the specific DMA channel from the system.
*-----------------------------------------------------------------------------*/
cplb_data[i].end,
SIZE_4M,
cplb_data[i].i_conf);
- } else {
+ } else
#endif
+ {
fill_cplbtab(t,
cplb_data[i].start,
a_start,
extra-y := head.o
-obj-y := ints-priority.o
+obj-y := ints-priority.o dma.o
obj-$(CONFIG_CPU_FREQ_BF533) += cpu.o
--- /dev/null
+/*
+ * File: arch/blackfin/mach-bf533/dma.c
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description: This file contains the simple DMA Implementation for Blackfin
+ *
+ * Modified:
+ * Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <asm/blackfin.h>
+#include <asm/dma.h>
+
+struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+ (struct dma_register *) DMA0_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_NEXT_DESC_PTR,
+ (struct dma_register *) DMA3_NEXT_DESC_PTR,
+ (struct dma_register *) DMA4_NEXT_DESC_PTR,
+ (struct dma_register *) DMA5_NEXT_DESC_PTR,
+ (struct dma_register *) DMA6_NEXT_DESC_PTR,
+ (struct dma_register *) DMA7_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
+};
+
+int bf533_channel2irq(unsigned int channel)
+{
+ int ret_irq = -1;
+
+ switch (channel) {
+ case CH_PPI:
+ ret_irq = IRQ_PPI;
+ break;
+
+ case CH_SPORT0_RX:
+ ret_irq = IRQ_SPORT0_RX;
+ break;
+
+ case CH_SPORT0_TX:
+ ret_irq = IRQ_SPORT0_TX;
+ break;
+
+ case CH_SPORT1_RX:
+ ret_irq = IRQ_SPORT1_RX;
+ break;
+
+ case CH_SPORT1_TX:
+ ret_irq = IRQ_SPORT1_TX;
+ break;
+
+ case CH_SPI:
+ ret_irq = IRQ_SPI;
+ break;
+
+ case CH_UART_RX:
+ ret_irq = IRQ_UART_RX;
+ break;
+
+ case CH_UART_TX:
+ ret_irq = IRQ_UART_TX;
+ break;
+
+ case CH_MEM_STREAM0_SRC:
+ case CH_MEM_STREAM0_DEST:
+ ret_irq = IRQ_MEM_DMA0;
+ break;
+
+ case CH_MEM_STREAM1_SRC:
+ case CH_MEM_STREAM1_DEST:
+ ret_irq = IRQ_MEM_DMA1;
+ break;
+ }
+ return ret_irq;
+}
extra-y := head.o
-obj-y := ints-priority.o
+obj-y := ints-priority.o dma.o
obj-$(CONFIG_CPU_FREQ) += cpu.o
--- /dev/null
+/*
+ * File: arch/blackfin/mach-bf537/dma.c
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description: This file contains the simple DMA Implementation for Blackfin
+ *
+ * Modified:
+ * Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <asm/blackfin.h>
+#include <asm/dma.h>
+
+struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+ (struct dma_register *) DMA0_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_NEXT_DESC_PTR,
+ (struct dma_register *) DMA3_NEXT_DESC_PTR,
+ (struct dma_register *) DMA4_NEXT_DESC_PTR,
+ (struct dma_register *) DMA5_NEXT_DESC_PTR,
+ (struct dma_register *) DMA6_NEXT_DESC_PTR,
+ (struct dma_register *) DMA7_NEXT_DESC_PTR,
+ (struct dma_register *) DMA8_NEXT_DESC_PTR,
+ (struct dma_register *) DMA9_NEXT_DESC_PTR,
+ (struct dma_register *) DMA10_NEXT_DESC_PTR,
+ (struct dma_register *) DMA11_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
+};
+
+int channel2irq(unsigned int channel)
+{
+ int ret_irq = -1;
+
+ switch (channel) {
+ case CH_PPI:
+ ret_irq = IRQ_PPI;
+ break;
+
+ case CH_EMAC_RX:
+ ret_irq = IRQ_MAC_RX;
+ break;
+
+ case CH_EMAC_TX:
+ ret_irq = IRQ_MAC_TX;
+ break;
+
+ case CH_UART1_RX:
+ ret_irq = IRQ_UART1_RX;
+ break;
+
+ case CH_UART1_TX:
+ ret_irq = IRQ_UART1_TX;
+ break;
+
+ case CH_SPORT0_RX:
+ ret_irq = IRQ_SPORT0_RX;
+ break;
+
+ case CH_SPORT0_TX:
+ ret_irq = IRQ_SPORT0_TX;
+ break;
+
+ case CH_SPORT1_RX:
+ ret_irq = IRQ_SPORT1_RX;
+ break;
+
+ case CH_SPORT1_TX:
+ ret_irq = IRQ_SPORT1_TX;
+ break;
+
+ case CH_SPI:
+ ret_irq = IRQ_SPI;
+ break;
+
+ case CH_UART_RX:
+ ret_irq = IRQ_UART_RX;
+ break;
+
+ case CH_UART_TX:
+ ret_irq = IRQ_UART_TX;
+ break;
+
+ case CH_MEM_STREAM0_SRC:
+ case CH_MEM_STREAM0_DEST:
+ ret_irq = IRQ_MEM_DMA0;
+ break;
+
+ case CH_MEM_STREAM1_SRC:
+ case CH_MEM_STREAM1_DEST:
+ ret_irq = IRQ_MEM_DMA1;
+ break;
+ }
+ return ret_irq;
+}
--- /dev/null
+if (BF54x)
+
+menu "BF548 Specific Configuration"
+
+comment "Interrupt Priority Assignment"
+menu "Priority"
+
+config IRQ_PLL_WAKEUP
+ int "IRQ_PLL_WAKEUP"
+ default 7
+config IRQ_DMAC0_ERR
+ int "IRQ_DMAC0_ERR"
+ default 7
+config IRQ_EPPI0_ERR
+ int "IRQ_EPPI0_ERR"
+ default 7
+config IRQ_SPORT0_ERR
+ int "IRQ_SPORT0_ERR"
+ default 7
+config IRQ_SPORT1_ERR
+ int "IRQ_SPORT1_ERR"
+ default 7
+config IRQ_SPI0_ERR
+ int "IRQ_SPI0_ERR"
+ default 7
+config IRQ_UART0_ERR
+ int "IRQ_UART0_ERR"
+ default 7
+config IRQ_RTC
+ int "IRQ_RTC"
+ default 8
+config IRQ_EPPI0
+ int "IRQ_EPPI0"
+ default 8
+config IRQ_SPORT0_RX
+ int "IRQ_SPORT0_RX"
+ default 9
+config IRQ_SPORT0_TX
+ int "IRQ_SPORT0_TX"
+ default 9
+config IRQ_SPORT1_RX
+ int "IRQ_SPORT1_RX"
+ default 9
+config IRQ_SPORT1_TX
+ int "IRQ_SPORT1_TX"
+ default 9
+config IRQ_SPI0
+ int "IRQ_SPI0"
+ default 10
+config IRQ_UART0_RX
+ int "IRQ_UART0_RX"
+ default 10
+config IRQ_UART0_TX
+ int "IRQ_UART0_TX"
+ default 10
+config IRQ_TIMER8
+ int "IRQ_TIMER8"
+ default 11
+config IRQ_TIMER9
+ int "IRQ_TIMER9"
+ default 11
+config IRQ_TIMER10
+ int "IRQ_TIMER10"
+ default 11
+config IRQ_PINT0
+ int "IRQ_PINT0"
+ default 12
+config IRQ_PINT1
+ int "IRQ_PINT0"
+ default 12
+config IRQ_MDMAS0
+ int "IRQ_MDMAS0"
+ default 13
+config IRQ_MDMAS1
+ int "IRQ_DMDMAS1"
+ default 13
+config IRQ_WATCHDOG
+ int "IRQ_WATCHDOG"
+ default 13
+config IRQ_DMAC1_ERR
+ int "IRQ_DMAC1_ERR"
+ default 7
+config IRQ_SPORT2_ERR
+ int "IRQ_SPORT2_ERR"
+ default 7
+config IRQ_SPORT3_ERR
+ int "IRQ_SPORT3_ERR"
+ default 7
+config IRQ_MXVR_DATA
+ int "IRQ MXVR Data"
+ default 7
+config IRQ_SPI1_ERR
+ int "IRQ_SPI1_ERR"
+ default 7
+config IRQ_SPI2_ERR
+ int "IRQ_SPI2_ERR"
+ default 7
+config IRQ_UART1_ERR
+ int "IRQ_UART1_ERR"
+ default 7
+config IRQ_UART2_ERR
+ int "IRQ_UART2_ERR"
+ default 7
+config IRQ_CAN0_ERR
+ int "IRQ_CAN0_ERR"
+ default 7
+config IRQ_SPORT2_RX
+ int "IRQ_SPORT2_RX"
+ default 9
+config IRQ_SPORT2_TX
+ int "IRQ_SPORT2_TX"
+ default 9
+config IRQ_SPORT3_RX
+ int "IRQ_SPORT3_RX"
+ default 9
+config IRQ_SPORT3_TX
+ int "IRQ_SPORT3_TX"
+ default 9
+config IRQ_EPPI1
+ int "IRQ_EPPI1"
+ default 9
+config IRQ_EPPI2
+ int "IRQ_EPPI2"
+ default 9
+config IRQ_SPI1
+ int "IRQ_SPI1"
+ default 10
+config IRQ_SPI2
+ int "IRQ_SPI2"
+ default 10
+config IRQ_UART1_RX
+ int "IRQ_UART1_RX"
+ default 10
+config IRQ_UART1_TX
+ int "IRQ_UART1_TX"
+ default 10
+config IRQ_ATAPI_RX
+ int "IRQ_ATAPI_RX"
+ default 10
+config IRQ_ATAPI_TX
+ int "IRQ_ATAPI_TX"
+ default 10
+config IRQ_TWI0
+ int "IRQ_TWI0"
+ default 11
+config IRQ_TWI1
+ int "IRQ_TWI1"
+ default 11
+config IRQ_CAN0_RX
+ int "IRQ_CAN_RX"
+ default 11
+config IRQ_CAN0_TX
+ int "IRQ_CAN_TX"
+ default 11
+config IRQ_MDMAS2
+ int "IRQ_MDMAS2"
+ default 13
+config IRQ_MDMAS3
+ int "IRQ_DMMAS3"
+ default 13
+config IRQ_MXVR_ERR
+ int "IRQ_MXVR_ERR"
+ default 11
+config IRQ_MXVR_MSG
+ int "IRQ_MXVR_MSG"
+ default 11
+config IRQ_MXVR_PKT
+ int "IRQ_MXVR_PKT"
+ default 11
+config IRQ_EPPI1_ERR
+ int "IRQ_EPPI1_ERR"
+ default 7
+config IRQ_EPPI2_ERR
+ int "IRQ_EPPI2_ERR"
+ default 7
+config IRQ_UART3_ERR
+ int "IRQ_UART3_ERR"
+ default 7
+config IRQ_HOST_ERR
+ int "IRQ_HOST_ERR"
+ default 7
+config IRQ_PIXC_ERR
+ int "IRQ_PIXC_ERR"
+ default 7
+config IRQ_NFC_ERR
+ int "IRQ_NFC_ERR"
+ default 7
+config IRQ_ATAPI_ERR
+ int "IRQ_ATAPI_ERR"
+ default 7
+config IRQ_CAN1_ERR
+ int "IRQ_CAN1_ERR"
+ default 7
+config IRQ_HS_DMA_ERR
+ int "IRQ Handshake DMA Status"
+ default 7
+config IRQ_PIXC_IN0
+ int "IRQ PIXC IN0"
+ default 8
+config IRQ_PIXC_IN1
+ int "IRQ PIXC IN1"
+ default 8
+config IRQ_PIXC_OUT
+ int "IRQ PIXC OUT"
+ default 8
+config IRQ_SDH
+ int "IRQ SDH"
+ default 8
+config IRQ_CNT
+ int "IRQ CNT"
+ default 8
+config IRQ_KEY
+ int "IRQ KEY"
+ default 8
+config IRQ_CAN1_RX
+ int "IRQ CAN1 RX"
+ default 11
+config IRQ_CAN1_TX
+ int "IRQ_CAN1_TX"
+ default 11
+config IRQ_SDH_MASK0
+ int "IRQ_SDH_MASK0"
+ default 11
+config IRQ_SDH_MASK1
+ int "IRQ_SDH_MASK1"
+ default 11
+config IRQ_USB_INT0
+ int "IRQ USB INT0"
+ default 11
+config IRQ_USB_INT1
+ int "IRQ USB INT1"
+ default 11
+config IRQ_USB_INT2
+ int "IRQ USB INT2"
+ default 11
+config IRQ_USB_DMA
+ int "IRQ USB DMA"
+ default 11
+config IRQ_OTPSEC
+ int "IRQ OPTSEC"
+ default 11
+config IRQ_TIMER0
+ int "IRQ_TIMER0"
+ default 11
+config IRQ_TIMER1
+ int "IRQ_TIMER1"
+ default 11
+config IRQ_TIMER2
+ int "IRQ_TIMER2"
+ default 11
+config IRQ_TIMER3
+ int "IRQ_TIMER3"
+ default 11
+config IRQ_TIMER4
+ int "IRQ_TIMER4"
+ default 11
+config IRQ_TIMER5
+ int "IRQ_TIMER5"
+ default 11
+config IRQ_TIMER6
+ int "IRQ_TIMER6"
+ default 11
+config IRQ_TIMER7
+ int "IRQ_TIMER7"
+ default 11
+config IRQ_PINT2
+ int "IRQ_PIN2"
+ default 11
+config IRQ_PINT3
+ int "IRQ_PIN3"
+ default 11
+
+ help
+ Enter the priority numbers between 7-13 ONLY. Others are Reserved.
+ This applies to all the above. It is not recommended to assign the
+ highest priority number 7 to UART or any other device.
+
+endmenu
+
+endmenu
+
+endif
--- /dev/null
+#
+# arch/blackfin/mach-bf537/Makefile
+#
+
+extra-y := head.o
+
+obj-y := ints-priority.o dma.o gpio.o
+
+obj-$(CONFIG_CPU_FREQ) += cpu.o
--- /dev/null
+#
+# arch/blackfin/mach-bf548/boards/Makefile
+#
+
+obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o led.o
--- /dev/null
+/*
+ * File: arch/blackfin/mach-bf548/boards/ezkit.c
+ * Based on: arch/blackfin/mach-bf537/boards/ezkit.c
+ * Author: Aidan Williams <aidan@nicta.com.au>
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ * Copyright 2005 National ICT Australia (NICTA)
+ * Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <asm/irq.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <asm/bfin5xx_spi.h>
+
+/*
+ * Name the Board for the /proc/cpuinfo
+ */
+char *bfin_board_name = "ADSP-BF548-EZKIT";
+
+/*
+ * Driver needs to know address, irq and flag pin.
+ */
+
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+static struct platform_device rtc_device = {
+ .name = "rtc-bfin",
+ .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+static struct resource bfin_uart_resources[] = {
+#ifdef CONFIG_SERIAL_BFIN_UART0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+ {
+ .start = 0xFFC02000,
+ .end = 0xFFC020FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART2
+ {
+ .start = 0xFFC02100,
+ .end = 0xFFC021FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART3
+ {
+ .start = 0xFFC03100,
+ .end = 0xFFC031FF,
+ },
+#endif
+};
+
+static struct platform_device bfin_uart_device = {
+ .name = "bfin-uart",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(bfin_uart_resources),
+ .resource = bfin_uart_resources,
+};
+#endif
+
+static struct platform_device *ezkit_devices[] __initdata = {
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+ &rtc_device,
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+ &bfin_uart_device,
+#endif
+};
+
+static int __init stamp_init(void)
+{
+ printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
+ platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
+ return 0;
+}
+
+arch_initcall(stamp_init);
--- /dev/null
+/****************************************************
+ * LED1 ---- PG6 LED2 ---- PG7 *
+ * LED3 ---- PG8 LED4 ---- PG9 *
+ * LED5 ---- PG10 LED6 ---- PG11 *
+ ****************************************************/
+
+#include <linux/linkage.h>
+#include <asm/blackfin.h>
+
+/* All functions in this file save the registers they uses.
+ So there is no need to save any registers before calling them. */
+
+ .text;
+
+/* Initialize LEDs. */
+
+ENTRY(_led_init)
+ LINK 0;
+ [--SP] = P0;
+ [--SP] = R0;
+ [--SP] = R1;
+ [--SP] = R2;
+ R1 = (PG6|PG7|PG8|PG9|PG10|PG11)(Z);
+ R2 = ~R1;
+
+ P0.H = hi(PORTG_FER);
+ P0.L = lo(PORTG_FER);
+ R0 = W[P0](Z);
+ SSYNC;
+ R0 = R0 & R2;
+ W[P0] = R0.L;
+ SSYNC;
+
+ P0.H = hi(PORTG_DIR_SET);
+ P0.L = lo(PORTG_DIR_SET);
+ W[P0] = R1.L;
+ SSYNC;
+
+ P0.H = hi(PORTG_INEN);
+ P0.L = lo(PORTG_INEN);
+ R0 = W[P0](Z);
+ SSYNC;
+ R0 = R0 & R2;
+ W[P0] = R0.L;
+ SSYNC;
+
+ R2 = [SP++];
+ R1 = [SP++];
+ R0 = [SP++];
+ P0 = [SP++];
+ RTS;
+ .size _led_init, .-_led_init
+
+/* Set one LED on. Leave other LEDs unchanged.
+ It expects the LED number passed through R0. */
+
+ENTRY(_led_on)
+ LINK 0;
+ [--SP] = P0;
+ [--SP] = R1;
+ CALL _led_init;
+ R1 = 1;
+ R0 += 5;
+ R1 <<= R0;
+ P0.H = hi(PORTG_SET);
+ P0.L = lo(PORTG_SET);
+ W[P0] = R1.L;
+ SSYNC;
+ R1 = [SP++];
+ P0 = [SP++];
+ UNLINK;
+ RTS;
+ .size _led_on, .-_led_on
+
+/* Set one LED off. Leave other LEDs unchanged. */
+
+ENTRY(_led_off)
+ LINK 0;
+ [--SP] = P0;
+ [--SP] = R1;
+ CALL _led_init;
+ R1 = 1;
+ R0 += 5;
+ R1 <<= R0;
+ P0.H = hi(PORTG_CLEAR);
+ P0.L = lo(PORTG_CLEAR);
+ W[P0] = R1.L;
+ SSYNC;
+ R1 = [SP++];
+ P0 = [SP++];
+ UNLINK;
+ RTS;
+ .size _led_off, .-_led_off
+
+/* Toggle one LED. Leave other LEDs unchanged. */
+
+ENTRY(_led_toggle)
+ LINK 0;
+ [--SP] = P0;
+ [--SP] = R1;
+ CALL _led_init;
+ R1 = 1;
+ R0 += 5;
+ R1 <<= R0;
+ P0.H = hi(PORTG);
+ P0.L = lo(PORTG);
+ R0 = W[P0](Z);
+ SSYNC;
+ R0 = R0 ^ R1;
+ W[P0] = R0.L;
+ SSYNC;
+ R1 = [SP++];
+ P0 = [SP++];
+ UNLINK;
+ RTS;
+ .size _led_toggle, .-_led_toggle
+
+/* Display the number using LEDs in binary format. */
+
+ENTRY(_led_disp_num)
+ LINK 0;
+ [--SP] = P0;
+ [--SP] = R1;
+ [--SP] = R2;
+ CALL _led_init;
+ R1 = 0x3f(X);
+ R0 = R0 & R1;
+ R2 = 6(X);
+ R0 <<= R2;
+ R1 <<= R2;
+ P0.H = hi(PORTG);
+ P0.L = lo(PORTG);
+ R2 = W[P0](Z);
+ SSYNC;
+ R1 = ~R1;
+ R2 = R2 & R1;
+ R2 = R2 | R0;
+ W[P0] = R2.L;
+ SSYNC;
+ R2 = [SP++];
+ R1 = [SP++];
+ P0 = [SP++];
+ UNLINK;
+ RTS;
+ .size _led_disp_num, .-_led_disp_num
+
+/* Toggle the number using LEDs in binary format. */
+
+ENTRY(_led_toggle_num)
+ LINK 0;
+ [--SP] = P0;
+ [--SP] = R1;
+ [--SP] = R2;
+ CALL _led_init;
+ R1 = 0x3f(X);
+ R0 = R0 & R1;
+ R1 = 6(X);
+ R0 <<= R1;
+ P0.H = hi(PORTG);
+ P0.L = lo(PORTG);
+ R1 = W[P0](Z);
+ SSYNC;
+ R1 = R1 ^ R0;
+ W[P0] = R1.L;
+ SSYNC;
+ R2 = [SP++];
+ R1 = [SP++];
+ P0 = [SP++];
+ UNLINK;
+ RTS;
+ .size _led_toggle_num, .-_led_toggle_num
+
--- /dev/null
+/*
+ * File: arch/blackfin/mach-bf548/cpu.c
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description: clock scaling for the bf54x
+ *
+ * Modified:
+ * Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/cpufreq.h>
+#include <asm/dpmc.h>
+#include <linux/fs.h>
+#include <asm/bfin-global.h>
+
+/* CONFIG_CLKIN_HZ=25000000 */
+#define VCO5 (CONFIG_CLKIN_HZ*45)
+#define VCO4 (CONFIG_CLKIN_HZ*36)
+#define VCO3 (CONFIG_CLKIN_HZ*27)
+#define VCO2 (CONFIG_CLKIN_HZ*18)
+#define VCO1 (CONFIG_CLKIN_HZ*9)
+#define VCO(x) VCO##x
+
+#define MFREQ(x) {VCO(x),VCO(x)/4},{VCO(x),VCO(x)/2},{VCO(x),VCO(x)}
+/* frequency */
+static struct cpufreq_frequency_table bf548_freq_table[] = {
+ MFREQ(1),
+ MFREQ(3),
+ {VCO4, VCO4 / 2}, {VCO4, VCO4},
+ MFREQ(5),
+ {0, CPUFREQ_TABLE_END},
+};
+
+/*
+ * dpmc_fops->ioctl()
+ * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+ */
+static int bf548_getfreq(unsigned int cpu)
+{
+ unsigned long cclk_mhz;
+
+ /* The driver only support single cpu */
+ if (cpu == 0)
+ dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz);
+ else
+ cclk_mhz = -1;
+
+ return cclk_mhz;
+}
+
+static int bf548_target(struct cpufreq_policy *policy,
+ unsigned int target_freq, unsigned int relation)
+{
+ unsigned long cclk_mhz;
+ unsigned long vco_mhz;
+ unsigned long flags;
+ unsigned int index;
+ struct cpufreq_freqs freqs;
+
+ if (cpufreq_frequency_table_target(policy, bf548_freq_table, target_freq, relation, &index))
+ return -EINVAL;
+
+ cclk_mhz = bf548_freq_table[index].frequency;
+ vco_mhz = bf548_freq_table[index].index;
+
+ dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz);
+ freqs.old = bf548_getfreq(0);
+ freqs.new = cclk_mhz;
+ freqs.cpu = 0;
+
+ pr_debug("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n",
+ cclk_mhz, vco_mhz, index, target_freq, freqs.old);
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+ local_irq_save(flags);
+ dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz);
+ local_irq_restore(flags);
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+ vco_mhz = get_vco();
+ cclk_mhz = get_cclk();
+ return 0;
+}
+
+/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
+ * this platform, anyway.
+ */
+static int bf548_verify_speed(struct cpufreq_policy *policy)
+{
+ return cpufreq_frequency_table_verify(policy, &bf548_freq_table);
+}
+
+static int __init __bf548_cpu_init(struct cpufreq_policy *policy)
+{
+ if (policy->cpu != 0)
+ return -EINVAL;
+
+ policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+
+ policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+ /*Now ,only support one cpu */
+ policy->cur = bf548_getfreq(0);
+ cpufreq_frequency_table_get_attr(bf548_freq_table, policy->cpu);
+ return cpufreq_frequency_table_cpuinfo(policy, bf548_freq_table);
+}
+
+static struct freq_attr *bf548_freq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL,
+};
+
+static struct cpufreq_driver bf548_driver = {
+ .verify = bf548_verify_speed,
+ .target = bf548_target,
+ .get = bf548_getfreq,
+ .init = __bf548_cpu_init,
+ .name = "bf548",
+ .owner = THIS_MODULE,
+ .attr = bf548_freq_attr,
+};
+
+static int __init bf548_cpu_init(void)
+{
+ return cpufreq_register_driver(&bf548_driver);
+}
+
+static void __exit bf548_cpu_exit(void)
+{
+ cpufreq_unregister_driver(&bf548_driver);
+}
+
+MODULE_AUTHOR("Mickael Kang");
+MODULE_DESCRIPTION("cpufreq driver for BF548 CPU");
+MODULE_LICENSE("GPL");
+
+module_init(bf548_cpu_init);
+module_exit(bf548_cpu_exit);
--- /dev/null
+/*
+ * File: arch/blackfin/mach-bf561/dma.c
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description: This file contains the simple DMA Implementation for Blackfin
+ *
+ * Modified:
+ * Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <asm/blackfin.h>
+#include <asm/dma.h>
+
+ struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+ (struct dma_register *) DMA0_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_NEXT_DESC_PTR,
+ (struct dma_register *) DMA3_NEXT_DESC_PTR,
+ (struct dma_register *) DMA4_NEXT_DESC_PTR,
+ (struct dma_register *) DMA5_NEXT_DESC_PTR,
+ (struct dma_register *) DMA6_NEXT_DESC_PTR,
+ (struct dma_register *) DMA7_NEXT_DESC_PTR,
+ (struct dma_register *) DMA8_NEXT_DESC_PTR,
+ (struct dma_register *) DMA9_NEXT_DESC_PTR,
+ (struct dma_register *) DMA10_NEXT_DESC_PTR,
+ (struct dma_register *) DMA11_NEXT_DESC_PTR,
+ (struct dma_register *) DMA12_NEXT_DESC_PTR,
+ (struct dma_register *) DMA13_NEXT_DESC_PTR,
+ (struct dma_register *) DMA14_NEXT_DESC_PTR,
+ (struct dma_register *) DMA15_NEXT_DESC_PTR,
+ (struct dma_register *) DMA16_NEXT_DESC_PTR,
+ (struct dma_register *) DMA17_NEXT_DESC_PTR,
+ (struct dma_register *) DMA18_NEXT_DESC_PTR,
+ (struct dma_register *) DMA19_NEXT_DESC_PTR,
+ (struct dma_register *) DMA20_NEXT_DESC_PTR,
+ (struct dma_register *) DMA21_NEXT_DESC_PTR,
+ (struct dma_register *) DMA22_NEXT_DESC_PTR,
+ (struct dma_register *) DMA23_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
+};
+
+int channel2irq(unsigned int channel)
+{
+ int ret_irq = -1;
+
+ switch (channel) {
+ case CH_SPORT0_RX:
+ ret_irq = IRQ_SPORT0_RX;
+ break;
+ case CH_SPORT0_TX:
+ ret_irq = IRQ_SPORT0_TX;
+ break;
+ case CH_SPORT1_RX:
+ ret_irq = IRQ_SPORT1_RX;
+ break;
+ case CH_SPORT1_TX:
+ ret_irq = IRQ_SPORT1_TX;
+ case CH_SPI0:
+ ret_irq = IRQ_SPI0;
+ break;
+ case CH_SPI1:
+ ret_irq = IRQ_SPI1;
+ break;
+ case CH_UART0_RX:
+ ret_irq = IRQ_UART_RX;
+ break;
+ case CH_UART0_TX:
+ ret_irq = IRQ_UART_TX;
+ break;
+ case CH_UART1_RX:
+ ret_irq = IRQ_UART_RX;
+ break;
+ case CH_UART1_TX:
+ ret_irq = IRQ_UART_TX;
+ break;
+ case CH_EPPI0:
+ ret_irq = IRQ_EPPI0;
+ break;
+ case CH_EPPI1:
+ ret_irq = IRQ_EPPI1;
+ break;
+ case CH_EPPI2:
+ ret_irq = IRQ_EPPI2;
+ break;
+ case CH_PIXC_IMAGE:
+ ret_irq = IRQ_PIXC_IN0;
+ break;
+ case CH_PIXC_OVERLAY:
+ ret_irq = IRQ_PIXC_IN1;
+ break;
+ case CH_PIXC_OUTPUT:
+ ret_irq = IRQ_PIXC_OUT;
+ break;
+ case CH_SPORT2_RX:
+ ret_irq = IRQ_SPORT2_RX;
+ break;
+ case CH_SPORT2_TX:
+ ret_irq = IRQ_SPORT2_TX;
+ break;
+ case CH_SPORT3_RX:
+ ret_irq = IRQ_SPORT3_RX;
+ break;
+ case CH_SPORT3_TX:
+ ret_irq = IRQ_SPORT3_TX;
+ break;
+ case CH_SDH:
+ ret_irq = IRQ_SDH;
+ break;
+ case CH_SPI2:
+ ret_irq = IRQ_SPI2;
+ break;
+ case CH_MEM_STREAM0_SRC:
+ case CH_MEM_STREAM0_DEST:
+ ret_irq = IRQ_MDMAS0;
+ break;
+ case CH_MEM_STREAM1_SRC:
+ case CH_MEM_STREAM1_DEST:
+ ret_irq = IRQ_MDMAS1;
+ break;
+ case CH_MEM_STREAM2_SRC:
+ case CH_MEM_STREAM2_DEST:
+ ret_irq = IRQ_MDMAS2;
+ break;
+ case CH_MEM_STREAM3_SRC:
+ case CH_MEM_STREAM3_DEST:
+ ret_irq = IRQ_MDMAS3;
+ break;
+ }
+ return ret_irq;
+}
--- /dev/null
+/*
+ * File: arch/blackfin/mach-bf548/gpio.c
+ * Based on:
+ * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
+ *
+ * Created:
+ * Description: GPIO Abstraction Layer
+ *
+ * Modified:
+ * Copyright 2007 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <linux/irq.h>
+
+static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
+ (struct gpio_port_t *) PORTA_FER,
+ (struct gpio_port_t *) PORTB_FER,
+ (struct gpio_port_t *) PORTC_FER,
+ (struct gpio_port_t *) PORTD_FER,
+ (struct gpio_port_t *) PORTE_FER,
+ (struct gpio_port_t *) PORTF_FER,
+ (struct gpio_port_t *) PORTG_FER,
+ (struct gpio_port_t *) PORTH_FER,
+ (struct gpio_port_t *) PORTI_FER,
+ (struct gpio_port_t *) PORTJ_FER,
+};
+
+static unsigned short reserved_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
+
+inline int check_gpio(unsigned short gpio)
+{
+ if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 \
+ || gpio == GPIO_PH14 || gpio == GPIO_PH15 \
+ || gpio > MAX_BLACKFIN_GPIOS)
+ return -EINVAL;
+ return 0;
+}
+
+static void port_setup(unsigned short gpio, unsigned short usage)
+{
+ if (usage == GPIO_USAGE) {
+ if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio))
+ printk(KERN_WARNING "bfin-gpio: Possible Conflict with Peripheral "
+ "usage and GPIO %d detected!\n", gpio);
+ gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
+ } else
+ gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
+ SSYNC();
+}
+
+static int __init bfin_gpio_init(void)
+{
+ int i;
+
+ printk(KERN_INFO "Blackfin GPIO Controller\n");
+
+ for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE)
+ reserved_map[gpio_bank(i)] = 0;
+
+ return 0;
+}
+
+arch_initcall(bfin_gpio_init);
+
+
+/***********************************************************
+*
+* FUNCTIONS: Blackfin GPIO Driver
+*
+* INPUTS/OUTPUTS:
+* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
+*
+*
+* DESCRIPTION: Blackfin GPIO Driver API
+*
+* CAUTION:
+*************************************************************
+* MODIFICATION HISTORY :
+**************************************************************/
+
+int gpio_request(unsigned short gpio, const char *label)
+{
+ unsigned long flags;
+
+ if (check_gpio(gpio) < 0)
+ return -EINVAL;
+
+ local_irq_save(flags);
+
+ if (unlikely(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
+ printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio);
+ dump_stack();
+ local_irq_restore(flags);
+ return -EBUSY;
+ }
+ reserved_map[gpio_bank(gpio)] |= gpio_bit(gpio);
+
+ local_irq_restore(flags);
+
+ port_setup(gpio, GPIO_USAGE);
+
+ return 0;
+}
+EXPORT_SYMBOL(gpio_request);
+
+
+void gpio_free(unsigned short gpio)
+{
+ unsigned long flags;
+
+ if (check_gpio(gpio) < 0)
+ return;
+
+ local_irq_save(flags);
+
+ if (unlikely(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
+ printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
+ dump_stack();
+ local_irq_restore(flags);
+ return;
+ }
+
+ reserved_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
+
+ local_irq_restore(flags);
+}
+EXPORT_SYMBOL(gpio_free);
+
+
+void gpio_direction_input(unsigned short gpio)
+{
+ unsigned long flags;
+
+ BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)));
+
+ local_irq_save(flags);
+ gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
+ gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
+ local_irq_restore(flags);
+}
+EXPORT_SYMBOL(gpio_direction_input);
+
+void gpio_direction_output(unsigned short gpio)
+{
+ unsigned long flags;
+
+ BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)));
+
+ local_irq_save(flags);
+ gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
+ gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
+ local_irq_restore(flags);
+}
+EXPORT_SYMBOL(gpio_direction_output);
--- /dev/null
+/*
+ * File: arch/blackfin/mach-bf548/head.S
+ * Based on: arch/blackfin/mach-bf537/head.S
+ * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
+ *
+ * Created: 1998
+ * Description: Startup code for Blackfin BF548
+ *
+ * Modified:
+ * Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/linkage.h>
+#include <asm/blackfin.h>
+#if CONFIG_BFIN_KERNEL_CLOCK
+#include <asm/mach/mem_init.h>
+#endif
+
+.global __rambase
+.global __ramstart
+.global __ramend
+.extern ___bss_stop
+.extern ___bss_start
+.extern _bf53x_relocate_l1_mem
+
+#define INITIAL_STACK 0xFFB01000
+
+.text
+
+ENTRY(__start)
+ENTRY(__stext)
+ /* R0: argument of command line string, passed from uboot, save it */
+ R7 = R0;
+ /* Set the SYSCFG register */
+ R0 = 0x36;
+ SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
+ R0 = 0;
+
+ /* Clear Out All the data and pointer Registers*/
+ R1 = R0;
+ R2 = R0;
+ R3 = R0;
+ R4 = R0;
+ R5 = R0;
+ R6 = R0;
+
+ P0 = R0;
+ P1 = R0;
+ P2 = R0;
+ P3 = R0;
+ P4 = R0;
+ P5 = R0;
+
+ LC0 = r0;
+ LC1 = r0;
+ L0 = r0;
+ L1 = r0;
+ L2 = r0;
+ L3 = r0;
+
+ /* Clear Out All the DAG Registers*/
+ B0 = r0;
+ B1 = r0;
+ B2 = r0;
+ B3 = r0;
+
+ I0 = r0;
+ I1 = r0;
+ I2 = r0;
+ I3 = r0;
+
+ M0 = r0;
+ M1 = r0;
+ M2 = r0;
+ M3 = r0;
+
+ /* Turn off the icache */
+ p0.l = (IMEM_CONTROL & 0xFFFF);
+ p0.h = (IMEM_CONTROL >> 16);
+ R1 = [p0];
+ R0 = ~ENICPLB;
+ R0 = R0 & R1;
+ [p0] = R0;
+ SSYNC;
+
+ /* Turn off the dcache */
+ p0.l = (DMEM_CONTROL & 0xFFFF);
+ p0.h = (DMEM_CONTROL >> 16);
+ R1 = [p0];
+ R0 = ~ENDCPLB;
+ R0 = R0 & R1;
+ [p0] = R0;
+ SSYNC;
+
+ /* Initialize stack pointer */
+ SP.L = LO(INITIAL_STACK);
+ SP.H = HI(INITIAL_STACK);
+ FP = SP;
+ USP = SP;
+
+ /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
+ call _bf53x_relocate_l1_mem;
+#if CONFIG_BFIN_KERNEL_CLOCK
+ call _start_dma_code;
+#endif
+ /* Code for initializing Async memory banks */
+
+ p2.h = hi(EBIU_AMBCTL1);
+ p2.l = lo(EBIU_AMBCTL1);
+ r0.h = hi(AMBCTL1VAL);
+ r0.l = lo(AMBCTL1VAL);
+ [p2] = r0;
+ ssync;
+
+ p2.h = hi(EBIU_AMBCTL0);
+ p2.l = lo(EBIU_AMBCTL0);
+ r0.h = hi(AMBCTL0VAL);
+ r0.l = lo(AMBCTL0VAL);
+ [p2] = r0;
+ ssync;
+
+ p2.h = hi(EBIU_AMGCTL);
+ p2.l = lo(EBIU_AMGCTL);
+ r0 = AMGCTLVAL;
+ w[p2] = r0;
+ ssync;
+
+ /* This section keeps the processor in supervisor mode
+ * during kernel boot. Switches to user mode at end of boot.
+ * See page 3-9 of Hardware Reference manual for documentation.
+ */
+
+ /* EVT15 = _real_start */
+
+ p0.l = lo(EVT15);
+ p0.h = hi(EVT15);
+ p1.l = _real_start;
+ p1.h = _real_start;
+ [p0] = p1;
+ csync;
+
+ p0.l = lo(IMASK);
+ p0.h = hi(IMASK);
+ p1.l = IMASK_IVG15;
+ p1.h = 0x0;
+ [p0] = p1;
+ csync;
+
+ raise 15;
+ p0.l = .LWAIT_HERE;
+ p0.h = .LWAIT_HERE;
+ reti = p0;
+#if defined (ANOMALY_05000281)
+ nop;
+ nop;
+ nop;
+#endif
+ rti;
+
+.LWAIT_HERE:
+ jump .LWAIT_HERE;
+
+ENTRY(_real_start)
+ [ -- sp ] = reti;
+ p0.l = lo(WDOG_CTL);
+ p0.h = hi(WDOG_CTL);
+ r0 = 0xAD6(z);
+ w[p0] = r0; /* watchdog off for now */
+ ssync;
+
+ /* Code update for BSS size == 0
+ * Zero out the bss region.
+ */
+
+ p1.l = ___bss_start;
+ p1.h = ___bss_start;
+ p2.l = ___bss_stop;
+ p2.h = ___bss_stop;
+ r0 = 0;
+ p2 -= p1;
+ lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
+.L_clear_bss:
+ B[p1++] = r0;
+
+ /* In case there is a NULL pointer reference
+ * Zero out region before stext
+ */
+
+ p1.l = 0x0;
+ p1.h = 0x0;
+ r0.l = __stext;
+ r0.h = __stext;
+ r0 = r0 >> 1;
+ p2 = r0;
+ r0 = 0;
+ lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
+.L_clear_zero:
+ W[p1++] = r0;
+
+ /* pass the uboot arguments to the global value command line */
+ R0 = R7;
+ call _cmdline_init;
+
+ p1.l = __rambase;
+ p1.h = __rambase;
+ r0.l = __sdata;
+ r0.h = __sdata;
+ [p1] = r0;
+
+ p1.l = __ramstart;
+ p1.h = __ramstart;
+ p3.l = ___bss_stop;
+ p3.h = ___bss_stop;
+
+ r1 = p3;
+ [p1] = r1;
+
+
+ /*
+ * load the current thread pointer and stack
+ */
+ r1.l = _init_thread_union;
+ r1.h = _init_thread_union;
+
+ r2.l = 0x2000;
+ r2.h = 0x0000;
+ r1 = r1 + r2;
+ sp = r1;
+ usp = sp;
+ fp = sp;
+ call _start_kernel;
+.L_exit:
+ jump.s .L_exit;
+
+.section .l1.text
+#if CONFIG_BFIN_KERNEL_CLOCK
+ENTRY(_start_dma_code)
+
+ /* Enable PHY CLK buffer output */
+ p0.h = hi(VR_CTL);
+ p0.l = lo(VR_CTL);
+ r0.l = w[p0];
+ bitset(r0, 14);
+ w[p0] = r0.l;
+ ssync;
+
+ p0.h = hi(SIC_IWR);
+ p0.l = lo(SIC_IWR);
+ r0.l = 0x1;
+ r0.h = 0x0;
+ [p0] = r0;
+ SSYNC;
+
+ /*
+ * Set PLL_CTL
+ * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+ * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
+ * - [7] = output delay (add 200ps of delay to mem signals)
+ * - [6] = input delay (add 200ps of input delay to mem signals)
+ * - [5] = PDWN : 1=All Clocks off
+ * - [3] = STOPCK : 1=Core Clock off
+ * - [1] = PLL_OFF : 1=Disable Power to PLL
+ * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+ * all other bits set to zero
+ */
+
+ p0.h = hi(PLL_LOCKCNT);
+ p0.l = lo(PLL_LOCKCNT);
+ r0 = 0x300(Z);
+ w[p0] = r0.l;
+ ssync;
+
+ P2.H = hi(EBIU_SDGCTL);
+ P2.L = lo(EBIU_SDGCTL);
+ R0 = [P2];
+ BITSET (R0, 24);
+ [P2] = R0;
+ SSYNC;
+
+ r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
+ r0 = r0 << 9; /* Shift it over, */
+ r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
+ r0 = r1 | r0;
+ r1 = PLL_BYPASS; /* Bypass the PLL? */
+ r1 = r1 << 8; /* Shift it over */
+ r0 = r1 | r0; /* add them all together */
+
+ p0.h = hi(PLL_CTL);
+ p0.l = lo(PLL_CTL); /* Load the address */
+ cli r2; /* Disable interrupts */
+ ssync;
+ w[p0] = r0.l; /* Set the value */
+ idle; /* Wait for the PLL to stablize */
+ sti r2; /* Enable interrupts */
+
+.Lcheck_again:
+ p0.h = hi(PLL_STAT);
+ p0.l = lo(PLL_STAT);
+ R0 = W[P0](Z);
+ CC = BITTST(R0,5);
+ if ! CC jump .Lcheck_again;
+
+ /* Configure SCLK & CCLK Dividers */
+ r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+ p0.h = hi(PLL_DIV);
+ p0.l = lo(PLL_DIV);
+ w[p0] = r0.l;
+ ssync;
+
+ p0.l = lo(EBIU_SDRRC);
+ p0.h = hi(EBIU_SDRRC);
+ r0 = mem_SDRRC;
+ w[p0] = r0.l;
+ ssync;
+
+ p0.l = (EBIU_SDBCTL & 0xFFFF);
+ p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
+ r0 = mem_SDBCTL;
+ w[p0] = r0.l;
+ ssync;
+
+ P2.H = hi(EBIU_SDGCTL);
+ P2.L = lo(EBIU_SDGCTL);
+ R0 = [P2];
+ BITCLR (R0, 24);
+ p0.h = hi(EBIU_SDSTAT);
+ p0.l = lo(EBIU_SDSTAT);
+ r2.l = w[p0];
+ cc = bittst(r2,3);
+ if !cc jump .Lskip;
+ NOP;
+ BITSET (R0, 23);
+.Lskip:
+ [P2] = R0;
+ SSYNC;
+
+ R0.L = lo(mem_SDGCTL);
+ R0.H = hi(mem_SDGCTL);
+ R1 = [p2];
+ R1 = R1 | R0;
+ [P2] = R1;
+ SSYNC;
+
+ p0.h = hi(SIC_IWR);
+ p0.l = lo(SIC_IWR);
+ r0.l = lo(IWR_ENABLE_ALL);
+ r0.h = hi(IWR_ENABLE_ALL);
+ [p0] = r0;
+ SSYNC;
+
+ RTS;
+#endif /* CONFIG_BFIN_KERNEL_CLOCK */
+
+ENTRY(_bfin_reset)
+ /* No more interrupts to be handled*/
+ CLI R6;
+ SSYNC;
+
+#if defined(CONFIG_MTD_M25P80)
+/*
+ * The following code fix the SPI flash reboot issue,
+ * /CS signal of the chip which is using PF10 return to GPIO mode
+ */
+ p0.h = hi(PORTF_FER);
+ p0.l = lo(PORTF_FER);
+ r0.l = 0x0000;
+ w[p0] = r0.l;
+ SSYNC;
+
+/* /CS return to high */
+ p0.h = hi(PORTFIO);
+ p0.l = lo(PORTFIO);
+ r0.l = 0xFFFF;
+ w[p0] = r0.l;
+ SSYNC;
+
+/* Delay some time, This is necessary */
+ r1.h = 0;
+ r1.l = 0x400;
+ p1 = r1;
+ lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1;
+_delay_lab1:
+ r0.h = 0;
+ r0.l = 0x8000;
+ p0 = r0;
+ lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0;
+_delay_lab0:
+ nop;
+_delay_lab0_end:
+ nop;
+_delay_lab1_end:
+ nop;
+#endif
+
+ /* Clear the bits 13-15 in SWRST if they werent cleared */
+ p0.h = hi(SWRST);
+ p0.l = lo(SWRST);
+ csync;
+ r0.l = w[p0];
+
+ /* Clear the IMASK register */
+ p0.h = hi(IMASK);
+ p0.l = lo(IMASK);
+ r0 = 0x0;
+ [p0] = r0;
+
+ /* Clear the ILAT register */
+ p0.h = hi(ILAT);
+ p0.l = lo(ILAT);
+ r0 = [p0];
+ [p0] = r0;
+ SSYNC;
+
+ /* Disable the WDOG TIMER */
+ p0.h = hi(WDOG_CTL);
+ p0.l = lo(WDOG_CTL);
+ r0.l = 0xAD6;
+ w[p0] = r0.l;
+ SSYNC;
+
+ /* Clear the sticky bit incase it is already set */
+ p0.h = hi(WDOG_CTL);
+ p0.l = lo(WDOG_CTL);
+ r0.l = 0x8AD6;
+ w[p0] = r0.l;
+ SSYNC;
+
+ /* Program the count value */
+ R0.l = 0x100;
+ R0.h = 0x0;
+ P0.h = hi(WDOG_CNT);
+ P0.l = lo(WDOG_CNT);
+ [P0] = R0;
+ SSYNC;
+
+ /* Program WDOG_STAT if necessary */
+ P0.h = hi(WDOG_CTL);
+ P0.l = lo(WDOG_CTL);
+ R0 = W[P0](Z);
+ CC = BITTST(R0,1);
+ if !CC JUMP .LWRITESTAT;
+ CC = BITTST(R0,2);
+ if !CC JUMP .LWRITESTAT;
+ JUMP .LSKIP_WRITE;
+
+.LWRITESTAT:
+ /* When watch dog timer is enabled,
+ * a write to STAT will load the contents of CNT to STAT
+ */
+ R0 = 0x0000(z);
+ P0.h = hi(WDOG_STAT);
+ P0.l = lo(WDOG_STAT)
+ [P0] = R0;
+ SSYNC;
+
+.LSKIP_WRITE:
+ /* Enable the reset event */
+ P0.h = hi(WDOG_CTL);
+ P0.l = lo(WDOG_CTL);
+ R0 = W[P0](Z);
+ BITCLR(R0,1);
+ BITCLR(R0,2);
+ W[P0] = R0.L;
+ SSYNC;
+ NOP;
+
+ /* Enable the wdog counter */
+ R0 = W[P0](Z);
+ BITCLR(R0,4);
+ W[P0] = R0.L;
+ SSYNC;
+
+ IDLE;
+
+ RTS;
+
+.data
+
+/*
+ * Set up the usable of RAM stuff. Size of RAM is determined then
+ * an initial stack set up at the end.
+ */
+
+.align 4
+__rambase:
+.long 0
+__ramstart:
+.long 0
+__ramend:
+.long 0
--- /dev/null
+/*
+ * File: arch/blackfin/mach-bf537/ints-priority.c
+ * Based on: arch/blackfin/mach-bf533/ints-priority.c
+ * Author: Michael Hennerich
+ *
+ * Created:
+ * Description: Set up the interupt priorities
+ *
+ * Modified:
+ * Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/module.h>
+#include <asm/blackfin.h>
+#include <asm/irq.h>
+
+void program_IAR(void)
+{
+ /* Program the IAR0 Register with the configured priority */
+ bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
+ ((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) |
+ ((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) |
+ ((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) |
+ ((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) |
+ ((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) |
+ ((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) |
+ ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
+
+ bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) |
+ ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
+ ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
+ ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
+ ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
+ ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
+ ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
+ ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
+
+ bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
+ ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
+ ((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) |
+ ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
+ ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
+ ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
+ ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS));
+
+ bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
+ ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
+ ((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) |
+ ((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) |
+ ((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) |
+ ((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) |
+ ((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) |
+ ((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS));
+
+ bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) |
+ ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
+ ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
+ ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
+ ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
+ ((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) |
+ ((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) |
+ ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
+
+ bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
+ ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
+ ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
+ ((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) |
+ ((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) |
+ ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
+ ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
+ ((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS));
+
+ bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) |
+ ((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) |
+ ((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) |
+ ((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) |
+ ((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) |
+ ((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) |
+ ((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) |
+ ((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS));
+
+ bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) |
+ ((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) |
+ ((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) |
+ ((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) |
+ ((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) |
+ ((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) |
+ ((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS));
+
+ bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) |
+ ((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) |
+ ((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) |
+ ((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) |
+ ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
+ ((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) |
+ ((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) |
+ ((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS));
+
+ bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) |
+ ((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) |
+ ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
+ ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
+ ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
+ ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) |
+ ((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS));
+
+ bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
+ ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS));
+
+ bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
+ ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
+ ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
+ ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
+ ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
+ ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
+ ((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) |
+ ((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS));
+
+ SSYNC();
+}
extra-y := head.o
-obj-y := ints-priority.o
+obj-y := ints-priority.o dma.o
obj-$(CONFIG_BF561_COREB) += coreb.o
--- /dev/null
+/*
+ * File: arch/blackfin/mach-bf561/dma.c
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description: This file contains the simple DMA Implementation for Blackfin
+ *
+ * Modified:
+ * Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <asm/blackfin.h>
+#include <asm/dma.h>
+
+struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+ (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
+ (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
+ (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
+ (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
+ (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
+ (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
+ (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
+ (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
+};
+
+int channel2irq(unsigned int channel)
+{
+ int ret_irq = -1;
+
+ switch (channel) {
+ case CH_PPI0:
+ ret_irq = IRQ_PPI0;
+ break;
+ case CH_PPI1:
+ ret_irq = IRQ_PPI1;
+ break;
+ case CH_SPORT0_RX:
+ ret_irq = IRQ_SPORT0_RX;
+ break;
+ case CH_SPORT0_TX:
+ ret_irq = IRQ_SPORT0_TX;
+ break;
+ case CH_SPORT1_RX:
+ ret_irq = IRQ_SPORT1_RX;
+ break;
+ case CH_SPORT1_TX:
+ ret_irq = IRQ_SPORT1_TX;
+ break;
+ case CH_SPI:
+ ret_irq = IRQ_SPI;
+ break;
+ case CH_UART_RX:
+ ret_irq = IRQ_UART_RX;
+ break;
+ case CH_UART_TX:
+ ret_irq = IRQ_UART_TX;
+ break;
+
+ case CH_MEM_STREAM0_SRC:
+ case CH_MEM_STREAM0_DEST:
+ ret_irq = IRQ_MEM_DMA0;
+ break;
+ case CH_MEM_STREAM1_SRC:
+ case CH_MEM_STREAM1_DEST:
+ ret_irq = IRQ_MEM_DMA1;
+ break;
+ case CH_MEM_STREAM2_SRC:
+ case CH_MEM_STREAM2_DEST:
+ ret_irq = IRQ_MEM_DMA2;
+ break;
+ case CH_MEM_STREAM3_SRC:
+ case CH_MEM_STREAM3_DEST:
+ ret_irq = IRQ_MEM_DMA3;
+ break;
+
+ case CH_IMEM_STREAM0_SRC:
+ case CH_IMEM_STREAM0_DEST:
+ ret_irq = IRQ_IMEM_DMA0;
+ break;
+ case CH_IMEM_STREAM1_SRC:
+ case CH_IMEM_STREAM1_DEST:
+ ret_irq = IRQ_IMEM_DMA1;
+ break;
+ }
+ return ret_irq;
+}
obj-y := \
cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \
- interrupt.o lock.o dpmc.o irqpanic.o
+ interrupt.o lock.o irqpanic.o
obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o
-obj-$(CONFIG_PM) += pm.o
+obj-$(CONFIG_PM) += pm.o dpmc.o
* 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
* 2003 Metrowerks/Motorola
* 2003 Bas Vermeulen <bas@buyways.nl>
- * Copyright 2004-2006 Analog Devices Inc.
+ * Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
struct ivgx {
/* irq number for request_irq, available in mach-bf533/irq.h */
- int irqno;
+ unsigned int irqno;
/* corresponding bit in the SIC_ISR register */
- int isrflag;
+ unsigned int isrflag;
} ivg_table[NR_PERI_INTS];
struct ivg_slice {
bfin_read32((unsigned long *) SIC_IAR0 +
(irqn >> 3)) >> iar_shift)) {
ivg_table[irq_pos].irqno = IVG7 + irqn;
- ivg_table[irq_pos].isrflag = 1 << irqn;
+ ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
ivg7_13[ivg].istop++;
irq_pos++;
}
static void bfin_internal_mask_irq(unsigned int irq)
{
+#ifndef CONFIG_BF54x
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
~(1 << (irq - (IRQ_CORETMR + 1))));
+#else
+ unsigned mask_bank, mask_bit;
+ mask_bank = (irq - (IRQ_CORETMR +1))/32;
+ mask_bit = (irq - (IRQ_CORETMR + 1))%32;
+ bfin_write_SIC_IMASK( mask_bank, bfin_read_SIC_IMASK(mask_bank) & \
+ ~(1 << mask_bit));
+#endif
SSYNC();
}
static void bfin_internal_unmask_irq(unsigned int irq)
{
+#ifndef CONFIG_BF54x
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
(1 << (irq - (IRQ_CORETMR + 1))));
+#else
+ unsigned mask_bank, mask_bit;
+ mask_bank = (irq - (IRQ_CORETMR +1))/32;
+ mask_bit = (irq - (IRQ_CORETMR + 1))%32;
+ bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | \
+ ( 1 << mask_bit));
+#endif
SSYNC();
}
int irq;
unsigned long ilat = 0;
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */
+#ifdef CONFIG_BF54x
+ bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
+ bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
+ bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
+#else
bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
+#endif
+
SSYNC();
local_irq_disable();
} else {
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
- unsigned long sic_status;
+#ifdef CONFIG_BF54x
+ unsigned long sic_status[3];
+ SSYNC();
+ sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
+ sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
+ sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
+ SSYNC();
+ for(;; ivg++) {
+ if (ivg >= ivg_stop) {
+ atomic_inc(&num_spurious);
+ return;
+ }
+ if (sic_status[(ivg->irqno - IVG7)/32] & ivg->isrflag)
+ break;
+ }
+#else
+ unsigned long sic_status;
SSYNC();
sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
} else if (sic_status & ivg->isrflag)
break;
}
+#endif
vec = ivg->irqno;
}
asm_do_IRQ(vec, fp);
#endif
+#ifdef BF548_FAMILY
+#include <asm-blackfin/mach-bf548/gpio.h>
+#endif
+
#ifdef BF561_FAMILY
#define MAX_BLACKFIN_GPIOS 48
#define PORT_FIO0 GPIO_0
unsigned short get_gpiop_maskb(unsigned short);
unsigned short get_gpiop_data(unsigned short);
+#ifndef BF548_FAMILY
struct gpio_port_t {
unsigned short data;
unsigned short dummy1;
unsigned short dummy16;
unsigned short inen;
};
+#endif
#ifdef CONFIG_PM
#define PM_WAKE_RISING 0x1
#define CH_MEM_STREAM1_DEST 10 /* TX */
#define CH_MEM_STREAM1_SRC 11 /* RX */
+extern int channel2irq(unsigned int channel);
+extern struct dma_register *base_addr[];
+
#endif
#define CH_MEM_STREAM1_DEST 14 /* TX */
#define CH_MEM_STREAM1_SRC 15 /* RX */
+extern int channel2irq(unsigned int channel);
+extern struct dma_register *base_addr[];
+
#endif
SPORT external receive and transmit clocks. */
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
VDDint <=0.9V */
+#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
+ not restored */
#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
Boundary of Reserved Memory */
#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and
#ifndef __MACH_BF548_H__
#define __MACH_BF548_H__
+#define SUPPORTED_REVID 0
+
/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
#include <linux/serial.h>
#include <asm/dma.h>
-#define NR_PORTS 2
+#define NR_PORTS 4
-#define OFFSET_THR 0x00 /* Transmit Holding register */
-#define OFFSET_RBR 0x00 /* Receive Buffer register */
#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-#define OFFSET_IER 0x04 /* Interrupt Enable Register */
#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
+#define OFFSET_GCTL 0x08 /* Global Control Register */
#define OFFSET_LCR 0x0C /* Line Control Register */
#define OFFSET_MCR 0x10 /* Modem Control Register */
#define OFFSET_LSR 0x14 /* Line Status Register */
#define OFFSET_MSR 0x18 /* Modem Status Register */
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
-#define OFFSET_GCTL 0x24 /* Global Control Register */
+#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
+#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
+#define OFFSET_THR 0x28 /* Transmit Holding register */
+#define OFFSET_RBR 0x2C /* Receive Buffer register */
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
+#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
+#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
+#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
CH_UART1_TX,
CH_UART1_RX,
#endif
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- CONFIG_UART1_CTS_PIN,
- CONFIG_UART1_RTS_PIN,
+ },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART2
+ {
+ 0xFFC02100,
+ IRQ_UART2_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+ CH_UART2_TX,
+ CH_UART2_RX,
+#endif
+#ifdef CONFIG_BFIN_UART2_CTSRTS
+ CONFIG_UART2_CTS_PIN,
+ CONFIG_UART2_RTS_PIN,
+#endif
+ },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART3
+ {
+ 0xFFC03100,
+ IRQ_UART3_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+ CH_UART3_TX,
+ CH_UART3_RX,
#endif
},
#endif
static void bfin_serial_hw_init(struct bfin_serial_port *uart)
{
- unsigned short val;
- val = bfin_read16(BFIN_PORT_MUX);
- val &= ~(PFDE | PFTE);
- bfin_write16(BFIN_PORT_MUX, val);
+#ifdef CONFIG_SERIAL_BFIN_UART0
+ /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */
+ bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER());
+ bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX());
+#endif
+
+#ifdef CONFIG_SERIAL_BFIN_UART1
+ /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */
+ bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER());
+ bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX());
+#ifdef CONFIG_BFIN_UART1_CTSRTS
+ /* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */
+ bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER());
+ bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX());
+#endif
+#endif
- val = bfin_read16(PORTF_FER);
- val |= 0xF;
- bfin_write16(PORTF_FER, val);
+#ifdef CONFIG_SERIAL_BFIN_UART2
+ /* Enable UART2 RX and TX on pin 4 & 5 of PORT B */
+ bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER());
+ bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX());
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART3
+ /* Enable UART3 RX and TX on pin 6 & 7 of PORT B */
+ bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER());
+ bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX());
+#ifdef CONFIG_BFIN_UART3_CTSRTS
+ /* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */
+ bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER());
+ bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX());
+#endif
+#endif
+ SSYNC();
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
if (uart->cts_pin >= 0) {
gpio_request(uart->cts_pin, NULL);
#define BF548_FAMILY
+#include "bf548.h"
+#include "mem_map.h"
+#include "anomaly.h"
+
#ifdef CONFIG_BF542
-#include "bf542.h"
+#include "defBF542.h"
+#endif
#ifdef CONFIG_BF544
-#include "bf544.h"
+#include "defBF544.h"
#endif
#ifdef CONFIG_BF548
-#include "bf548.h"
+#include "defBF548.h"
#endif
#ifdef CONFIG_BF549
-#include "bf549.h"
+#include "defBF549.h"
#endif
-#include "mem_map.h"
-#include "anomaly.h"
-
#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
#ifdef CONFIG_BF542
#include "cdefBF542.h"
#ifndef _CDEF_BF54X_H
#define _CDEF_BF54X_H
-#include <defBF54x_base.h>
+#include "defBF54x_base.h"
/* ************************************************************** */
/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
+#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
+#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
+
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
+#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
+#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
+
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR)
#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
/* MDMA Stream 1 Registers */
#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY)
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY)
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
/* Bit masks for KPAD_CTL */
#define KPAD_EN 0x1 /* Keypad Enable */
-#define nKPAD_EN 0x0
#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
#define KPAD_COLEN 0xe000 /* Column Enable Width */
/* Bit masks for KPAD_STAT */
#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
-#define nKPAD_IRQ 0x0
#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
#define KPAD_PRESSED 0x8 /* Key press current status */
-#define nKPAD_PRESSED 0x0
/* Bit masks for KPAD_SOFTEVAL */
#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
-#define nKPAD_SOFTEVAL_E 0x0
/* Bit masks for SDH_COMMAND */
#define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP 0x40 /* Response */
-#define nCMD_RSP 0x0
#define CMD_L_RSP 0x80 /* Long Response */
-#define nCMD_L_RSP 0x0
#define CMD_INT_E 0x100 /* Command Interrupt */
-#define nCMD_INT_E 0x0
#define CMD_PEND_E 0x200 /* Command Pending */
-#define nCMD_PEND_E 0x0
#define CMD_E 0x400 /* Command Enable */
-#define nCMD_E 0x0
/* Bit masks for SDH_PWR_CTL */
#define TBD 0x3c /* TBD */
#endif
#define SD_CMD_OD 0x40 /* Open Drain Output */
-#define nSD_CMD_OD 0x0
#define ROD_CTL 0x80 /* Rod Control */
-#define nROD_CTL 0x0
/* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
-#define nCLK_E 0x0
#define PWR_SV_E 0x200 /* Power Save Enable */
-#define nPWR_SV_E 0x0
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
-#define nCLKDIV_BYPASS 0x0
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
-#define nWIDE_BUS 0x0
/* Bit masks for SDH_RESP_CMD */
/* Bit masks for SDH_DATA_CTL */
#define DTX_E 0x1 /* Data Transfer Enable */
-#define nDTX_E 0x0
#define DTX_DIR 0x2 /* Data Transfer Direction */
-#define nDTX_DIR 0x0
#define DTX_MODE 0x4 /* Data Transfer Mode */
-#define nDTX_MODE 0x0
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
-#define nDTX_DMA_E 0x0
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
/* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
-#define nCMD_CRC_FAIL 0x0
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
-#define nDAT_CRC_FAIL 0x0
#define CMD_TIMEOUT 0x4 /* CMD Time Out */
-#define nCMD_TIMEOUT 0x0
#define DAT_TIMEOUT 0x8 /* Data Time Out */
-#define nDAT_TIMEOUT 0x0
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
-#define nTX_UNDERRUN 0x0
#define RX_OVERRUN 0x20 /* Receive Overrun */
-#define nRX_OVERRUN 0x0
#define CMD_RESP_END 0x40 /* CMD Response End */
-#define nCMD_RESP_END 0x0
#define CMD_SENT 0x80 /* CMD Sent */
-#define nCMD_SENT 0x0
#define DAT_END 0x100 /* Data End */
-#define nDAT_END 0x0
#define START_BIT_ERR 0x200 /* Start Bit Error */
-#define nSTART_BIT_ERR 0x0
#define DAT_BLK_END 0x400 /* Data Block End */
-#define nDAT_BLK_END 0x0
#define CMD_ACT 0x800 /* CMD Active */
-#define nCMD_ACT 0x0
#define TX_ACT 0x1000 /* Transmit Active */
-#define nTX_ACT 0x0
#define RX_ACT 0x2000 /* Receive Active */
-#define nRX_ACT 0x0
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
-#define nTX_FIFO_STAT 0x0
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
-#define nRX_FIFO_STAT 0x0
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
-#define nTX_FIFO_FULL 0x0
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
-#define nRX_FIFO_FULL 0x0
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
-#define nTX_FIFO_ZERO 0x0
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
-#define nRX_DAT_ZERO 0x0
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
-#define nTX_DAT_RDY 0x0
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
-#define nRX_FIFO_RDY 0x0
/* Bit masks for SDH_STATUS_CLR */
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
-#define nCMD_CRC_FAIL_STAT 0x0
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
-#define nDAT_CRC_FAIL_STAT 0x0
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
-#define nCMD_TIMEOUT_STAT 0x0
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
-#define nDAT_TIMEOUT_STAT 0x0
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
-#define nTX_UNDERRUN_STAT 0x0
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
-#define nRX_OVERRUN_STAT 0x0
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
-#define nCMD_RESP_END_STAT 0x0
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
-#define nCMD_SENT_STAT 0x0
#define DAT_END_STAT 0x100 /* Data End Status */
-#define nDAT_END_STAT 0x0
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
-#define nSTART_BIT_ERR_STAT 0x0
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
-#define nDAT_BLK_END_STAT 0x0
/* Bit masks for SDH_MASK0 */
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
-#define nCMD_CRC_FAIL_MASK 0x0
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
-#define nDAT_CRC_FAIL_MASK 0x0
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
-#define nCMD_TIMEOUT_MASK 0x0
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
-#define nDAT_TIMEOUT_MASK 0x0
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
-#define nTX_UNDERRUN_MASK 0x0
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
-#define nRX_OVERRUN_MASK 0x0
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
-#define nCMD_RESP_END_MASK 0x0
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
-#define nCMD_SENT_MASK 0x0
#define DAT_END_MASK 0x100 /* Data End Mask */
-#define nDAT_END_MASK 0x0
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
-#define nSTART_BIT_ERR_MASK 0x0
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
-#define nDAT_BLK_END_MASK 0x0
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
-#define nCMD_ACT_MASK 0x0
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
-#define nTX_ACT_MASK 0x0
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
-#define nRX_ACT_MASK 0x0
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
-#define nTX_FIFO_STAT_MASK 0x0
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
-#define nRX_FIFO_STAT_MASK 0x0
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
-#define nTX_FIFO_FULL_MASK 0x0
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
-#define nRX_FIFO_FULL_MASK 0x0
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
-#define nTX_FIFO_ZERO_MASK 0x0
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
-#define nRX_DAT_ZERO_MASK 0x0
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
-#define nTX_DAT_RDY_MASK 0x0
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
-#define nRX_FIFO_RDY_MASK 0x0
/* Bit masks for SDH_FIFO_CNT */
/* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
-#define nSDIO_INT_DET 0x0
#define SD_CARD_DET 0x10 /* SD Card Detect */
-#define nSD_CARD_DET 0x0
/* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
-#define nSDIO_MSK 0x0
#define SCD_MSK 0x40 /* Mask Card Detect */
-#define nSCD_MSK 0x0
/* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */
-#define nCLKS_EN 0x0
#define SD4E 0x4 /* SDIO 4-Bit Enable */
-#define nSD4E 0x0
#define MWE 0x8 /* Moving Window Enable */
-#define nMWE 0x0
#define SD_RST 0x10 /* SDMMC Reset */
-#define nSD_RST 0x0
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
-#define nPUP_SDDAT 0x0
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
-#define nPUP_SDDAT3 0x0
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
-#define nPD_SDDAT3 0x0
/* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */
-#define nRWR 0x0
/* Bit masks for ATAPI_CONTROL */
#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define nPIO_START 0x0
#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define nMULTI_START 0x0
#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define nULTRA_START 0x0
#define XFER_DIR 0x8 /* Transfer Direction */
-#define nXFER_DIR 0x0
#define IORDY_EN 0x10 /* IORDY Enable */
-#define nIORDY_EN 0x0
#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define nFIFO_FLUSH 0x0
#define SOFT_RST 0x40 /* Soft Reset */
-#define nSOFT_RST 0x0
#define DEV_RST 0x80 /* Device Reset */
-#define nDEV_RST 0x0
#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define nTFRCNT_RST 0x0
#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define nEND_ON_TERM 0x0
#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define nPIO_USE_DMA 0x0
#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
/* Bit masks for ATAPI_STATUS */
#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define nPIO_XFER_ON 0x0
#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define nMULTI_XFER_ON 0x0
#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define nULTRA_XFER_ON 0x0
#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
/* Bit masks for ATAPI_DEV_ADDR */
/* Bit masks for ATAPI_INT_MASK */
#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define nATAPI_DEV_INT_MASK 0x0
#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define nPIO_DONE_MASK 0x0
#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define nMULTI_DONE_MASK 0x0
#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define nUDMAIN_DONE_MASK 0x0
#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define nUDMAOUT_DONE_MASK 0x0
#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define nHOST_TERM_XFER_MASK 0x0
#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define nMULTI_TERM_MASK 0x0
#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define nUDMAIN_TERM_MASK 0x0
#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-#define nUDMAOUT_TERM_MASK 0x0
/* Bit masks for ATAPI_INT_STATUS */
#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define nATAPI_DEV_INT 0x0
#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define nPIO_DONE_INT 0x0
#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define nMULTI_DONE_INT 0x0
#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define nUDMAIN_DONE_INT 0x0
#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define nUDMAOUT_DONE_INT 0x0
#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define nHOST_TERM_XFER_INT 0x0
#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define nMULTI_TERM_INT 0x0
#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define nUDMAIN_TERM_INT 0x0
#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-#define nUDMAOUT_TERM_INT 0x0
/* Bit masks for ATAPI_LINE_STATUS */
#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define nATAPI_INTR 0x0
#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define nATAPI_DASP 0x0
#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define nATAPI_CS0N 0x0
#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define nATAPI_CS1N 0x0
#define ATAPI_ADDR 0x70 /* ATAPI address line status */
#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define nATAPI_DMAREQ 0x0
#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define nATAPI_DMAACKN 0x0
#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define nATAPI_DIOWN 0x0
#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define nATAPI_DIORN 0x0
#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-#define nATAPI_IORDY 0x0
/* Bit masks for ATAPI_SM_STATE */
/* Bit masks for ATAPI_TERMINATE */
#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-#define nATAPI_HOST_TERM 0x0
/* Bit masks for ATAPI_REG_TIM_0 */
/* Bit masks for USB_POWER */
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define nENABLE_SUSPENDM 0x0
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define nSUSPEND_MODE 0x0
#define RESUME_MODE 0x4 /* DMA Mode */
-#define nRESUME_MODE 0x0
#define RESET 0x8 /* Reset indicator */
-#define nRESET 0x0
#define HS_MODE 0x10 /* High Speed mode indicator */
-#define nHS_MODE 0x0
#define HS_ENABLE 0x20 /* high Speed Enable */
-#define nHS_ENABLE 0x0
#define SOFT_CONN 0x40 /* Soft connect */
-#define nSOFT_CONN 0x0
#define ISO_UPDATE 0x80 /* Isochronous update */
-#define nISO_UPDATE 0x0
/* Bit masks for USB_INTRTX */
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define nEP0_TX 0x0
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define nEP1_TX 0x0
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define nEP2_TX 0x0
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define nEP3_TX 0x0
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define nEP4_TX 0x0
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define nEP5_TX 0x0
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define nEP6_TX 0x0
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-#define nEP7_TX 0x0
/* Bit masks for USB_INTRRX */
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define nEP1_RX 0x0
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define nEP2_RX 0x0
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define nEP3_RX 0x0
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define nEP4_RX 0x0
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define nEP5_RX 0x0
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define nEP6_RX 0x0
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-#define nEP7_RX 0x0
/* Bit masks for USB_INTRTXE */
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define nEP0_TX_E 0x0
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define nEP1_TX_E 0x0
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define nEP2_TX_E 0x0
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define nEP3_TX_E 0x0
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define nEP4_TX_E 0x0
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define nEP5_TX_E 0x0
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define nEP6_TX_E 0x0
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-#define nEP7_TX_E 0x0
/* Bit masks for USB_INTRRXE */
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define nEP1_RX_E 0x0
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define nEP2_RX_E 0x0
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define nEP3_RX_E 0x0
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define nEP4_RX_E 0x0
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define nEP5_RX_E 0x0
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define nEP6_RX_E 0x0
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-#define nEP7_RX_E 0x0
/* Bit masks for USB_INTRUSB */
#define SUSPEND_B 0x1 /* Suspend indicator */
-#define nSUSPEND_B 0x0
#define RESUME_B 0x2 /* Resume indicator */
-#define nRESUME_B 0x0
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define nRESET_OR_BABLE_B 0x0
#define SOF_B 0x8 /* Start of frame */
-#define nSOF_B 0x0
#define CONN_B 0x10 /* Connection indicator */
-#define nCONN_B 0x0
#define DISCON_B 0x20 /* Disconnect indicator */
-#define nDISCON_B 0x0
#define SESSION_REQ_B 0x40 /* Session Request */
-#define nSESSION_REQ_B 0x0
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-#define nVBUS_ERROR_B 0x0
/* Bit masks for USB_INTRUSBE */
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define nSUSPEND_BE 0x0
#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define nRESUME_BE 0x0
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define nRESET_OR_BABLE_BE 0x0
#define SOF_BE 0x8 /* Start of frame int enable */
-#define nSOF_BE 0x0
#define CONN_BE 0x10 /* Connection indicator int enable */
-#define nCONN_BE 0x0
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define nDISCON_BE 0x0
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define nSESSION_REQ_BE 0x0
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-#define nVBUS_ERROR_BE 0x0
/* Bit masks for USB_FRAME */
/* Bit masks for USB_GLOBAL_CTL */
#define GLOBAL_ENA 0x1 /* enables USB module */
-#define nGLOBAL_ENA 0x0
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define nEP1_TX_ENA 0x0
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define nEP2_TX_ENA 0x0
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define nEP3_TX_ENA 0x0
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define nEP4_TX_ENA 0x0
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define nEP5_TX_ENA 0x0
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define nEP6_TX_ENA 0x0
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define nEP7_TX_ENA 0x0
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define nEP1_RX_ENA 0x0
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define nEP2_RX_ENA 0x0
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define nEP3_RX_ENA 0x0
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define nEP4_RX_ENA 0x0
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define nEP5_RX_ENA 0x0
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define nEP6_RX_ENA 0x0
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-#define nEP7_RX_ENA 0x0
/* Bit masks for USB_OTG_DEV_CTL */
#define SESSION 0x1 /* session indicator */
-#define nSESSION 0x0
#define HOST_REQ 0x2 /* Host negotiation request */
-#define nHOST_REQ 0x0
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define nHOST_MODE 0x0
#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define nVBUS0 0x0
#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define nVBUS1 0x0
#define LSDEV 0x20 /* Low-speed indicator */
-#define nLSDEV 0x0
#define FSDEV 0x40 /* Full or High-speed indicator */
-#define nFSDEV 0x0
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-#define nB_DEVICE 0x0
/* Bit masks for USB_OTG_VBUS_IRQ */
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define nDRIVE_VBUS_ON 0x0
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define nDRIVE_VBUS_OFF 0x0
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define nCHRG_VBUS_START 0x0
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define nCHRG_VBUS_END 0x0
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define nDISCHRG_VBUS_START 0x0
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-#define nDISCHRG_VBUS_END 0x0
/* Bit masks for USB_OTG_VBUS_MASK */
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define nDRIVE_VBUS_ON_ENA 0x0
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define nDRIVE_VBUS_OFF_ENA 0x0
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define nCHRG_VBUS_START_ENA 0x0
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define nCHRG_VBUS_END_ENA 0x0
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define nDISCHRG_VBUS_START_ENA 0x0
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-#define nDISCHRG_VBUS_END_ENA 0x0
/* Bit masks for USB_CSR0 */
#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define nRXPKTRDY 0x0
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define nTXPKTRDY 0x0
#define STALL_SENT 0x4 /* STALL handshake sent */
-#define nSTALL_SENT 0x0
#define DATAEND 0x8 /* Data end indicator */
-#define nDATAEND 0x0
#define SETUPEND 0x10 /* Setup end */
-#define nSETUPEND 0x0
#define SENDSTALL 0x20 /* Send STALL handshake */
-#define nSENDSTALL 0x0
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define nSERVICED_RXPKTRDY 0x0
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define nSERVICED_SETUPEND 0x0
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define nFLUSHFIFO 0x0
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define nSTALL_RECEIVED_H 0x0
#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define nSETUPPKT_H 0x0
#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define nERROR_H 0x0
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define nREQPKT_H 0x0
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define nSTATUSPKT_H 0x0
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-#define nNAK_TIMEOUT_H 0x0
/* Bit masks for USB_COUNT0 */
/* Bit masks for USB_TXCSR */
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define nTXPKTRDY_T 0x0
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define nFIFO_NOT_EMPTY_T 0x0
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define nUNDERRUN_T 0x0
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define nFLUSHFIFO_T 0x0
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define nSTALL_SEND_T 0x0
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define nSTALL_SENT_T 0x0
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_T 0x0
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define nINCOMPTX_T 0x0
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_T 0x0
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define nFORCE_DATATOGGLE_T 0x0
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_T 0x0
#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define nISO_T 0x0
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOSET_T 0x0
#define ERROR_TH 0x4 /* error condition host mode */
-#define nERROR_TH 0x0
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_TH 0x0
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-#define nNAK_TIMEOUT_TH 0x0
/* Bit masks for USB_TXCOUNT */
/* Bit masks for USB_RXCSR */
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define nRXPKTRDY_R 0x0
#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define nFIFO_FULL_R 0x0
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define nOVERRUN_R 0x0
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define nDATAERROR_R 0x0
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define nFLUSHFIFO_R 0x0
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define nSTALL_SEND_R 0x0
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define nSTALL_SENT_R 0x0
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_R 0x0
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define nINCOMPRX_R 0x0
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_R 0x0
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define nDISNYET_R 0x0
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_R 0x0
#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define nISO_R 0x0
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOCLEAR_R 0x0
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define nERROR_RH 0x0
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define nREQPKT_RH 0x0
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_RH 0x0
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define nINCOMPRX_RH 0x0
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define nDMAREQMODE_RH 0x0
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-#define nAUTOREQ_RH 0x0
/* Bit masks for USB_RXCOUNT */
/* Bit masks for USB_DMA_INTERRUPT */
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define nDMA0_INT 0x0
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define nDMA1_INT 0x0
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define nDMA2_INT 0x0
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define nDMA3_INT 0x0
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define nDMA4_INT 0x0
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define nDMA5_INT 0x0
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define nDMA6_INT 0x0
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-#define nDMA7_INT 0x0
/* Bit masks for USB_DMAxCONTROL */
#define DMA_ENA 0x1 /* DMA enable */
-#define nDMA_ENA 0x0
#define DIRECTION 0x2 /* direction of DMA transfer */
-#define nDIRECTION 0x0
#define MODE 0x4 /* DMA Bus error */
-#define nMODE 0x0
#define INT_ENA 0x8 /* Interrupt enable */
-#define nINT_ENA 0x0
#define EPNUM 0xf0 /* EP number */
#define BUSERROR 0x100 /* DMA Bus error */
-#define nBUSERROR 0x0
/* Bit masks for USB_DMAxADDRHIGH */
/* Bit masks for PIXC_CTL */
#define PIXC_EN 0x1 /* Pixel Compositor Enable */
-#define nPIXC_EN 0x0
#define OVR_A_EN 0x2 /* Overlay A Enable */
-#define nOVR_A_EN 0x0
#define OVR_B_EN 0x4 /* Overlay B Enable */
-#define nOVR_B_EN 0x0
#define IMG_FORM 0x8 /* Image Data Format */
-#define nIMG_FORM 0x0
#define OVR_FORM 0x10 /* Overlay Data Format */
-#define nOVR_FORM 0x0
#define OUT_FORM 0x20 /* Output Data Format */
-#define nOUT_FORM 0x0
#define UDS_MOD 0x40 /* Resampling Mode */
-#define nUDS_MOD 0x0
#define TC_EN 0x80 /* Transparent Color Enable */
-#define nTC_EN 0x0
#define IMG_STAT 0x300 /* Image FIFO Status */
#define OVR_STAT 0xc00 /* Overlay FIFO Status */
#define WM_LVL 0x3000 /* FIFO Watermark Level */
/* Bit masks for PIXC_INTRSTAT */
#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
-#define nOVR_INT_EN 0x0
#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
-#define nFRM_INT_EN 0x0
#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
-#define nOVR_INT_STAT 0x0
#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
-#define nFRM_INT_STAT 0x0
/* Bit masks for PIXC_RYCON */
#define A12 0xffc00 /* A12 in the Coefficient Matrix */
#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
-#define nRY_MULT4 0x0
/* Bit masks for PIXC_GUCON */
#define A22 0xffc00 /* A22 in the Coefficient Matrix */
#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
-#define nGU_MULT4 0x0
/* Bit masks for PIXC_BVCON */
#define A32 0xffc00 /* A32 in the Coefficient Matrix */
#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
-#define nBV_MULT4 0x0
/* Bit masks for PIXC_CCBIAS */
/* Bit masks for HOST_CONTROL */
#define HOST_EN 0x1 /* Host Enable */
-#define nHOST_EN 0x0
#define HOST_END 0x2 /* Host Endianess */
-#define nHOST_END 0x0
#define DATA_SIZE 0x4 /* Data Size */
-#define nDATA_SIZE 0x0
#define HOST_RST 0x8 /* Host Reset */
-#define nHOST_RST 0x0
#define HRDY_OVR 0x20 /* Host Ready Override */
-#define nHRDY_OVR 0x0
#define INT_MODE 0x40 /* Interrupt Mode */
-#define nINT_MODE 0x0
#define BT_EN 0x80 /* Bus Timeout Enable */
-#define nBT_EN 0x0
#define EHW 0x100 /* Enable Host Write */
-#define nEHW 0x0
#define EHR 0x200 /* Enable Host Read */
-#define nEHR 0x0
#define BDR 0x400 /* Burst DMA Requests */
-#define nBDR 0x0
/* Bit masks for HOST_STATUS */
#define READY 0x1 /* DMA Ready */
-#define nREADY 0x0
#define FIFOFULL 0x2 /* FIFO Full */
-#define nFIFOFULL 0x0
#define FIFOEMPTY 0x4 /* FIFO Empty */
-#define nFIFOEMPTY 0x0
#define COMPLETE 0x8 /* DMA Complete */
-#define nCOMPLETE 0x0
#define HSHK 0x10 /* Host Handshake */
-#define nHSHK 0x0
#define TIMEOUT 0x20 /* Host Timeout */
-#define nTIMEOUT 0x0
#define HIRQ 0x40 /* Host Interrupt Request */
-#define nHIRQ 0x0
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define nALLOW_CNFG 0x0
#define DMA_DIR 0x100 /* DMA Direction */
-#define nDMA_DIR 0x0
#define BTE 0x200 /* Bus Timeout Enabled */
-#define nBTE 0x0
/* Bit masks for HOST_TIMEOUT */
/* Bit masks for TIMER_ENABLE1 */
#define TIMEN8 0x1 /* Timer 8 Enable */
-#define nTIMEN8 0x0
#define TIMEN9 0x2 /* Timer 9 Enable */
-#define nTIMEN9 0x0
#define TIMEN10 0x4 /* Timer 10 Enable */
-#define nTIMEN10 0x0
/* Bit masks for TIMER_DISABLE1 */
#define TIMDIS8 0x1 /* Timer 8 Disable */
-#define nTIMDIS8 0x0
#define TIMDIS9 0x2 /* Timer 9 Disable */
-#define nTIMDIS9 0x0
#define TIMDIS10 0x4 /* Timer 10 Disable */
-#define nTIMDIS10 0x0
/* Bit masks for TIMER_STATUS1 */
#define TIMIL8 0x1 /* Timer 8 Interrupt */
-#define nTIMIL8 0x0
#define TIMIL9 0x2 /* Timer 9 Interrupt */
-#define nTIMIL9 0x0
#define TIMIL10 0x4 /* Timer 10 Interrupt */
-#define nTIMIL10 0x0
#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
-#define nTOVF_ERR8 0x0
#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
-#define nTOVF_ERR9 0x0
#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
-#define nTOVF_ERR10 0x0
#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
-#define nTRUN8 0x0
#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
-#define nTRUN9 0x0
#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
-#define nTRUN10 0x0
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
/* Bit masks for HMDMAx_CONTROL */
#define HMDMAEN 0x1 /* Handshake MDMA Enable */
-#define nHMDMAEN 0x0
#define REP 0x2 /* Handshake MDMA Request Polarity */
-#define nREP 0x0
#define UTE 0x8 /* Urgency Threshold Enable */
-#define nUTE 0x0
#define OIE 0x10 /* Overflow Interrupt Enable */
-#define nOIE 0x0
#define BDIE 0x20 /* Block Done Interrupt Enable */
-#define nBDIE 0x0
#define MBDI 0x40 /* Mask Block Done Interrupt */
-#define nMBDI 0x0
#define DRQ 0x300 /* Handshake MDMA Request Type */
#define RBC 0x1000 /* Force Reload of BCOUNT */
-#define nRBC 0x0
#define PS 0x2000 /* Pin Status */
-#define nPS 0x0
#define OI 0x4000 /* Overflow Interrupt Generated */
-#define nOI 0x0
#define BDI 0x8000 /* Block Done Interrupt Generated */
-#define nBDI 0x0
/* ******************************************* */
/* MULTI BIT MACRO ENUMERATIONS */
/* Bit masks for PIXC_CTL */
#define PIXC_EN 0x1 /* Pixel Compositor Enable */
-#define nPIXC_EN 0x0
#define OVR_A_EN 0x2 /* Overlay A Enable */
-#define nOVR_A_EN 0x0
#define OVR_B_EN 0x4 /* Overlay B Enable */
-#define nOVR_B_EN 0x0
#define IMG_FORM 0x8 /* Image Data Format */
-#define nIMG_FORM 0x0
#define OVR_FORM 0x10 /* Overlay Data Format */
-#define nOVR_FORM 0x0
#define OUT_FORM 0x20 /* Output Data Format */
-#define nOUT_FORM 0x0
#define UDS_MOD 0x40 /* Resampling Mode */
-#define nUDS_MOD 0x0
#define TC_EN 0x80 /* Transparent Color Enable */
-#define nTC_EN 0x0
#define IMG_STAT 0x300 /* Image FIFO Status */
#define OVR_STAT 0xc00 /* Overlay FIFO Status */
#define WM_LVL 0x3000 /* FIFO Watermark Level */
/* Bit masks for PIXC_INTRSTAT */
#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
-#define nOVR_INT_EN 0x0
#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
-#define nFRM_INT_EN 0x0
#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
-#define nOVR_INT_STAT 0x0
#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
-#define nFRM_INT_STAT 0x0
/* Bit masks for PIXC_RYCON */
#define A12 0xffc00 /* A12 in the Coefficient Matrix */
#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
-#define nRY_MULT4 0x0
/* Bit masks for PIXC_GUCON */
#define A22 0xffc00 /* A22 in the Coefficient Matrix */
#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
-#define nGU_MULT4 0x0
/* Bit masks for PIXC_BVCON */
#define A32 0xffc00 /* A32 in the Coefficient Matrix */
#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
-#define nBV_MULT4 0x0
/* Bit masks for PIXC_CCBIAS */
/* Bit masks for HOST_CONTROL */
#define HOST_EN 0x1 /* Host Enable */
-#define nHOST_EN 0x0
#define HOST_END 0x2 /* Host Endianess */
-#define nHOST_END 0x0
#define DATA_SIZE 0x4 /* Data Size */
-#define nDATA_SIZE 0x0
#define HOST_RST 0x8 /* Host Reset */
-#define nHOST_RST 0x0
#define HRDY_OVR 0x20 /* Host Ready Override */
-#define nHRDY_OVR 0x0
#define INT_MODE 0x40 /* Interrupt Mode */
-#define nINT_MODE 0x0
#define BT_EN 0x80 /* Bus Timeout Enable */
-#define nBT_EN 0x0
#define EHW 0x100 /* Enable Host Write */
-#define nEHW 0x0
#define EHR 0x200 /* Enable Host Read */
-#define nEHR 0x0
#define BDR 0x400 /* Burst DMA Requests */
-#define nBDR 0x0
/* Bit masks for HOST_STATUS */
#define READY 0x1 /* DMA Ready */
-#define nREADY 0x0
#define FIFOFULL 0x2 /* FIFO Full */
-#define nFIFOFULL 0x0
#define FIFOEMPTY 0x4 /* FIFO Empty */
-#define nFIFOEMPTY 0x0
#define COMPLETE 0x8 /* DMA Complete */
-#define nCOMPLETE 0x0
#define HSHK 0x10 /* Host Handshake */
-#define nHSHK 0x0
#define TIMEOUT 0x20 /* Host Timeout */
-#define nTIMEOUT 0x0
#define HIRQ 0x40 /* Host Interrupt Request */
-#define nHIRQ 0x0
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define nALLOW_CNFG 0x0
#define DMA_DIR 0x100 /* DMA Direction */
-#define nDMA_DIR 0x0
#define BTE 0x200 /* Bus Timeout Enabled */
-#define nBTE 0x0
/* Bit masks for HOST_TIMEOUT */
/* Bit masks for KPAD_CTL */
#define KPAD_EN 0x1 /* Keypad Enable */
-#define nKPAD_EN 0x0
#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
#define KPAD_COLEN 0xe000 /* Column Enable Width */
/* Bit masks for KPAD_STAT */
#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
-#define nKPAD_IRQ 0x0
#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
#define KPAD_PRESSED 0x8 /* Key press current status */
-#define nKPAD_PRESSED 0x0
/* Bit masks for KPAD_SOFTEVAL */
#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
-#define nKPAD_SOFTEVAL_E 0x0
/* Bit masks for SDH_COMMAND */
#define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP 0x40 /* Response */
-#define nCMD_RSP 0x0
#define CMD_L_RSP 0x80 /* Long Response */
-#define nCMD_L_RSP 0x0
#define CMD_INT_E 0x100 /* Command Interrupt */
-#define nCMD_INT_E 0x0
#define CMD_PEND_E 0x200 /* Command Pending */
-#define nCMD_PEND_E 0x0
#define CMD_E 0x400 /* Command Enable */
-#define nCMD_E 0x0
/* Bit masks for SDH_PWR_CTL */
#define TBD 0x3c /* TBD */
#endif
#define SD_CMD_OD 0x40 /* Open Drain Output */
-#define nSD_CMD_OD 0x0
#define ROD_CTL 0x80 /* Rod Control */
-#define nROD_CTL 0x0
/* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
-#define nCLK_E 0x0
#define PWR_SV_E 0x200 /* Power Save Enable */
-#define nPWR_SV_E 0x0
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
-#define nCLKDIV_BYPASS 0x0
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
-#define nWIDE_BUS 0x0
/* Bit masks for SDH_RESP_CMD */
/* Bit masks for SDH_DATA_CTL */
#define DTX_E 0x1 /* Data Transfer Enable */
-#define nDTX_E 0x0
#define DTX_DIR 0x2 /* Data Transfer Direction */
-#define nDTX_DIR 0x0
#define DTX_MODE 0x4 /* Data Transfer Mode */
-#define nDTX_MODE 0x0
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
-#define nDTX_DMA_E 0x0
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
/* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
-#define nCMD_CRC_FAIL 0x0
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
-#define nDAT_CRC_FAIL 0x0
#define CMD_TIMEOUT 0x4 /* CMD Time Out */
-#define nCMD_TIMEOUT 0x0
#define DAT_TIMEOUT 0x8 /* Data Time Out */
-#define nDAT_TIMEOUT 0x0
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
-#define nTX_UNDERRUN 0x0
#define RX_OVERRUN 0x20 /* Receive Overrun */
-#define nRX_OVERRUN 0x0
#define CMD_RESP_END 0x40 /* CMD Response End */
-#define nCMD_RESP_END 0x0
#define CMD_SENT 0x80 /* CMD Sent */
-#define nCMD_SENT 0x0
#define DAT_END 0x100 /* Data End */
-#define nDAT_END 0x0
#define START_BIT_ERR 0x200 /* Start Bit Error */
-#define nSTART_BIT_ERR 0x0
#define DAT_BLK_END 0x400 /* Data Block End */
-#define nDAT_BLK_END 0x0
#define CMD_ACT 0x800 /* CMD Active */
-#define nCMD_ACT 0x0
#define TX_ACT 0x1000 /* Transmit Active */
-#define nTX_ACT 0x0
#define RX_ACT 0x2000 /* Receive Active */
-#define nRX_ACT 0x0
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
-#define nTX_FIFO_STAT 0x0
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
-#define nRX_FIFO_STAT 0x0
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
-#define nTX_FIFO_FULL 0x0
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
-#define nRX_FIFO_FULL 0x0
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
-#define nTX_FIFO_ZERO 0x0
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
-#define nRX_DAT_ZERO 0x0
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
-#define nTX_DAT_RDY 0x0
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
-#define nRX_FIFO_RDY 0x0
/* Bit masks for SDH_STATUS_CLR */
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
-#define nCMD_CRC_FAIL_STAT 0x0
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
-#define nDAT_CRC_FAIL_STAT 0x0
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
-#define nCMD_TIMEOUT_STAT 0x0
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
-#define nDAT_TIMEOUT_STAT 0x0
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
-#define nTX_UNDERRUN_STAT 0x0
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
-#define nRX_OVERRUN_STAT 0x0
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
-#define nCMD_RESP_END_STAT 0x0
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
-#define nCMD_SENT_STAT 0x0
#define DAT_END_STAT 0x100 /* Data End Status */
-#define nDAT_END_STAT 0x0
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
-#define nSTART_BIT_ERR_STAT 0x0
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
-#define nDAT_BLK_END_STAT 0x0
/* Bit masks for SDH_MASK0 */
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
-#define nCMD_CRC_FAIL_MASK 0x0
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
-#define nDAT_CRC_FAIL_MASK 0x0
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
-#define nCMD_TIMEOUT_MASK 0x0
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
-#define nDAT_TIMEOUT_MASK 0x0
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
-#define nTX_UNDERRUN_MASK 0x0
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
-#define nRX_OVERRUN_MASK 0x0
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
-#define nCMD_RESP_END_MASK 0x0
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
-#define nCMD_SENT_MASK 0x0
#define DAT_END_MASK 0x100 /* Data End Mask */
-#define nDAT_END_MASK 0x0
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
-#define nSTART_BIT_ERR_MASK 0x0
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
-#define nDAT_BLK_END_MASK 0x0
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
-#define nCMD_ACT_MASK 0x0
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
-#define nTX_ACT_MASK 0x0
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
-#define nRX_ACT_MASK 0x0
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
-#define nTX_FIFO_STAT_MASK 0x0
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
-#define nRX_FIFO_STAT_MASK 0x0
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
-#define nTX_FIFO_FULL_MASK 0x0
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
-#define nRX_FIFO_FULL_MASK 0x0
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
-#define nTX_FIFO_ZERO_MASK 0x0
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
-#define nRX_DAT_ZERO_MASK 0x0
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
-#define nTX_DAT_RDY_MASK 0x0
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
-#define nRX_FIFO_RDY_MASK 0x0
/* Bit masks for SDH_FIFO_CNT */
/* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
-#define nSDIO_INT_DET 0x0
#define SD_CARD_DET 0x10 /* SD Card Detect */
-#define nSD_CARD_DET 0x0
/* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
-#define nSDIO_MSK 0x0
#define SCD_MSK 0x40 /* Mask Card Detect */
-#define nSCD_MSK 0x0
/* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */
-#define nCLKS_EN 0x0
#define SD4E 0x4 /* SDIO 4-Bit Enable */
-#define nSD4E 0x0
#define MWE 0x8 /* Moving Window Enable */
-#define nMWE 0x0
#define SD_RST 0x10 /* SDMMC Reset */
-#define nSD_RST 0x0
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
-#define nPUP_SDDAT 0x0
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
-#define nPUP_SDDAT3 0x0
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
-#define nPD_SDDAT3 0x0
/* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */
-#define nRWR 0x0
/* Bit masks for ATAPI_CONTROL */
#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define nPIO_START 0x0
#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define nMULTI_START 0x0
#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define nULTRA_START 0x0
#define XFER_DIR 0x8 /* Transfer Direction */
-#define nXFER_DIR 0x0
#define IORDY_EN 0x10 /* IORDY Enable */
-#define nIORDY_EN 0x0
#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define nFIFO_FLUSH 0x0
#define SOFT_RST 0x40 /* Soft Reset */
-#define nSOFT_RST 0x0
#define DEV_RST 0x80 /* Device Reset */
-#define nDEV_RST 0x0
#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define nTFRCNT_RST 0x0
#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define nEND_ON_TERM 0x0
#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define nPIO_USE_DMA 0x0
#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
/* Bit masks for ATAPI_STATUS */
#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define nPIO_XFER_ON 0x0
#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define nMULTI_XFER_ON 0x0
#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define nULTRA_XFER_ON 0x0
#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
/* Bit masks for ATAPI_DEV_ADDR */
/* Bit masks for ATAPI_INT_MASK */
#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define nATAPI_DEV_INT_MASK 0x0
#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define nPIO_DONE_MASK 0x0
#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define nMULTI_DONE_MASK 0x0
#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define nUDMAIN_DONE_MASK 0x0
#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define nUDMAOUT_DONE_MASK 0x0
#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define nHOST_TERM_XFER_MASK 0x0
#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define nMULTI_TERM_MASK 0x0
#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define nUDMAIN_TERM_MASK 0x0
#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-#define nUDMAOUT_TERM_MASK 0x0
/* Bit masks for ATAPI_INT_STATUS */
#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define nATAPI_DEV_INT 0x0
#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define nPIO_DONE_INT 0x0
#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define nMULTI_DONE_INT 0x0
#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define nUDMAIN_DONE_INT 0x0
#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define nUDMAOUT_DONE_INT 0x0
#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define nHOST_TERM_XFER_INT 0x0
#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define nMULTI_TERM_INT 0x0
#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define nUDMAIN_TERM_INT 0x0
#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-#define nUDMAOUT_TERM_INT 0x0
/* Bit masks for ATAPI_LINE_STATUS */
#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define nATAPI_INTR 0x0
#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define nATAPI_DASP 0x0
#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define nATAPI_CS0N 0x0
#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define nATAPI_CS1N 0x0
#define ATAPI_ADDR 0x70 /* ATAPI address line status */
#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define nATAPI_DMAREQ 0x0
#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define nATAPI_DMAACKN 0x0
#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define nATAPI_DIOWN 0x0
#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define nATAPI_DIORN 0x0
#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-#define nATAPI_IORDY 0x0
/* Bit masks for ATAPI_SM_STATE */
/* Bit masks for ATAPI_TERMINATE */
#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-#define nATAPI_HOST_TERM 0x0
/* Bit masks for ATAPI_REG_TIM_0 */
/* Bit masks for TIMER_ENABLE1 */
#define TIMEN8 0x1 /* Timer 8 Enable */
-#define nTIMEN8 0x0
#define TIMEN9 0x2 /* Timer 9 Enable */
-#define nTIMEN9 0x0
#define TIMEN10 0x4 /* Timer 10 Enable */
-#define nTIMEN10 0x0
/* Bit masks for TIMER_DISABLE1 */
#define TIMDIS8 0x1 /* Timer 8 Disable */
-#define nTIMDIS8 0x0
#define TIMDIS9 0x2 /* Timer 9 Disable */
-#define nTIMDIS9 0x0
#define TIMDIS10 0x4 /* Timer 10 Disable */
-#define nTIMDIS10 0x0
/* Bit masks for TIMER_STATUS1 */
#define TIMIL8 0x1 /* Timer 8 Interrupt */
-#define nTIMIL8 0x0
#define TIMIL9 0x2 /* Timer 9 Interrupt */
-#define nTIMIL9 0x0
#define TIMIL10 0x4 /* Timer 10 Interrupt */
-#define nTIMIL10 0x0
#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
-#define nTOVF_ERR8 0x0
#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
-#define nTOVF_ERR9 0x0
#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
-#define nTOVF_ERR10 0x0
#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
-#define nTRUN8 0x0
#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
-#define nTRUN9 0x0
#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
-#define nTRUN10 0x0
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
/* Bit masks for USB_POWER */
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define nENABLE_SUSPENDM 0x0
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define nSUSPEND_MODE 0x0
#define RESUME_MODE 0x4 /* DMA Mode */
-#define nRESUME_MODE 0x0
#define RESET 0x8 /* Reset indicator */
-#define nRESET 0x0
#define HS_MODE 0x10 /* High Speed mode indicator */
-#define nHS_MODE 0x0
#define HS_ENABLE 0x20 /* high Speed Enable */
-#define nHS_ENABLE 0x0
#define SOFT_CONN 0x40 /* Soft connect */
-#define nSOFT_CONN 0x0
#define ISO_UPDATE 0x80 /* Isochronous update */
-#define nISO_UPDATE 0x0
/* Bit masks for USB_INTRTX */
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define nEP0_TX 0x0
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define nEP1_TX 0x0
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define nEP2_TX 0x0
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define nEP3_TX 0x0
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define nEP4_TX 0x0
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define nEP5_TX 0x0
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define nEP6_TX 0x0
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-#define nEP7_TX 0x0
/* Bit masks for USB_INTRRX */
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define nEP1_RX 0x0
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define nEP2_RX 0x0
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define nEP3_RX 0x0
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define nEP4_RX 0x0
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define nEP5_RX 0x0
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define nEP6_RX 0x0
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-#define nEP7_RX 0x0
/* Bit masks for USB_INTRTXE */
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define nEP0_TX_E 0x0
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define nEP1_TX_E 0x0
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define nEP2_TX_E 0x0
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define nEP3_TX_E 0x0
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define nEP4_TX_E 0x0
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define nEP5_TX_E 0x0
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define nEP6_TX_E 0x0
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-#define nEP7_TX_E 0x0
/* Bit masks for USB_INTRRXE */
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define nEP1_RX_E 0x0
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define nEP2_RX_E 0x0
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define nEP3_RX_E 0x0
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define nEP4_RX_E 0x0
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define nEP5_RX_E 0x0
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define nEP6_RX_E 0x0
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-#define nEP7_RX_E 0x0
/* Bit masks for USB_INTRUSB */
#define SUSPEND_B 0x1 /* Suspend indicator */
-#define nSUSPEND_B 0x0
#define RESUME_B 0x2 /* Resume indicator */
-#define nRESUME_B 0x0
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define nRESET_OR_BABLE_B 0x0
#define SOF_B 0x8 /* Start of frame */
-#define nSOF_B 0x0
#define CONN_B 0x10 /* Connection indicator */
-#define nCONN_B 0x0
#define DISCON_B 0x20 /* Disconnect indicator */
-#define nDISCON_B 0x0
#define SESSION_REQ_B 0x40 /* Session Request */
-#define nSESSION_REQ_B 0x0
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-#define nVBUS_ERROR_B 0x0
/* Bit masks for USB_INTRUSBE */
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define nSUSPEND_BE 0x0
#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define nRESUME_BE 0x0
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define nRESET_OR_BABLE_BE 0x0
#define SOF_BE 0x8 /* Start of frame int enable */
-#define nSOF_BE 0x0
#define CONN_BE 0x10 /* Connection indicator int enable */
-#define nCONN_BE 0x0
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define nDISCON_BE 0x0
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define nSESSION_REQ_BE 0x0
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-#define nVBUS_ERROR_BE 0x0
/* Bit masks for USB_FRAME */
/* Bit masks for USB_GLOBAL_CTL */
#define GLOBAL_ENA 0x1 /* enables USB module */
-#define nGLOBAL_ENA 0x0
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define nEP1_TX_ENA 0x0
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define nEP2_TX_ENA 0x0
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define nEP3_TX_ENA 0x0
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define nEP4_TX_ENA 0x0
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define nEP5_TX_ENA 0x0
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define nEP6_TX_ENA 0x0
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define nEP7_TX_ENA 0x0
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define nEP1_RX_ENA 0x0
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define nEP2_RX_ENA 0x0
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define nEP3_RX_ENA 0x0
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define nEP4_RX_ENA 0x0
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define nEP5_RX_ENA 0x0
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define nEP6_RX_ENA 0x0
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-#define nEP7_RX_ENA 0x0
/* Bit masks for USB_OTG_DEV_CTL */
#define SESSION 0x1 /* session indicator */
-#define nSESSION 0x0
#define HOST_REQ 0x2 /* Host negotiation request */
-#define nHOST_REQ 0x0
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define nHOST_MODE 0x0
#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define nVBUS0 0x0
#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define nVBUS1 0x0
#define LSDEV 0x20 /* Low-speed indicator */
-#define nLSDEV 0x0
#define FSDEV 0x40 /* Full or High-speed indicator */
-#define nFSDEV 0x0
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-#define nB_DEVICE 0x0
/* Bit masks for USB_OTG_VBUS_IRQ */
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define nDRIVE_VBUS_ON 0x0
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define nDRIVE_VBUS_OFF 0x0
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define nCHRG_VBUS_START 0x0
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define nCHRG_VBUS_END 0x0
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define nDISCHRG_VBUS_START 0x0
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-#define nDISCHRG_VBUS_END 0x0
/* Bit masks for USB_OTG_VBUS_MASK */
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define nDRIVE_VBUS_ON_ENA 0x0
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define nDRIVE_VBUS_OFF_ENA 0x0
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define nCHRG_VBUS_START_ENA 0x0
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define nCHRG_VBUS_END_ENA 0x0
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define nDISCHRG_VBUS_START_ENA 0x0
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-#define nDISCHRG_VBUS_END_ENA 0x0
/* Bit masks for USB_CSR0 */
#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define nRXPKTRDY 0x0
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define nTXPKTRDY 0x0
#define STALL_SENT 0x4 /* STALL handshake sent */
-#define nSTALL_SENT 0x0
#define DATAEND 0x8 /* Data end indicator */
-#define nDATAEND 0x0
#define SETUPEND 0x10 /* Setup end */
-#define nSETUPEND 0x0
#define SENDSTALL 0x20 /* Send STALL handshake */
-#define nSENDSTALL 0x0
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define nSERVICED_RXPKTRDY 0x0
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define nSERVICED_SETUPEND 0x0
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define nFLUSHFIFO 0x0
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define nSTALL_RECEIVED_H 0x0
#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define nSETUPPKT_H 0x0
#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define nERROR_H 0x0
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define nREQPKT_H 0x0
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define nSTATUSPKT_H 0x0
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-#define nNAK_TIMEOUT_H 0x0
/* Bit masks for USB_COUNT0 */
/* Bit masks for USB_TXCSR */
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define nTXPKTRDY_T 0x0
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define nFIFO_NOT_EMPTY_T 0x0
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define nUNDERRUN_T 0x0
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define nFLUSHFIFO_T 0x0
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define nSTALL_SEND_T 0x0
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define nSTALL_SENT_T 0x0
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_T 0x0
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define nINCOMPTX_T 0x0
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_T 0x0
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define nFORCE_DATATOGGLE_T 0x0
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_T 0x0
#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define nISO_T 0x0
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOSET_T 0x0
#define ERROR_TH 0x4 /* error condition host mode */
-#define nERROR_TH 0x0
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_TH 0x0
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-#define nNAK_TIMEOUT_TH 0x0
/* Bit masks for USB_TXCOUNT */
/* Bit masks for USB_RXCSR */
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define nRXPKTRDY_R 0x0
#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define nFIFO_FULL_R 0x0
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define nOVERRUN_R 0x0
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define nDATAERROR_R 0x0
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define nFLUSHFIFO_R 0x0
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define nSTALL_SEND_R 0x0
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define nSTALL_SENT_R 0x0
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_R 0x0
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define nINCOMPRX_R 0x0
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_R 0x0
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define nDISNYET_R 0x0
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_R 0x0
#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define nISO_R 0x0
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOCLEAR_R 0x0
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define nERROR_RH 0x0
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define nREQPKT_RH 0x0
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_RH 0x0
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define nINCOMPRX_RH 0x0
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define nDMAREQMODE_RH 0x0
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-#define nAUTOREQ_RH 0x0
/* Bit masks for USB_RXCOUNT */
/* Bit masks for USB_DMA_INTERRUPT */
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define nDMA0_INT 0x0
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define nDMA1_INT 0x0
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define nDMA2_INT 0x0
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define nDMA3_INT 0x0
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define nDMA4_INT 0x0
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define nDMA5_INT 0x0
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define nDMA6_INT 0x0
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-#define nDMA7_INT 0x0
/* Bit masks for USB_DMAxCONTROL */
#define DMA_ENA 0x1 /* DMA enable */
-#define nDMA_ENA 0x0
#define DIRECTION 0x2 /* direction of DMA transfer */
-#define nDIRECTION 0x0
#define MODE 0x4 /* DMA Bus error */
-#define nMODE 0x0
#define INT_ENA 0x8 /* Interrupt enable */
-#define nINT_ENA 0x0
#define EPNUM 0xf0 /* EP number */
#define BUSERROR 0x100 /* DMA Bus error */
-#define nBUSERROR 0x0
/* Bit masks for USB_DMAxADDRHIGH */
/* Bit masks for HMDMAx_CONTROL */
#define HMDMAEN 0x1 /* Handshake MDMA Enable */
-#define nHMDMAEN 0x0
#define REP 0x2 /* Handshake MDMA Request Polarity */
-#define nREP 0x0
#define UTE 0x8 /* Urgency Threshold Enable */
-#define nUTE 0x0
#define OIE 0x10 /* Overflow Interrupt Enable */
-#define nOIE 0x0
#define BDIE 0x20 /* Block Done Interrupt Enable */
-#define nBDIE 0x0
#define MBDI 0x40 /* Mask Block Done Interrupt */
-#define nMBDI 0x0
#define DRQ 0x300 /* Handshake MDMA Request Type */
#define RBC 0x1000 /* Force Reload of BCOUNT */
-#define nRBC 0x0
#define PS 0x2000 /* Pin Status */
-#define nPS 0x0
#define OI 0x4000 /* Overflow Interrupt Generated */
-#define nOI 0x0
#define BDI 0x8000 /* Block Done Interrupt Generated */
-#define nBDI 0x0
/* ******************************************* */
/* MULTI BIT MACRO ENUMERATIONS */
/* Bit masks for PIXC_CTL */
#define PIXC_EN 0x1 /* Pixel Compositor Enable */
-#define nPIXC_EN 0x0
#define OVR_A_EN 0x2 /* Overlay A Enable */
-#define nOVR_A_EN 0x0
#define OVR_B_EN 0x4 /* Overlay B Enable */
-#define nOVR_B_EN 0x0
#define IMG_FORM 0x8 /* Image Data Format */
-#define nIMG_FORM 0x0
#define OVR_FORM 0x10 /* Overlay Data Format */
-#define nOVR_FORM 0x0
#define OUT_FORM 0x20 /* Output Data Format */
-#define nOUT_FORM 0x0
#define UDS_MOD 0x40 /* Resampling Mode */
-#define nUDS_MOD 0x0
#define TC_EN 0x80 /* Transparent Color Enable */
-#define nTC_EN 0x0
#define IMG_STAT 0x300 /* Image FIFO Status */
#define OVR_STAT 0xc00 /* Overlay FIFO Status */
#define WM_LVL 0x3000 /* FIFO Watermark Level */
/* Bit masks for PIXC_INTRSTAT */
#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
-#define nOVR_INT_EN 0x0
#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
-#define nFRM_INT_EN 0x0
#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
-#define nOVR_INT_STAT 0x0
#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
-#define nFRM_INT_STAT 0x0
/* Bit masks for PIXC_RYCON */
#define A12 0xffc00 /* A12 in the Coefficient Matrix */
#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
-#define nRY_MULT4 0x0
/* Bit masks for PIXC_GUCON */
#define A22 0xffc00 /* A22 in the Coefficient Matrix */
#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
-#define nGU_MULT4 0x0
/* Bit masks for PIXC_BVCON */
#define A32 0xffc00 /* A32 in the Coefficient Matrix */
#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
-#define nBV_MULT4 0x0
/* Bit masks for PIXC_CCBIAS */
/* Bit masks for HOST_CONTROL */
#define HOST_EN 0x1 /* Host Enable */
-#define nHOST_EN 0x0
#define HOST_END 0x2 /* Host Endianess */
-#define nHOST_END 0x0
#define DATA_SIZE 0x4 /* Data Size */
-#define nDATA_SIZE 0x0
#define HOST_RST 0x8 /* Host Reset */
-#define nHOST_RST 0x0
#define HRDY_OVR 0x20 /* Host Ready Override */
-#define nHRDY_OVR 0x0
#define INT_MODE 0x40 /* Interrupt Mode */
-#define nINT_MODE 0x0
#define BT_EN 0x80 /* Bus Timeout Enable */
-#define nBT_EN 0x0
#define EHW 0x100 /* Enable Host Write */
-#define nEHW 0x0
#define EHR 0x200 /* Enable Host Read */
-#define nEHR 0x0
#define BDR 0x400 /* Burst DMA Requests */
-#define nBDR 0x0
/* Bit masks for HOST_STATUS */
#define READY 0x1 /* DMA Ready */
-#define nREADY 0x0
#define FIFOFULL 0x2 /* FIFO Full */
-#define nFIFOFULL 0x0
#define FIFOEMPTY 0x4 /* FIFO Empty */
-#define nFIFOEMPTY 0x0
-#define COMPLETE 0x8 /* DMA Complete */
-#define nCOMPLETE 0x0
+#define DMA_COMPLETE 0x8 /* DMA Complete */
#define HSHK 0x10 /* Host Handshake */
-#define nHSHK 0x0
#define TIMEOUT 0x20 /* Host Timeout */
-#define nTIMEOUT 0x0
#define HIRQ 0x40 /* Host Interrupt Request */
-#define nHIRQ 0x0
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define nALLOW_CNFG 0x0
#define DMA_DIR 0x100 /* DMA Direction */
-#define nDMA_DIR 0x0
#define BTE 0x200 /* Bus Timeout Enabled */
-#define nBTE 0x0
/* Bit masks for HOST_TIMEOUT */
/* Bit masks for MXVR_CONFIG */
#define MXVREN 0x1 /* MXVR Enable */
-#define nMXVREN 0x0
#define MMSM 0x2 /* MXVR Master/Slave Mode Select */
-#define nMMSM 0x0
#define ACTIVE 0x4 /* Active Mode */
-#define nACTIVE 0x0
#define SDELAY 0x8 /* Synchronous Data Delay */
-#define nSDELAY 0x0
#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */
-#define nNCMRXEN 0x0
#define RWRRXEN 0x20 /* Remote Write Receive Enable */
-#define nRWRRXEN 0x0
#define MTXEN 0x40 /* MXVR Transmit Data Enable */
-#define nMTXEN 0x0
#define MTXONB 0x80 /* MXVR Phy Transmitter On */
-#define nMTXONB 0x0
#define EPARITY 0x100 /* Even Parity Select */
-#define nEPARITY 0x0
#define MSB 0x1e00 /* Master Synchronous Boundary */
#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */
-#define nAPRXEN 0x0
#define WAKEUP 0x4000 /* Wake-Up */
-#define nWAKEUP 0x0
#define LMECH 0x8000 /* Lock Mechanism Select */
-#define nLMECH 0x0
/* Bit masks for MXVR_STATE_0 */
#define NACT 0x1 /* Network Activity */
-#define nNACT 0x0
#define SBLOCK 0x2 /* Super Block Lock */
-#define nSBLOCK 0x0
#define FMPLLST 0xc /* Frequency Multiply PLL SM State */
#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */
#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */
-#define nAPBSY 0x0
#define APARB 0x200 /* Asynchronous Packet Arbitrating */
-#define nAPARB 0x0
#define APTX 0x400 /* Asynchronous Packet Transmitting */
-#define nAPTX 0x0
#define APRX 0x800 /* Receiving Asynchronous Packet */
-#define nAPRX 0x0
#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */
-#define nCMBSY 0x0
#define CMARB 0x2000 /* Control Message Arbitrating */
-#define nCMARB 0x0
#define CMTX 0x4000 /* Control Message Transmitting */
-#define nCMTX 0x0
#define CMRX 0x8000 /* Receiving Control Message */
-#define nCMRX 0x0
#define MRXONB 0x10000 /* MRXONB Pin State */
-#define nMRXONB 0x0
#define RGSIP 0x20000 /* Remote Get Source In Progress */
-#define nRGSIP 0x0
#define DALIP 0x40000 /* Resource Deallocate In Progress */
-#define nDALIP 0x0
#define ALIP 0x80000 /* Resource Allocate In Progress */
-#define nALIP 0x0
#define RRDIP 0x100000 /* Remote Read In Progress */
-#define nRRDIP 0x0
#define RWRIP 0x200000 /* Remote Write In Progress */
-#define nRWRIP 0x0
#define FLOCK 0x400000 /* Frame Lock */
-#define nFLOCK 0x0
#define BLOCK 0x800000 /* Block Lock */
-#define nBLOCK 0x0
#define RSB 0xf000000 /* Received Synchronous Boundary */
#define DERRNUM 0xf0000000 /* DMA Error Channel Number */
#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */
#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */
#define APCONT 0x100 /* Asynchronous Packet Continuation */
-#define nAPCONT 0x0
#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */
#define DMAACTIVE0 0x10000 /* DMA0 Active */
-#define nDMAACTIVE0 0x0
#define DMAACTIVE1 0x20000 /* DMA1 Active */
-#define nDMAACTIVE1 0x0
#define DMAACTIVE2 0x40000 /* DMA2 Active */
-#define nDMAACTIVE2 0x0
#define DMAACTIVE3 0x80000 /* DMA3 Active */
-#define nDMAACTIVE3 0x0
#define DMAACTIVE4 0x100000 /* DMA4 Active */
-#define nDMAACTIVE4 0x0
#define DMAACTIVE5 0x200000 /* DMA5 Active */
-#define nDMAACTIVE5 0x0
#define DMAACTIVE6 0x400000 /* DMA6 Active */
-#define nDMAACTIVE6 0x0
#define DMAACTIVE7 0x800000 /* DMA7 Active */
-#define nDMAACTIVE7 0x0
#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */
-#define nDMAPMEN0 0x0
#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */
-#define nDMAPMEN1 0x0
#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */
-#define nDMAPMEN2 0x0
#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */
-#define nDMAPMEN3 0x0
#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */
-#define nDMAPMEN4 0x0
#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */
-#define nDMAPMEN5 0x0
#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */
-#define nDMAPMEN6 0x0
#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */
-#define nDMAPMEN7 0x0
/* Bit masks for MXVR_INT_STAT_0 */
#define NI2A 0x1 /* Network Inactive to Active */
-#define nNI2A 0x0
#define NA2I 0x2 /* Network Active to Inactive */
-#define nNA2I 0x0
#define SBU2L 0x4 /* Super Block Unlock to Lock */
-#define nSBU2L 0x0
#define SBL2U 0x8 /* Super Block Lock to Unlock */
-#define nSBL2U 0x0
#define PRU 0x10 /* Position Register Updated */
-#define nPRU 0x0
#define MPRU 0x20 /* Maximum Position Register Updated */
-#define nMPRU 0x0
#define DRU 0x40 /* Delay Register Updated */
-#define nDRU 0x0
#define MDRU 0x80 /* Maximum Delay Register Updated */
-#define nMDRU 0x0
#define SBU 0x100 /* Synchronous Boundary Updated */
-#define nSBU 0x0
#define ATU 0x200 /* Allocation Table Updated */
-#define nATU 0x0
#define FCZ0 0x400 /* Frame Counter 0 Zero */
-#define nFCZ0 0x0
#define FCZ1 0x800 /* Frame Counter 1 Zero */
-#define nFCZ1 0x0
#define PERR 0x1000 /* Parity Error */
-#define nPERR 0x0
#define MH2L 0x2000 /* MRXONB High to Low */
-#define nMH2L 0x0
#define ML2H 0x4000 /* MRXONB Low to High */
-#define nML2H 0x0
#define WUP 0x8000 /* Wake-Up Preamble Received */
-#define nWUP 0x0
#define FU2L 0x10000 /* Frame Unlock to Lock */
-#define nFU2L 0x0
#define FL2U 0x20000 /* Frame Lock to Unlock */
-#define nFL2U 0x0
#define BU2L 0x40000 /* Block Unlock to Lock */
-#define nBU2L 0x0
#define BL2U 0x80000 /* Block Lock to Unlock */
-#define nBL2U 0x0
#define OBERR 0x100000 /* DMA Out of Bounds Error */
-#define nOBERR 0x0
#define PFL 0x200000 /* PLL Frequency Locked */
-#define nPFL 0x0
#define SCZ 0x400000 /* System Clock Counter Zero */
-#define nSCZ 0x0
#define FERR 0x800000 /* FIFO Error */
-#define nFERR 0x0
#define CMR 0x1000000 /* Control Message Received */
-#define nCMR 0x0
#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */
-#define nCMROF 0x0
#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */
-#define nCMTS 0x0
#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */
-#define nCMTC 0x0
#define RWRC 0x10000000 /* Remote Write Control Message Completed */
-#define nRWRC 0x0
#define BCZ 0x20000000 /* Block Counter Zero */
-#define nBCZ 0x0
#define BMERR 0x40000000 /* Biphase Mark Coding Error */
-#define nBMERR 0x0
#define DERR 0x80000000 /* DMA Error */
-#define nDERR 0x0
/* Bit masks for MXVR_INT_STAT_1 */
#define HDONE0 0x1 /* DMA0 Half Done */
-#define nHDONE0 0x0
#define DONE0 0x2 /* DMA0 Done */
-#define nDONE0 0x0
#define APR 0x4 /* Asynchronous Packet Received */
-#define nAPR 0x0
#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */
-#define nAPROF 0x0
#define HDONE1 0x10 /* DMA1 Half Done */
-#define nHDONE1 0x0
#define DONE1 0x20 /* DMA1 Done */
-#define nDONE1 0x0
#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */
-#define nAPTS 0x0
#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
-#define nAPTC 0x0
#define HDONE2 0x100 /* DMA2 Half Done */
-#define nHDONE2 0x0
#define DONE2 0x200 /* DMA2 Done */
-#define nDONE2 0x0
#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */
-#define nAPRCE 0x0
#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */
-#define nAPRPE 0x0
#define HDONE3 0x1000 /* DMA3 Half Done */
-#define nHDONE3 0x0
#define DONE3 0x2000 /* DMA3 Done */
-#define nDONE3 0x0
#define HDONE4 0x10000 /* DMA4 Half Done */
-#define nHDONE4 0x0
#define DONE4 0x20000 /* DMA4 Done */
-#define nDONE4 0x0
#define HDONE5 0x100000 /* DMA5 Half Done */
-#define nHDONE5 0x0
#define DONE5 0x200000 /* DMA5 Done */
-#define nDONE5 0x0
#define HDONE6 0x1000000 /* DMA6 Half Done */
-#define nHDONE6 0x0
#define DONE6 0x2000000 /* DMA6 Done */
-#define nDONE6 0x0
#define HDONE7 0x10000000 /* DMA7 Half Done */
-#define nHDONE7 0x0
#define DONE7 0x20000000 /* DMA7 Done */
-#define nDONE7 0x0
/* Bit masks for MXVR_INT_EN_0 */
#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */
-#define nNI2AEN 0x0
#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */
-#define nNA2IEN 0x0
#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */
-#define nSBU2LEN 0x0
#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */
-#define nSBL2UEN 0x0
#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */
-#define nPRUEN 0x0
#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */
-#define nMPRUEN 0x0
#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */
-#define nDRUEN 0x0
#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */
-#define nMDRUEN 0x0
#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */
-#define nSBUEN 0x0
#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */
-#define nATUEN 0x0
#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */
-#define nFCZ0EN 0x0
#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */
-#define nFCZ1EN 0x0
#define PERREN 0x1000 /* Parity Error Interrupt Enable */
-#define nPERREN 0x0
#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */
-#define nMH2LEN 0x0
#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */
-#define nML2HEN 0x0
#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */
-#define nWUPEN 0x0
#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */
-#define nFU2LEN 0x0
#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */
-#define nFL2UEN 0x0
#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */
-#define nBU2LEN 0x0
#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */
-#define nBL2UEN 0x0
#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */
-#define nOBERREN 0x0
#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */
-#define nPFLEN 0x0
#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */
-#define nSCZEN 0x0
#define FERREN 0x800000 /* FIFO Error Interrupt Enable */
-#define nFERREN 0x0
#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */
-#define nCMREN 0x0
#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */
-#define nCMROFEN 0x0
#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
-#define nCMTSEN 0x0
#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define nCMTCEN 0x0
#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
-#define nRWRCEN 0x0
#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */
-#define nBCZEN 0x0
#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
-#define nBMERREN 0x0
#define DERREN 0x80000000 /* DMA Error Interrupt Enable */
-#define nDERREN 0x0
/* Bit masks for MXVR_INT_EN_1 */
#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */
-#define nHDONEEN0 0x0
#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */
-#define nDONEEN0 0x0
#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */
-#define nAPREN 0x0
#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
-#define nAPROFEN 0x0
#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */
-#define nHDONEEN1 0x0
#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */
-#define nDONEEN1 0x0
#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
-#define nAPTSEN 0x0
#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define nAPTCEN 0x0
#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */
-#define nHDONEEN2 0x0
#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */
-#define nDONEEN2 0x0
#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */
-#define nAPRCEEN 0x0
#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */
-#define nAPRPEEN 0x0
#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */
-#define nHDONEEN3 0x0
#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */
-#define nDONEEN3 0x0
#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */
-#define nHDONEEN4 0x0
#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */
-#define nDONEEN4 0x0
#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */
-#define nHDONEEN5 0x0
#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */
-#define nDONEEN5 0x0
#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */
-#define nHDONEEN6 0x0
#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */
-#define nDONEEN6 0x0
#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */
-#define nHDONEEN7 0x0
#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */
-#define nDONEEN7 0x0
/* Bit masks for MXVR_POSITION */
#define POSITION 0x3f /* Node Position */
#define PVALID 0x8000 /* Node Position Valid */
-#define nPVALID 0x0
/* Bit masks for MXVR_MAX_POSITION */
#define MPOSITION 0x3f /* Maximum Node Position */
#define MPVALID 0x8000 /* Maximum Node Position Valid */
-#define nMPVALID 0x0
/* Bit masks for MXVR_DELAY */
#define DELAY 0x3f /* Node Frame Delay */
#define DVALID 0x8000 /* Node Frame Delay Valid */
-#define nDVALID 0x0
/* Bit masks for MXVR_MAX_DELAY */
#define MDELAY 0x3f /* Maximum Node Frame Delay */
#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */
-#define nMDVALID 0x0
/* Bit masks for MXVR_LADDR */
#define LADDR 0xffff /* Logical Address */
#define LVALID 0x80000000 /* Logical Address Valid */
-#define nLVALID 0x0
/* Bit masks for MXVR_GADDR */
#define GADDRL 0xff /* Group Address Lower Byte */
#define GVALID 0x8000 /* Group Address Valid */
-#define nGVALID 0x0
/* Bit masks for MXVR_AADDR */
#define AADDR 0xffff /* Alternate Address */
#define AVALID 0x80000000 /* Alternate Address Valid */
-#define nAVALID 0x0
/* Bit masks for MXVR_ALLOC_0 */
#define CL0 0x7f /* Channel 0 Connection Label */
#define CIU0 0x80 /* Channel 0 In Use */
-#define nCIU0 0x0
#define CL1 0x7f00 /* Channel 0 Connection Label */
#define CIU1 0x8000 /* Channel 0 In Use */
-#define nCIU1 0x0
#define CL2 0x7f0000 /* Channel 0 Connection Label */
#define CIU2 0x800000 /* Channel 0 In Use */
-#define nCIU2 0x0
#define CL3 0x7f000000 /* Channel 0 Connection Label */
#define CIU3 0x80000000 /* Channel 0 In Use */
-#define nCIU3 0x0
/* Bit masks for MXVR_ALLOC_1 */
#define CL4 0x7f /* Channel 4 Connection Label */
#define CIU4 0x80 /* Channel 4 In Use */
-#define nCIU4 0x0
#define CL5 0x7f00 /* Channel 5 Connection Label */
#define CIU5 0x8000 /* Channel 5 In Use */
-#define nCIU5 0x0
#define CL6 0x7f0000 /* Channel 6 Connection Label */
#define CIU6 0x800000 /* Channel 6 In Use */
-#define nCIU6 0x0
#define CL7 0x7f000000 /* Channel 7 Connection Label */
#define CIU7 0x80000000 /* Channel 7 In Use */
-#define nCIU7 0x0
/* Bit masks for MXVR_ALLOC_2 */
#define CL8 0x7f /* Channel 8 Connection Label */
#define CIU8 0x80 /* Channel 8 In Use */
-#define nCIU8 0x0
#define CL9 0x7f00 /* Channel 9 Connection Label */
#define CIU9 0x8000 /* Channel 9 In Use */
-#define nCIU9 0x0
#define CL10 0x7f0000 /* Channel 10 Connection Label */
#define CIU10 0x800000 /* Channel 10 In Use */
-#define nCIU10 0x0
#define CL11 0x7f000000 /* Channel 11 Connection Label */
#define CIU11 0x80000000 /* Channel 11 In Use */
-#define nCIU11 0x0
/* Bit masks for MXVR_ALLOC_3 */
#define CL12 0x7f /* Channel 12 Connection Label */
#define CIU12 0x80 /* Channel 12 In Use */
-#define nCIU12 0x0
#define CL13 0x7f00 /* Channel 13 Connection Label */
#define CIU13 0x8000 /* Channel 13 In Use */
-#define nCIU13 0x0
#define CL14 0x7f0000 /* Channel 14 Connection Label */
#define CIU14 0x800000 /* Channel 14 In Use */
-#define nCIU14 0x0
#define CL15 0x7f000000 /* Channel 15 Connection Label */
#define CIU15 0x80000000 /* Channel 15 In Use */
-#define nCIU15 0x0
/* Bit masks for MXVR_ALLOC_4 */
#define CL16 0x7f /* Channel 16 Connection Label */
#define CIU16 0x80 /* Channel 16 In Use */
-#define nCIU16 0x0
#define CL17 0x7f00 /* Channel 17 Connection Label */
#define CIU17 0x8000 /* Channel 17 In Use */
-#define nCIU17 0x0
#define CL18 0x7f0000 /* Channel 18 Connection Label */
#define CIU18 0x800000 /* Channel 18 In Use */
-#define nCIU18 0x0
#define CL19 0x7f000000 /* Channel 19 Connection Label */
#define CIU19 0x80000000 /* Channel 19 In Use */
-#define nCIU19 0x0
/* Bit masks for MXVR_ALLOC_5 */
#define CL20 0x7f /* Channel 20 Connection Label */
#define CIU20 0x80 /* Channel 20 In Use */
-#define nCIU20 0x0
#define CL21 0x7f00 /* Channel 21 Connection Label */
#define CIU21 0x8000 /* Channel 21 In Use */
-#define nCIU21 0x0
#define CL22 0x7f0000 /* Channel 22 Connection Label */
#define CIU22 0x800000 /* Channel 22 In Use */
-#define nCIU22 0x0
#define CL23 0x7f000000 /* Channel 23 Connection Label */
#define CIU23 0x80000000 /* Channel 23 In Use */
-#define nCIU23 0x0
/* Bit masks for MXVR_ALLOC_6 */
#define CL24 0x7f /* Channel 24 Connection Label */
#define CIU24 0x80 /* Channel 24 In Use */
-#define nCIU24 0x0
#define CL25 0x7f00 /* Channel 25 Connection Label */
#define CIU25 0x8000 /* Channel 25 In Use */
-#define nCIU25 0x0
#define CL26 0x7f0000 /* Channel 26 Connection Label */
#define CIU26 0x800000 /* Channel 26 In Use */
-#define nCIU26 0x0
#define CL27 0x7f000000 /* Channel 27 Connection Label */
#define CIU27 0x80000000 /* Channel 27 In Use */
-#define nCIU27 0x0
/* Bit masks for MXVR_ALLOC_7 */
#define CL28 0x7f /* Channel 28 Connection Label */
#define CIU28 0x80 /* Channel 28 In Use */
-#define nCIU28 0x0
#define CL29 0x7f00 /* Channel 29 Connection Label */
#define CIU29 0x8000 /* Channel 29 In Use */
-#define nCIU29 0x0
#define CL30 0x7f0000 /* Channel 30 Connection Label */
#define CIU30 0x800000 /* Channel 30 In Use */
-#define nCIU30 0x0
#define CL31 0x7f000000 /* Channel 31 Connection Label */
#define CIU31 0x80000000 /* Channel 31 In Use */
-#define nCIU31 0x0
/* Bit masks for MXVR_ALLOC_8 */
#define CL32 0x7f /* Channel 32 Connection Label */
#define CIU32 0x80 /* Channel 32 In Use */
-#define nCIU32 0x0
#define CL33 0x7f00 /* Channel 33 Connection Label */
#define CIU33 0x8000 /* Channel 33 In Use */
-#define nCIU33 0x0
#define CL34 0x7f0000 /* Channel 34 Connection Label */
#define CIU34 0x800000 /* Channel 34 In Use */
-#define nCIU34 0x0
#define CL35 0x7f000000 /* Channel 35 Connection Label */
#define CIU35 0x80000000 /* Channel 35 In Use */
-#define nCIU35 0x0
/* Bit masks for MXVR_ALLOC_9 */
#define CL36 0x7f /* Channel 36 Connection Label */
#define CIU36 0x80 /* Channel 36 In Use */
-#define nCIU36 0x0
#define CL37 0x7f00 /* Channel 37 Connection Label */
#define CIU37 0x8000 /* Channel 37 In Use */
-#define nCIU37 0x0
#define CL38 0x7f0000 /* Channel 38 Connection Label */
#define CIU38 0x800000 /* Channel 38 In Use */
-#define nCIU38 0x0
#define CL39 0x7f000000 /* Channel 39 Connection Label */
#define CIU39 0x80000000 /* Channel 39 In Use */
-#define nCIU39 0x0
/* Bit masks for MXVR_ALLOC_10 */
#define CL40 0x7f /* Channel 40 Connection Label */
#define CIU40 0x80 /* Channel 40 In Use */
-#define nCIU40 0x0
#define CL41 0x7f00 /* Channel 41 Connection Label */
#define CIU41 0x8000 /* Channel 41 In Use */
-#define nCIU41 0x0
#define CL42 0x7f0000 /* Channel 42 Connection Label */
#define CIU42 0x800000 /* Channel 42 In Use */
-#define nCIU42 0x0
#define CL43 0x7f000000 /* Channel 43 Connection Label */
#define CIU43 0x80000000 /* Channel 43 In Use */
-#define nCIU43 0x0
/* Bit masks for MXVR_ALLOC_11 */
#define CL44 0x7f /* Channel 44 Connection Label */
#define CIU44 0x80 /* Channel 44 In Use */
-#define nCIU44 0x0
#define CL45 0x7f00 /* Channel 45 Connection Label */
#define CIU45 0x8000 /* Channel 45 In Use */
-#define nCIU45 0x0
#define CL46 0x7f0000 /* Channel 46 Connection Label */
#define CIU46 0x800000 /* Channel 46 In Use */
-#define nCIU46 0x0
#define CL47 0x7f000000 /* Channel 47 Connection Label */
#define CIU47 0x80000000 /* Channel 47 In Use */
-#define nCIU47 0x0
/* Bit masks for MXVR_ALLOC_12 */
#define CL48 0x7f /* Channel 48 Connection Label */
#define CIU48 0x80 /* Channel 48 In Use */
-#define nCIU48 0x0
#define CL49 0x7f00 /* Channel 49 Connection Label */
#define CIU49 0x8000 /* Channel 49 In Use */
-#define nCIU49 0x0
#define CL50 0x7f0000 /* Channel 50 Connection Label */
#define CIU50 0x800000 /* Channel 50 In Use */
-#define nCIU50 0x0
#define CL51 0x7f000000 /* Channel 51 Connection Label */
#define CIU51 0x80000000 /* Channel 51 In Use */
-#define nCIU51 0x0
/* Bit masks for MXVR_ALLOC_13 */
#define CL52 0x7f /* Channel 52 Connection Label */
#define CIU52 0x80 /* Channel 52 In Use */
-#define nCIU52 0x0
#define CL53 0x7f00 /* Channel 53 Connection Label */
#define CIU53 0x8000 /* Channel 53 In Use */
-#define nCIU53 0x0
#define CL54 0x7f0000 /* Channel 54 Connection Label */
#define CIU54 0x800000 /* Channel 54 In Use */
-#define nCIU54 0x0
#define CL55 0x7f000000 /* Channel 55 Connection Label */
#define CIU55 0x80000000 /* Channel 55 In Use */
-#define nCIU55 0x0
/* Bit masks for MXVR_ALLOC_14 */
#define CL56 0x7f /* Channel 56 Connection Label */
#define CIU56 0x80 /* Channel 56 In Use */
-#define nCIU56 0x0
#define CL57 0x7f00 /* Channel 57 Connection Label */
#define CIU57 0x8000 /* Channel 57 In Use */
-#define nCIU57 0x0
#define CL58 0x7f0000 /* Channel 58 Connection Label */
#define CIU58 0x800000 /* Channel 58 In Use */
-#define nCIU58 0x0
#define CL59 0x7f000000 /* Channel 59 Connection Label */
#define CIU59 0x80000000 /* Channel 59 In Use */
-#define nCIU59 0x0
/* MXVR_SYNC_LCHAN_0 Masks */
/* Bit masks for MXVR_DMAx_CONFIG */
#define MDMAEN 0x1 /* DMA Channel Enable */
-#define nMDMAEN 0x0
#define DD 0x2 /* DMA Channel Direction */
-#define nDD 0x0
#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */
-#define nBY4SWAPEN 0x0
#define LCHAN 0x3c0 /* DMA Channel Logical Channel */
#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */
-#define nBITSWAPEN 0x0
#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */
-#define nBY2SWAPEN 0x0
#define MFLOW 0x7000 /* DMA Channel Operation Flow */
#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */
-#define nFIXEDPM 0x0
#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */
#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */
#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */
/* Bit masks for MXVR_AP_CTL */
#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */
-#define nSTARTAP 0x0
#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */
-#define nCANCELAP 0x0
#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */
-#define nRESETAP 0x0
#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */
-#define nAPRBE0 0x0
#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */
-#define nAPRBE1 0x0
/* Bit masks for MXVR_APRB_START_ADDR */
-#define MXVR_APRB_START_ADDR 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */
+#define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */
/* Bit masks for MXVR_APRB_CURR_ADDR */
-#define MXVR_APRB_CURR_ADDR 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
+#define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
/* Bit masks for MXVR_APTB_START_ADDR */
-#define MXVR_APTB_START_ADDR 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */
+#define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */
/* Bit masks for MXVR_APTB_CURR_ADDR */
-#define MXVR_APTB_CURR_ADDR 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
+#define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
/* Bit masks for MXVR_CM_CTL */
#define STARTCM 0x1 /* Start Control Message Transmission */
-#define nSTARTCM 0x0
#define CANCELCM 0x2 /* Cancel Control Message Transmission */
-#define nCANCELCM 0x0
#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */
-#define nCMRBE0 0x0
#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */
-#define nCMRBE1 0x0
#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */
-#define nCMRBE2 0x0
#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */
-#define nCMRBE3 0x0
#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */
-#define nCMRBE4 0x0
#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */
-#define nCMRBE5 0x0
#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */
-#define nCMRBE6 0x0
#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */
-#define nCMRBE7 0x0
#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */
-#define nCMRBE8 0x0
#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */
-#define nCMRBE9 0x0
#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */
-#define nCMRBE10 0x0
#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */
-#define nCMRBE11 0x0
#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */
-#define nCMRBE12 0x0
#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */
-#define nCMRBE13 0x0
#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */
-#define nCMRBE14 0x0
#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */
-#define nCMRBE15 0x0
/* Bit masks for MXVR_CMRB_START_ADDR */
-#define MXVR_CMRB_START_ADDR 0x1fffffe /* Control Message Receive Buffer Start Address */
+#define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */
/* Bit masks for MXVR_CMRB_CURR_ADDR */
-#define MXVR_CMRB_CURR_ADDR 0xffffffff /* Control Message Receive Buffer Current Address */
+#define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */
/* Bit masks for MXVR_CMTB_START_ADDR */
-#define MXVR_CMTB_START_ADDR 0x1fffffe /* Control Message Transmit Buffer Start Address */
+#define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */
/* Bit masks for MXVR_CMTB_CURR_ADDR */
-#define MXVR_CMTB_CURR_ADDR 0xffffffff /* Control Message Transmit Buffer Current Address */
+#define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */
/* Bit masks for MXVR_RRDB_START_ADDR */
-#define MXVR_RRDB_START_ADDR 0x1fffffe /* Remote Read Buffer Start Address */
+#define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */
/* Bit masks for MXVR_RRDB_CURR_ADDR */
-#define MXVR_RRDB_CURR_ADDR 0xffffffff /* Remote Read Buffer Current Address */
+#define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */
/* Bit masks for MXVR_PAT_DATAx */
/* Bit masks for MXVR_PAT_EN_0 */
#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
-#define nMATCH_EN_0_0 0x0
#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
-#define nMATCH_EN_0_1 0x0
#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
-#define nMATCH_EN_0_2 0x0
#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
-#define nMATCH_EN_0_3 0x0
#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
-#define nMATCH_EN_0_4 0x0
#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
-#define nMATCH_EN_0_5 0x0
#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
-#define nMATCH_EN_0_6 0x0
#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
-#define nMATCH_EN_0_7 0x0
#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
-#define nMATCH_EN_1_0 0x0
#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
-#define nMATCH_EN_1_1 0x0
#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
-#define nMATCH_EN_1_2 0x0
#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
-#define nMATCH_EN_1_3 0x0
#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
-#define nMATCH_EN_1_4 0x0
#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
-#define nMATCH_EN_1_5 0x0
#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
-#define nMATCH_EN_1_6 0x0
#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
-#define nMATCH_EN_1_7 0x0
#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
-#define nMATCH_EN_2_0 0x0
#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
-#define nMATCH_EN_2_1 0x0
#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
-#define nMATCH_EN_2_2 0x0
#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
-#define nMATCH_EN_2_3 0x0
#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
-#define nMATCH_EN_2_4 0x0
#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
-#define nMATCH_EN_2_5 0x0
#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
-#define nMATCH_EN_2_6 0x0
#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
-#define nMATCH_EN_2_7 0x0
#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
-#define nMATCH_EN_3_0 0x0
#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
-#define nMATCH_EN_3_1 0x0
#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
-#define nMATCH_EN_3_2 0x0
#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
-#define nMATCH_EN_3_3 0x0
#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define nMATCH_EN_3_4 0x0
#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define nMATCH_EN_3_5 0x0
#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define nMATCH_EN_3_6 0x0
#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-#define nMATCH_EN_3_7 0x0
/* Bit masks for MXVR_PAT_EN_1 */
#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
-#define nMATCH_EN_0_0 0x0
#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
-#define nMATCH_EN_0_1 0x0
#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
-#define nMATCH_EN_0_2 0x0
#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
-#define nMATCH_EN_0_3 0x0
#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
-#define nMATCH_EN_0_4 0x0
#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
-#define nMATCH_EN_0_5 0x0
#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
-#define nMATCH_EN_0_6 0x0
#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
-#define nMATCH_EN_0_7 0x0
#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
-#define nMATCH_EN_1_0 0x0
#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
-#define nMATCH_EN_1_1 0x0
#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
-#define nMATCH_EN_1_2 0x0
#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
-#define nMATCH_EN_1_3 0x0
#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
-#define nMATCH_EN_1_4 0x0
#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
-#define nMATCH_EN_1_5 0x0
#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
-#define nMATCH_EN_1_6 0x0
#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
-#define nMATCH_EN_1_7 0x0
#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
-#define nMATCH_EN_2_0 0x0
#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
-#define nMATCH_EN_2_1 0x0
#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
-#define nMATCH_EN_2_2 0x0
#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
-#define nMATCH_EN_2_3 0x0
#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
-#define nMATCH_EN_2_4 0x0
#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
-#define nMATCH_EN_2_5 0x0
#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
-#define nMATCH_EN_2_6 0x0
#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
-#define nMATCH_EN_2_7 0x0
#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
-#define nMATCH_EN_3_0 0x0
#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
-#define nMATCH_EN_3_1 0x0
#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
-#define nMATCH_EN_3_2 0x0
#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
-#define nMATCH_EN_3_3 0x0
#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define nMATCH_EN_3_4 0x0
#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define nMATCH_EN_3_5 0x0
#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define nMATCH_EN_3_6 0x0
#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-#define nMATCH_EN_3_7 0x0
/* Bit masks for MXVR_FRAME_CNT_0 */
#define TX_CH0 0x3f /* Transmit Channel 0 */
#define MUTE_CH0 0x80 /* Mute Channel 0 */
-#define nMUTE_CH0 0x0
#define TX_CH1 0x3f00 /* Transmit Channel 0 */
#define MUTE_CH1 0x8000 /* Mute Channel 0 */
-#define nMUTE_CH1 0x0
#define TX_CH2 0x3f0000 /* Transmit Channel 0 */
#define MUTE_CH2 0x800000 /* Mute Channel 0 */
-#define nMUTE_CH2 0x0
#define TX_CH3 0x3f000000 /* Transmit Channel 0 */
#define MUTE_CH3 0x80000000 /* Mute Channel 0 */
-#define nMUTE_CH3 0x0
/* Bit masks for MXVR_ROUTING_1 */
#define TX_CH4 0x3f /* Transmit Channel 4 */
#define MUTE_CH4 0x80 /* Mute Channel 4 */
-#define nMUTE_CH4 0x0
#define TX_CH5 0x3f00 /* Transmit Channel 5 */
#define MUTE_CH5 0x8000 /* Mute Channel 5 */
-#define nMUTE_CH5 0x0
#define TX_CH6 0x3f0000 /* Transmit Channel 6 */
#define MUTE_CH6 0x800000 /* Mute Channel 6 */
-#define nMUTE_CH6 0x0
#define TX_CH7 0x3f000000 /* Transmit Channel 7 */
#define MUTE_CH7 0x80000000 /* Mute Channel 7 */
-#define nMUTE_CH7 0x0
/* Bit masks for MXVR_ROUTING_2 */
#define TX_CH8 0x3f /* Transmit Channel 8 */
#define MUTE_CH8 0x80 /* Mute Channel 8 */
-#define nMUTE_CH8 0x0
#define TX_CH9 0x3f00 /* Transmit Channel 9 */
#define MUTE_CH9 0x8000 /* Mute Channel 9 */
-#define nMUTE_CH9 0x0
#define TX_CH10 0x3f0000 /* Transmit Channel 10 */
#define MUTE_CH10 0x800000 /* Mute Channel 10 */
-#define nMUTE_CH10 0x0
#define TX_CH11 0x3f000000 /* Transmit Channel 11 */
#define MUTE_CH11 0x80000000 /* Mute Channel 11 */
-#define nMUTE_CH11 0x0
/* Bit masks for MXVR_ROUTING_3 */
#define TX_CH12 0x3f /* Transmit Channel 12 */
#define MUTE_CH12 0x80 /* Mute Channel 12 */
-#define nMUTE_CH12 0x0
#define TX_CH13 0x3f00 /* Transmit Channel 13 */
#define MUTE_CH13 0x8000 /* Mute Channel 13 */
-#define nMUTE_CH13 0x0
#define TX_CH14 0x3f0000 /* Transmit Channel 14 */
#define MUTE_CH14 0x800000 /* Mute Channel 14 */
-#define nMUTE_CH14 0x0
#define TX_CH15 0x3f000000 /* Transmit Channel 15 */
#define MUTE_CH15 0x80000000 /* Mute Channel 15 */
-#define nMUTE_CH15 0x0
/* Bit masks for MXVR_ROUTING_4 */
#define TX_CH16 0x3f /* Transmit Channel 16 */
#define MUTE_CH16 0x80 /* Mute Channel 16 */
-#define nMUTE_CH16 0x0
#define TX_CH17 0x3f00 /* Transmit Channel 17 */
#define MUTE_CH17 0x8000 /* Mute Channel 17 */
-#define nMUTE_CH17 0x0
#define TX_CH18 0x3f0000 /* Transmit Channel 18 */
#define MUTE_CH18 0x800000 /* Mute Channel 18 */
-#define nMUTE_CH18 0x0
#define TX_CH19 0x3f000000 /* Transmit Channel 19 */
#define MUTE_CH19 0x80000000 /* Mute Channel 19 */
-#define nMUTE_CH19 0x0
/* Bit masks for MXVR_ROUTING_5 */
#define TX_CH20 0x3f /* Transmit Channel 20 */
#define MUTE_CH20 0x80 /* Mute Channel 20 */
-#define nMUTE_CH20 0x0
#define TX_CH21 0x3f00 /* Transmit Channel 21 */
#define MUTE_CH21 0x8000 /* Mute Channel 21 */
-#define nMUTE_CH21 0x0
#define TX_CH22 0x3f0000 /* Transmit Channel 22 */
#define MUTE_CH22 0x800000 /* Mute Channel 22 */
-#define nMUTE_CH22 0x0
#define TX_CH23 0x3f000000 /* Transmit Channel 23 */
#define MUTE_CH23 0x80000000 /* Mute Channel 23 */
-#define nMUTE_CH23 0x0
/* Bit masks for MXVR_ROUTING_6 */
#define TX_CH24 0x3f /* Transmit Channel 24 */
#define MUTE_CH24 0x80 /* Mute Channel 24 */
-#define nMUTE_CH24 0x0
#define TX_CH25 0x3f00 /* Transmit Channel 25 */
#define MUTE_CH25 0x8000 /* Mute Channel 25 */
-#define nMUTE_CH25 0x0
#define TX_CH26 0x3f0000 /* Transmit Channel 26 */
#define MUTE_CH26 0x800000 /* Mute Channel 26 */
-#define nMUTE_CH26 0x0
#define TX_CH27 0x3f000000 /* Transmit Channel 27 */
#define MUTE_CH27 0x80000000 /* Mute Channel 27 */
-#define nMUTE_CH27 0x0
/* Bit masks for MXVR_ROUTING_7 */
#define TX_CH28 0x3f /* Transmit Channel 28 */
#define MUTE_CH28 0x80 /* Mute Channel 28 */
-#define nMUTE_CH28 0x0
#define TX_CH29 0x3f00 /* Transmit Channel 29 */
#define MUTE_CH29 0x8000 /* Mute Channel 29 */
-#define nMUTE_CH29 0x0
#define TX_CH30 0x3f0000 /* Transmit Channel 30 */
#define MUTE_CH30 0x800000 /* Mute Channel 30 */
-#define nMUTE_CH30 0x0
#define TX_CH31 0x3f000000 /* Transmit Channel 31 */
#define MUTE_CH31 0x80000000 /* Mute Channel 31 */
-#define nMUTE_CH31 0x0
/* Bit masks for MXVR_ROUTING_8 */
#define TX_CH32 0x3f /* Transmit Channel 32 */
#define MUTE_CH32 0x80 /* Mute Channel 32 */
-#define nMUTE_CH32 0x0
#define TX_CH33 0x3f00 /* Transmit Channel 33 */
#define MUTE_CH33 0x8000 /* Mute Channel 33 */
-#define nMUTE_CH33 0x0
#define TX_CH34 0x3f0000 /* Transmit Channel 34 */
#define MUTE_CH34 0x800000 /* Mute Channel 34 */
-#define nMUTE_CH34 0x0
#define TX_CH35 0x3f000000 /* Transmit Channel 35 */
#define MUTE_CH35 0x80000000 /* Mute Channel 35 */
-#define nMUTE_CH35 0x0
/* Bit masks for MXVR_ROUTING_9 */
#define TX_CH36 0x3f /* Transmit Channel 36 */
#define MUTE_CH36 0x80 /* Mute Channel 36 */
-#define nMUTE_CH36 0x0
#define TX_CH37 0x3f00 /* Transmit Channel 37 */
#define MUTE_CH37 0x8000 /* Mute Channel 37 */
-#define nMUTE_CH37 0x0
#define TX_CH38 0x3f0000 /* Transmit Channel 38 */
#define MUTE_CH38 0x800000 /* Mute Channel 38 */
-#define nMUTE_CH38 0x0
#define TX_CH39 0x3f000000 /* Transmit Channel 39 */
#define MUTE_CH39 0x80000000 /* Mute Channel 39 */
-#define nMUTE_CH39 0x0
/* Bit masks for MXVR_ROUTING_10 */
#define TX_CH40 0x3f /* Transmit Channel 40 */
#define MUTE_CH40 0x80 /* Mute Channel 40 */
-#define nMUTE_CH40 0x0
#define TX_CH41 0x3f00 /* Transmit Channel 41 */
#define MUTE_CH41 0x8000 /* Mute Channel 41 */
-#define nMUTE_CH41 0x0
#define TX_CH42 0x3f0000 /* Transmit Channel 42 */
#define MUTE_CH42 0x800000 /* Mute Channel 42 */
-#define nMUTE_CH42 0x0
#define TX_CH43 0x3f000000 /* Transmit Channel 43 */
#define MUTE_CH43 0x80000000 /* Mute Channel 43 */
-#define nMUTE_CH43 0x0
/* Bit masks for MXVR_ROUTING_11 */
#define TX_CH44 0x3f /* Transmit Channel 44 */
#define MUTE_CH44 0x80 /* Mute Channel 44 */
-#define nMUTE_CH44 0x0
#define TX_CH45 0x3f00 /* Transmit Channel 45 */
#define MUTE_CH45 0x8000 /* Mute Channel 45 */
-#define nMUTE_CH45 0x0
#define TX_CH46 0x3f0000 /* Transmit Channel 46 */
#define MUTE_CH46 0x800000 /* Mute Channel 46 */
-#define nMUTE_CH46 0x0
#define TX_CH47 0x3f000000 /* Transmit Channel 47 */
#define MUTE_CH47 0x80000000 /* Mute Channel 47 */
-#define nMUTE_CH47 0x0
/* Bit masks for MXVR_ROUTING_12 */
#define TX_CH48 0x3f /* Transmit Channel 48 */
#define MUTE_CH48 0x80 /* Mute Channel 48 */
-#define nMUTE_CH48 0x0
#define TX_CH49 0x3f00 /* Transmit Channel 49 */
#define MUTE_CH49 0x8000 /* Mute Channel 49 */
-#define nMUTE_CH49 0x0
#define TX_CH50 0x3f0000 /* Transmit Channel 50 */
#define MUTE_CH50 0x800000 /* Mute Channel 50 */
-#define nMUTE_CH50 0x0
#define TX_CH51 0x3f000000 /* Transmit Channel 51 */
#define MUTE_CH51 0x80000000 /* Mute Channel 51 */
-#define nMUTE_CH51 0x0
/* Bit masks for MXVR_ROUTING_13 */
#define TX_CH52 0x3f /* Transmit Channel 52 */
#define MUTE_CH52 0x80 /* Mute Channel 52 */
-#define nMUTE_CH52 0x0
#define TX_CH53 0x3f00 /* Transmit Channel 53 */
#define MUTE_CH53 0x8000 /* Mute Channel 53 */
-#define nMUTE_CH53 0x0
#define TX_CH54 0x3f0000 /* Transmit Channel 54 */
#define MUTE_CH54 0x800000 /* Mute Channel 54 */
-#define nMUTE_CH54 0x0
#define TX_CH55 0x3f000000 /* Transmit Channel 55 */
#define MUTE_CH55 0x80000000 /* Mute Channel 55 */
-#define nMUTE_CH55 0x0
/* Bit masks for MXVR_ROUTING_14 */
#define TX_CH56 0x3f /* Transmit Channel 56 */
#define MUTE_CH56 0x80 /* Mute Channel 56 */
-#define nMUTE_CH56 0x0
#define TX_CH57 0x3f00 /* Transmit Channel 57 */
#define MUTE_CH57 0x8000 /* Mute Channel 57 */
-#define nMUTE_CH57 0x0
#define TX_CH58 0x3f0000 /* Transmit Channel 58 */
#define MUTE_CH58 0x800000 /* Mute Channel 58 */
-#define nMUTE_CH58 0x0
#define TX_CH59 0x3f000000 /* Transmit Channel 59 */
#define MUTE_CH59 0x80000000 /* Mute Channel 59 */
-#define nMUTE_CH59 0x0
/* Bit masks for MXVR_BLOCK_CNT */
/* Bit masks for MXVR_CLK_CTL */
#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */
-#define nMXTALCEN 0x0
#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */
-#define nMXTALFEN 0x0
#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */
#define CLKX3SEL 0x80 /* Clock Generation Source Select */
-#define nCLKX3SEL 0x0
#define MMCLKEN 0x100 /* Master Clock Enable */
-#define nMMCLKEN 0x0
#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */
#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */
#define MBCLKEN 0x10000 /* Bit Clock Enable */
-#define nMBCLKEN 0x0
#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */
#define INVRX 0x800000 /* Invert Receive Data */
-#define nINVRX 0x0
#define MFSEN 0x1000000 /* Frame Sync Enable */
-#define nMFSEN 0x0
#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */
#define MFSSEL 0x60000000 /* Frame Sync Select */
#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */
-#define nMFSSYNC 0x0
/* Bit masks for MXVR_CDRPLL_CTL */
#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */
-#define nCDRSMEN 0x0
#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */
-#define nCDRRSTB 0x0
#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */
-#define nCDRSVCO 0x0
#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */
-#define nCDRMODE 0x0
#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */
#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */
#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */
#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */
-#define nCDRSHPEN 0x0
#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
/* Bit masks for MXVR_FMPLL_CTL */
#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */
-#define nFMSMEN 0x0
#define FMRSTB 0x2 /* MXVR FMPLL Reset */
-#define nFMRSTB 0x0
#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */
-#define nFMSVCO 0x0
#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */
#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */
#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */
/* Bit masks for MXVR_PIN_CTL */
#define MTXONBOD 0x1 /* MTXONB Open Drain Select */
-#define nMTXONBOD 0x0
#define MTXONBG 0x2 /* MTXONB Gates MTX Select */
-#define nMTXONBG 0x0
#define MFSOE 0x10 /* MFS Output Enable */
-#define nMFSOE 0x0
#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */
-#define nMFSGPSEL 0x0
#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */
-#define nMFSGPDAT 0x0
/* Bit masks for MXVR_SCLK_CNT */
/* Bit masks for KPAD_CTL */
#define KPAD_EN 0x1 /* Keypad Enable */
-#define nKPAD_EN 0x0
#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
#define KPAD_COLEN 0xe000 /* Column Enable Width */
/* Bit masks for KPAD_STAT */
#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
-#define nKPAD_IRQ 0x0
#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
#define KPAD_PRESSED 0x8 /* Key press current status */
-#define nKPAD_PRESSED 0x0
/* Bit masks for KPAD_SOFTEVAL */
#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
-#define nKPAD_SOFTEVAL_E 0x0
/* Bit masks for SDH_COMMAND */
#define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP 0x40 /* Response */
-#define nCMD_RSP 0x0
#define CMD_L_RSP 0x80 /* Long Response */
-#define nCMD_L_RSP 0x0
#define CMD_INT_E 0x100 /* Command Interrupt */
-#define nCMD_INT_E 0x0
#define CMD_PEND_E 0x200 /* Command Pending */
-#define nCMD_PEND_E 0x0
#define CMD_E 0x400 /* Command Enable */
-#define nCMD_E 0x0
/* Bit masks for SDH_PWR_CTL */
#define TBD 0x3c /* TBD */
#endif
#define SD_CMD_OD 0x40 /* Open Drain Output */
-#define nSD_CMD_OD 0x0
#define ROD_CTL 0x80 /* Rod Control */
-#define nROD_CTL 0x0
/* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
-#define nCLK_E 0x0
#define PWR_SV_E 0x200 /* Power Save Enable */
-#define nPWR_SV_E 0x0
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
-#define nCLKDIV_BYPASS 0x0
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
-#define nWIDE_BUS 0x0
/* Bit masks for SDH_RESP_CMD */
/* Bit masks for SDH_DATA_CTL */
#define DTX_E 0x1 /* Data Transfer Enable */
-#define nDTX_E 0x0
#define DTX_DIR 0x2 /* Data Transfer Direction */
-#define nDTX_DIR 0x0
#define DTX_MODE 0x4 /* Data Transfer Mode */
-#define nDTX_MODE 0x0
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
-#define nDTX_DMA_E 0x0
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
/* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
-#define nCMD_CRC_FAIL 0x0
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
-#define nDAT_CRC_FAIL 0x0
-#define CMD_TIMEOUT 0x4 /* CMD Time Out */
-#define nCMD_TIMEOUT 0x0
-#define DAT_TIMEOUT 0x8 /* Data Time Out */
-#define nDAT_TIMEOUT 0x0
+#define CMD_TIME_OUT 0x4 /* CMD Time Out */
+#define DAT_TIME_OUT 0x8 /* Data Time Out */
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
-#define nTX_UNDERRUN 0x0
#define RX_OVERRUN 0x20 /* Receive Overrun */
-#define nRX_OVERRUN 0x0
#define CMD_RESP_END 0x40 /* CMD Response End */
-#define nCMD_RESP_END 0x0
#define CMD_SENT 0x80 /* CMD Sent */
-#define nCMD_SENT 0x0
#define DAT_END 0x100 /* Data End */
-#define nDAT_END 0x0
#define START_BIT_ERR 0x200 /* Start Bit Error */
-#define nSTART_BIT_ERR 0x0
#define DAT_BLK_END 0x400 /* Data Block End */
-#define nDAT_BLK_END 0x0
#define CMD_ACT 0x800 /* CMD Active */
-#define nCMD_ACT 0x0
#define TX_ACT 0x1000 /* Transmit Active */
-#define nTX_ACT 0x0
#define RX_ACT 0x2000 /* Receive Active */
-#define nRX_ACT 0x0
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
-#define nTX_FIFO_STAT 0x0
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
-#define nRX_FIFO_STAT 0x0
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
-#define nTX_FIFO_FULL 0x0
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
-#define nRX_FIFO_FULL 0x0
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
-#define nTX_FIFO_ZERO 0x0
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
-#define nRX_DAT_ZERO 0x0
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
-#define nTX_DAT_RDY 0x0
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
-#define nRX_FIFO_RDY 0x0
/* Bit masks for SDH_STATUS_CLR */
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
-#define nCMD_CRC_FAIL_STAT 0x0
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
-#define nDAT_CRC_FAIL_STAT 0x0
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
-#define nCMD_TIMEOUT_STAT 0x0
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
-#define nDAT_TIMEOUT_STAT 0x0
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
-#define nTX_UNDERRUN_STAT 0x0
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
-#define nRX_OVERRUN_STAT 0x0
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
-#define nCMD_RESP_END_STAT 0x0
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
-#define nCMD_SENT_STAT 0x0
#define DAT_END_STAT 0x100 /* Data End Status */
-#define nDAT_END_STAT 0x0
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
-#define nSTART_BIT_ERR_STAT 0x0
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
-#define nDAT_BLK_END_STAT 0x0
/* Bit masks for SDH_MASK0 */
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
-#define nCMD_CRC_FAIL_MASK 0x0
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
-#define nDAT_CRC_FAIL_MASK 0x0
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
-#define nCMD_TIMEOUT_MASK 0x0
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
-#define nDAT_TIMEOUT_MASK 0x0
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
-#define nTX_UNDERRUN_MASK 0x0
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
-#define nRX_OVERRUN_MASK 0x0
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
-#define nCMD_RESP_END_MASK 0x0
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
-#define nCMD_SENT_MASK 0x0
#define DAT_END_MASK 0x100 /* Data End Mask */
-#define nDAT_END_MASK 0x0
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
-#define nSTART_BIT_ERR_MASK 0x0
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
-#define nDAT_BLK_END_MASK 0x0
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
-#define nCMD_ACT_MASK 0x0
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
-#define nTX_ACT_MASK 0x0
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
-#define nRX_ACT_MASK 0x0
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
-#define nTX_FIFO_STAT_MASK 0x0
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
-#define nRX_FIFO_STAT_MASK 0x0
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
-#define nTX_FIFO_FULL_MASK 0x0
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
-#define nRX_FIFO_FULL_MASK 0x0
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
-#define nTX_FIFO_ZERO_MASK 0x0
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
-#define nRX_DAT_ZERO_MASK 0x0
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
-#define nTX_DAT_RDY_MASK 0x0
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
-#define nRX_FIFO_RDY_MASK 0x0
/* Bit masks for SDH_FIFO_CNT */
/* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
-#define nSDIO_INT_DET 0x0
#define SD_CARD_DET 0x10 /* SD Card Detect */
-#define nSD_CARD_DET 0x0
/* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
-#define nSDIO_MSK 0x0
#define SCD_MSK 0x40 /* Mask Card Detect */
-#define nSCD_MSK 0x0
/* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */
-#define nCLKS_EN 0x0
#define SD4E 0x4 /* SDIO 4-Bit Enable */
-#define nSD4E 0x0
#define MWE 0x8 /* Moving Window Enable */
-#define nMWE 0x0
#define SD_RST 0x10 /* SDMMC Reset */
-#define nSD_RST 0x0
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
-#define nPUP_SDDAT 0x0
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
-#define nPUP_SDDAT3 0x0
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
-#define nPD_SDDAT3 0x0
/* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */
-#define nRWR 0x0
/* Bit masks for ATAPI_CONTROL */
#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define nPIO_START 0x0
#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define nMULTI_START 0x0
#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define nULTRA_START 0x0
#define XFER_DIR 0x8 /* Transfer Direction */
-#define nXFER_DIR 0x0
#define IORDY_EN 0x10 /* IORDY Enable */
-#define nIORDY_EN 0x0
#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define nFIFO_FLUSH 0x0
#define SOFT_RST 0x40 /* Soft Reset */
-#define nSOFT_RST 0x0
#define DEV_RST 0x80 /* Device Reset */
-#define nDEV_RST 0x0
#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define nTFRCNT_RST 0x0
#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define nEND_ON_TERM 0x0
#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define nPIO_USE_DMA 0x0
#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
/* Bit masks for ATAPI_STATUS */
#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define nPIO_XFER_ON 0x0
#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define nMULTI_XFER_ON 0x0
#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define nULTRA_XFER_ON 0x0
#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
/* Bit masks for ATAPI_DEV_ADDR */
/* Bit masks for ATAPI_INT_MASK */
#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define nATAPI_DEV_INT_MASK 0x0
#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define nPIO_DONE_MASK 0x0
#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define nMULTI_DONE_MASK 0x0
#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define nUDMAIN_DONE_MASK 0x0
#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define nUDMAOUT_DONE_MASK 0x0
#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define nHOST_TERM_XFER_MASK 0x0
#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define nMULTI_TERM_MASK 0x0
#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define nUDMAIN_TERM_MASK 0x0
#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-#define nUDMAOUT_TERM_MASK 0x0
/* Bit masks for ATAPI_INT_STATUS */
#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define nATAPI_DEV_INT 0x0
#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define nPIO_DONE_INT 0x0
#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define nMULTI_DONE_INT 0x0
#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define nUDMAIN_DONE_INT 0x0
#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define nUDMAOUT_DONE_INT 0x0
#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define nHOST_TERM_XFER_INT 0x0
#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define nMULTI_TERM_INT 0x0
#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define nUDMAIN_TERM_INT 0x0
#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-#define nUDMAOUT_TERM_INT 0x0
/* Bit masks for ATAPI_LINE_STATUS */
#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define nATAPI_INTR 0x0
#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define nATAPI_DASP 0x0
#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define nATAPI_CS0N 0x0
#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define nATAPI_CS1N 0x0
#define ATAPI_ADDR 0x70 /* ATAPI address line status */
#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define nATAPI_DMAREQ 0x0
#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define nATAPI_DMAACKN 0x0
#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define nATAPI_DIOWN 0x0
#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define nATAPI_DIORN 0x0
#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-#define nATAPI_IORDY 0x0
/* Bit masks for ATAPI_SM_STATE */
/* Bit masks for ATAPI_TERMINATE */
#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-#define nATAPI_HOST_TERM 0x0
/* Bit masks for ATAPI_REG_TIM_0 */
/* Bit masks for TIMER_ENABLE1 */
#define TIMEN8 0x1 /* Timer 8 Enable */
-#define nTIMEN8 0x0
#define TIMEN9 0x2 /* Timer 9 Enable */
-#define nTIMEN9 0x0
#define TIMEN10 0x4 /* Timer 10 Enable */
-#define nTIMEN10 0x0
/* Bit masks for TIMER_DISABLE1 */
#define TIMDIS8 0x1 /* Timer 8 Disable */
-#define nTIMDIS8 0x0
#define TIMDIS9 0x2 /* Timer 9 Disable */
-#define nTIMDIS9 0x0
#define TIMDIS10 0x4 /* Timer 10 Disable */
-#define nTIMDIS10 0x0
/* Bit masks for TIMER_STATUS1 */
#define TIMIL8 0x1 /* Timer 8 Interrupt */
-#define nTIMIL8 0x0
#define TIMIL9 0x2 /* Timer 9 Interrupt */
-#define nTIMIL9 0x0
#define TIMIL10 0x4 /* Timer 10 Interrupt */
-#define nTIMIL10 0x0
#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
-#define nTOVF_ERR8 0x0
#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
-#define nTOVF_ERR9 0x0
#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
-#define nTOVF_ERR10 0x0
#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
-#define nTRUN8 0x0
#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
-#define nTRUN9 0x0
#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
-#define nTRUN10 0x0
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
/* Bit masks for USB_POWER */
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define nENABLE_SUSPENDM 0x0
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define nSUSPEND_MODE 0x0
#define RESUME_MODE 0x4 /* DMA Mode */
-#define nRESUME_MODE 0x0
#define RESET 0x8 /* Reset indicator */
-#define nRESET 0x0
#define HS_MODE 0x10 /* High Speed mode indicator */
-#define nHS_MODE 0x0
#define HS_ENABLE 0x20 /* high Speed Enable */
-#define nHS_ENABLE 0x0
#define SOFT_CONN 0x40 /* Soft connect */
-#define nSOFT_CONN 0x0
#define ISO_UPDATE 0x80 /* Isochronous update */
-#define nISO_UPDATE 0x0
/* Bit masks for USB_INTRTX */
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define nEP0_TX 0x0
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define nEP1_TX 0x0
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define nEP2_TX 0x0
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define nEP3_TX 0x0
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define nEP4_TX 0x0
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define nEP5_TX 0x0
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define nEP6_TX 0x0
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-#define nEP7_TX 0x0
/* Bit masks for USB_INTRRX */
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define nEP1_RX 0x0
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define nEP2_RX 0x0
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define nEP3_RX 0x0
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define nEP4_RX 0x0
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define nEP5_RX 0x0
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define nEP6_RX 0x0
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-#define nEP7_RX 0x0
/* Bit masks for USB_INTRTXE */
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define nEP0_TX_E 0x0
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define nEP1_TX_E 0x0
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define nEP2_TX_E 0x0
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define nEP3_TX_E 0x0
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define nEP4_TX_E 0x0
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define nEP5_TX_E 0x0
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define nEP6_TX_E 0x0
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-#define nEP7_TX_E 0x0
/* Bit masks for USB_INTRRXE */
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define nEP1_RX_E 0x0
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define nEP2_RX_E 0x0
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define nEP3_RX_E 0x0
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define nEP4_RX_E 0x0
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define nEP5_RX_E 0x0
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define nEP6_RX_E 0x0
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-#define nEP7_RX_E 0x0
/* Bit masks for USB_INTRUSB */
#define SUSPEND_B 0x1 /* Suspend indicator */
-#define nSUSPEND_B 0x0
#define RESUME_B 0x2 /* Resume indicator */
-#define nRESUME_B 0x0
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define nRESET_OR_BABLE_B 0x0
#define SOF_B 0x8 /* Start of frame */
-#define nSOF_B 0x0
#define CONN_B 0x10 /* Connection indicator */
-#define nCONN_B 0x0
#define DISCON_B 0x20 /* Disconnect indicator */
-#define nDISCON_B 0x0
#define SESSION_REQ_B 0x40 /* Session Request */
-#define nSESSION_REQ_B 0x0
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-#define nVBUS_ERROR_B 0x0
/* Bit masks for USB_INTRUSBE */
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define nSUSPEND_BE 0x0
#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define nRESUME_BE 0x0
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define nRESET_OR_BABLE_BE 0x0
#define SOF_BE 0x8 /* Start of frame int enable */
-#define nSOF_BE 0x0
#define CONN_BE 0x10 /* Connection indicator int enable */
-#define nCONN_BE 0x0
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define nDISCON_BE 0x0
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define nSESSION_REQ_BE 0x0
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-#define nVBUS_ERROR_BE 0x0
/* Bit masks for USB_FRAME */
/* Bit masks for USB_GLOBAL_CTL */
#define GLOBAL_ENA 0x1 /* enables USB module */
-#define nGLOBAL_ENA 0x0
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define nEP1_TX_ENA 0x0
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define nEP2_TX_ENA 0x0
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define nEP3_TX_ENA 0x0
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define nEP4_TX_ENA 0x0
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define nEP5_TX_ENA 0x0
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define nEP6_TX_ENA 0x0
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define nEP7_TX_ENA 0x0
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define nEP1_RX_ENA 0x0
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define nEP2_RX_ENA 0x0
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define nEP3_RX_ENA 0x0
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define nEP4_RX_ENA 0x0
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define nEP5_RX_ENA 0x0
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define nEP6_RX_ENA 0x0
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-#define nEP7_RX_ENA 0x0
/* Bit masks for USB_OTG_DEV_CTL */
#define SESSION 0x1 /* session indicator */
-#define nSESSION 0x0
#define HOST_REQ 0x2 /* Host negotiation request */
-#define nHOST_REQ 0x0
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define nHOST_MODE 0x0
#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define nVBUS0 0x0
#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define nVBUS1 0x0
#define LSDEV 0x20 /* Low-speed indicator */
-#define nLSDEV 0x0
#define FSDEV 0x40 /* Full or High-speed indicator */
-#define nFSDEV 0x0
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-#define nB_DEVICE 0x0
/* Bit masks for USB_OTG_VBUS_IRQ */
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define nDRIVE_VBUS_ON 0x0
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define nDRIVE_VBUS_OFF 0x0
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define nCHRG_VBUS_START 0x0
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define nCHRG_VBUS_END 0x0
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define nDISCHRG_VBUS_START 0x0
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-#define nDISCHRG_VBUS_END 0x0
/* Bit masks for USB_OTG_VBUS_MASK */
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define nDRIVE_VBUS_ON_ENA 0x0
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define nDRIVE_VBUS_OFF_ENA 0x0
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define nCHRG_VBUS_START_ENA 0x0
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define nCHRG_VBUS_END_ENA 0x0
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define nDISCHRG_VBUS_START_ENA 0x0
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-#define nDISCHRG_VBUS_END_ENA 0x0
/* Bit masks for USB_CSR0 */
#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define nRXPKTRDY 0x0
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define nTXPKTRDY 0x0
#define STALL_SENT 0x4 /* STALL handshake sent */
-#define nSTALL_SENT 0x0
#define DATAEND 0x8 /* Data end indicator */
-#define nDATAEND 0x0
#define SETUPEND 0x10 /* Setup end */
-#define nSETUPEND 0x0
#define SENDSTALL 0x20 /* Send STALL handshake */
-#define nSENDSTALL 0x0
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define nSERVICED_RXPKTRDY 0x0
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define nSERVICED_SETUPEND 0x0
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define nFLUSHFIFO 0x0
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define nSTALL_RECEIVED_H 0x0
#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define nSETUPPKT_H 0x0
#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define nERROR_H 0x0
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define nREQPKT_H 0x0
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define nSTATUSPKT_H 0x0
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-#define nNAK_TIMEOUT_H 0x0
/* Bit masks for USB_COUNT0 */
/* Bit masks for USB_TXCSR */
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define nTXPKTRDY_T 0x0
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define nFIFO_NOT_EMPTY_T 0x0
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define nUNDERRUN_T 0x0
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define nFLUSHFIFO_T 0x0
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define nSTALL_SEND_T 0x0
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define nSTALL_SENT_T 0x0
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_T 0x0
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define nINCOMPTX_T 0x0
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_T 0x0
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define nFORCE_DATATOGGLE_T 0x0
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_T 0x0
#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define nISO_T 0x0
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOSET_T 0x0
#define ERROR_TH 0x4 /* error condition host mode */
-#define nERROR_TH 0x0
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_TH 0x0
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-#define nNAK_TIMEOUT_TH 0x0
/* Bit masks for USB_TXCOUNT */
/* Bit masks for USB_RXCSR */
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define nRXPKTRDY_R 0x0
#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define nFIFO_FULL_R 0x0
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define nOVERRUN_R 0x0
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define nDATAERROR_R 0x0
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define nFLUSHFIFO_R 0x0
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define nSTALL_SEND_R 0x0
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define nSTALL_SENT_R 0x0
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_R 0x0
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define nINCOMPRX_R 0x0
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_R 0x0
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define nDISNYET_R 0x0
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_R 0x0
#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define nISO_R 0x0
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOCLEAR_R 0x0
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define nERROR_RH 0x0
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define nREQPKT_RH 0x0
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_RH 0x0
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define nINCOMPRX_RH 0x0
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define nDMAREQMODE_RH 0x0
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-#define nAUTOREQ_RH 0x0
/* Bit masks for USB_RXCOUNT */
/* Bit masks for USB_DMA_INTERRUPT */
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define nDMA0_INT 0x0
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define nDMA1_INT 0x0
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define nDMA2_INT 0x0
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define nDMA3_INT 0x0
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define nDMA4_INT 0x0
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define nDMA5_INT 0x0
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define nDMA6_INT 0x0
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-#define nDMA7_INT 0x0
/* Bit masks for USB_DMAxCONTROL */
#define DMA_ENA 0x1 /* DMA enable */
-#define nDMA_ENA 0x0
#define DIRECTION 0x2 /* direction of DMA transfer */
-#define nDIRECTION 0x0
#define MODE 0x4 /* DMA Bus error */
-#define nMODE 0x0
#define INT_ENA 0x8 /* Interrupt enable */
-#define nINT_ENA 0x0
#define EPNUM 0xf0 /* EP number */
#define BUSERROR 0x100 /* DMA Bus error */
-#define nBUSERROR 0x0
/* Bit masks for USB_DMAxADDRHIGH */
/* Bit masks for HMDMAx_CONTROL */
#define HMDMAEN 0x1 /* Handshake MDMA Enable */
-#define nHMDMAEN 0x0
#define REP 0x2 /* Handshake MDMA Request Polarity */
-#define nREP 0x0
#define UTE 0x8 /* Urgency Threshold Enable */
-#define nUTE 0x0
#define OIE 0x10 /* Overflow Interrupt Enable */
-#define nOIE 0x0
#define BDIE 0x20 /* Block Done Interrupt Enable */
-#define nBDIE 0x0
#define MBDI 0x40 /* Mask Block Done Interrupt */
-#define nMBDI 0x0
#define DRQ 0x300 /* Handshake MDMA Request Type */
#define RBC 0x1000 /* Force Reload of BCOUNT */
-#define nRBC 0x0
#define PS 0x2000 /* Pin Status */
-#define nPS 0x0
#define OI 0x4000 /* Overflow Interrupt Generated */
-#define nOI 0x0
#define BDI 0x8000 /* Block Done Interrupt Generated */
-#define nBDI 0x0
/* ******************************************* */
/* MULTI BIT MACRO ENUMERATIONS */
/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-#define CHIPID 0xffc00014
+#define CHIPID 0xffc00014
/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
/* and MULTI BIT READ MACROS */
/* ********************************************************** */
+/* SIC_IMASK Masks */
+#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
+#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
+
/* Bit masks for SIC_IAR0 */
-#define IRQ_PLL_WAKEUP 0x1 /* PLL Wakeup */
-#define nIRQ_PLL_WAKEUP 0x0
+#define PLL_WAKEUP 0x1 /* PLL Wakeup */
/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
-#define IRQ_DMA0_ERR 0x2 /* DMA Controller 0 Error */
-#define nIRQ_DMA0_ERR 0x0
-#define IRQ_EPPI0_ERR 0x4 /* EPPI0 Error */
-#define nIRQ_EPPI0_ERR 0x0
-#define IRQ_SPORT0_ERR 0x8 /* SPORT0 Error */
-#define nIRQ_SPORT0_ERR 0x0
-#define IRQ_SPORT1_ERR 0x10 /* SPORT1 Error */
-#define nIRQ_SPORT1_ERR 0x0
-#define IRQ_SPI0_ERR 0x20 /* SPI0 Error */
-#define nIRQ_SPI0_ERR 0x0
-#define IRQ_UART0_ERR 0x40 /* UART0 Error */
-#define nIRQ_UART0_ERR 0x0
-#define IRQ_RTC 0x80 /* Real-Time Clock */
-#define nIRQ_RTC 0x0
-#define IRQ_DMA12 0x100 /* DMA Channel 12 */
-#define nIRQ_DMA12 0x0
-#define IRQ_DMA0 0x200 /* DMA Channel 0 */
-#define nIRQ_DMA0 0x0
-#define IRQ_DMA1 0x400 /* DMA Channel 1 */
-#define nIRQ_DMA1 0x0
-#define IRQ_DMA2 0x800 /* DMA Channel 2 */
-#define nIRQ_DMA2 0x0
-#define IRQ_DMA3 0x1000 /* DMA Channel 3 */
-#define nIRQ_DMA3 0x0
-#define IRQ_DMA4 0x2000 /* DMA Channel 4 */
-#define nIRQ_DMA4 0x0
-#define IRQ_DMA6 0x4000 /* DMA Channel 6 */
-#define nIRQ_DMA6 0x0
-#define IRQ_DMA7 0x8000 /* DMA Channel 7 */
-#define nIRQ_DMA7 0x0
-#define IRQ_PINT0 0x80000 /* Pin Interrupt 0 */
-#define nIRQ_PINT0 0x0
-#define IRQ_PINT1 0x100000 /* Pin Interrupt 1 */
-#define nIRQ_PINT1 0x0
-#define IRQ_MDMA0 0x200000 /* Memory DMA Stream 0 */
-#define nIRQ_MDMA0 0x0
-#define IRQ_MDMA1 0x400000 /* Memory DMA Stream 1 */
-#define nIRQ_MDMA1 0x0
-#define IRQ_WDOG 0x800000 /* Watchdog Timer */
-#define nIRQ_WDOG 0x0
-#define IRQ_DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
-#define nIRQ_DMA1_ERR 0x0
-#define IRQ_SPORT2_ERR 0x2000000 /* SPORT2 Error */
-#define nIRQ_SPORT2_ERR 0x0
-#define IRQ_SPORT3_ERR 0x4000000 /* SPORT3 Error */
-#define nIRQ_SPORT3_ERR 0x0
-#define IRQ_MXVR_SD 0x8000000 /* MXVR Synchronous Data */
-#define nIRQ_MXVR_SD 0x0
-#define IRQ_SPI1_ERR 0x10000000 /* SPI1 Error */
-#define nIRQ_SPI1_ERR 0x0
-#define IRQ_SPI2_ERR 0x20000000 /* SPI2 Error */
-#define nIRQ_SPI2_ERR 0x0
-#define IRQ_UART1_ERR 0x40000000 /* UART1 Error */
-#define nIRQ_UART1_ERR 0x0
-#define IRQ_UART2_ERR 0x80000000 /* UART2 Error */
-#define nIRQ_UART2_ERR 0x0
+#define DMA0_ERR 0x2 /* DMA Controller 0 Error */
+#define EPPI0_ERR 0x4 /* EPPI0 Error */
+#define SPORT0_ERR 0x8 /* SPORT0 Error */
+#define SPORT1_ERR 0x10 /* SPORT1 Error */
+#define SPI0_ERR 0x20 /* SPI0 Error */
+#define UART0_ERR 0x40 /* UART0 Error */
+#define RTC 0x80 /* Real-Time Clock */
+#define DMA12 0x100 /* DMA Channel 12 */
+#define DMA0 0x200 /* DMA Channel 0 */
+#define DMA1 0x400 /* DMA Channel 1 */
+#define DMA2 0x800 /* DMA Channel 2 */
+#define DMA3 0x1000 /* DMA Channel 3 */
+#define DMA4 0x2000 /* DMA Channel 4 */
+#define DMA6 0x4000 /* DMA Channel 6 */
+#define DMA7 0x8000 /* DMA Channel 7 */
+#define PINT0 0x80000 /* Pin Interrupt 0 */
+#define PINT1 0x100000 /* Pin Interrupt 1 */
+#define MDMA0 0x200000 /* Memory DMA Stream 0 */
+#define MDMA1 0x400000 /* Memory DMA Stream 1 */
+#define WDOG 0x800000 /* Watchdog Timer */
+#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
+#define SPORT2_ERR 0x2000000 /* SPORT2 Error */
+#define SPORT3_ERR 0x4000000 /* SPORT3 Error */
+#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */
+#define SPI1_ERR 0x10000000 /* SPI1 Error */
+#define SPI2_ERR 0x20000000 /* SPI2 Error */
+#define UART1_ERR 0x40000000 /* UART1 Error */
+#define UART2_ERR 0x80000000 /* UART2 Error */
/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
-#define IRQ_CAN0_ERR 0x1 /* CAN0 Error */
-#define nIRQ_CAN0_ERR 0x0
-#define IRQ_DMA18 0x2 /* DMA Channel 18 */
-#define nIRQ_DMA18 0x0
-#define IRQ_DMA19 0x4 /* DMA Channel 19 */
-#define nIRQ_DMA19 0x0
-#define IRQ_DMA20 0x8 /* DMA Channel 20 */
-#define nIRQ_DMA20 0x0
-#define IRQ_DMA21 0x10 /* DMA Channel 21 */
-#define nIRQ_DMA21 0x0
-#define IRQ_DMA13 0x20 /* DMA Channel 13 */
-#define nIRQ_DMA13 0x0
-#define IRQ_DMA14 0x40 /* DMA Channel 14 */
-#define nIRQ_DMA14 0x0
-#define IRQ_DMA5 0x80 /* DMA Channel 5 */
-#define nIRQ_DMA5 0x0
-#define IRQ_DMA23 0x100 /* DMA Channel 23 */
-#define nIRQ_DMA23 0x0
-#define IRQ_DMA8 0x200 /* DMA Channel 8 */
-#define nIRQ_DMA8 0x0
-#define IRQ_DMA9 0x400 /* DMA Channel 9 */
-#define nIRQ_DMA9 0x0
-#define IRQ_DMA10 0x800 /* DMA Channel 10 */
-#define nIRQ_DMA10 0x0
-#define IRQ_DMA11 0x1000 /* DMA Channel 11 */
-#define nIRQ_DMA11 0x0
-#define IRQ_TWI0 0x2000 /* TWI0 */
-#define nIRQ_TWI0 0x0
-#define IRQ_TWI1 0x4000 /* TWI1 */
-#define nIRQ_TWI1 0x0
-#define IRQ_CAN0_RX 0x8000 /* CAN0 Receive */
-#define nIRQ_CAN0_RX 0x0
-#define IRQ_CAN0_TX 0x10000 /* CAN0 Transmit */
-#define nIRQ_CAN0_TX 0x0
-#define IRQ_MDMA2 0x20000 /* Memory DMA Stream 0 */
-#define nIRQ_MDMA2 0x0
-#define IRQ_MDMA3 0x40000 /* Memory DMA Stream 1 */
-#define nIRQ_MDMA3 0x0
-#define IRQ_MXVR_STAT 0x80000 /* MXVR Status */
-#define nIRQ_MXVR_STAT 0x0
-#define IRQ_MXVR_CM 0x100000 /* MXVR Control Message */
-#define nIRQ_MXVR_CM 0x0
-#define IRQ_MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
-#define nIRQ_MXVR_AP 0x0
-#define IRQ_EPPI1_ERR 0x400000 /* EPPI1 Error */
-#define nIRQ_EPPI1_ERR 0x0
-#define IRQ_EPPI2_ERR 0x800000 /* EPPI2 Error */
-#define nIRQ_EPPI2_ERR 0x0
-#define IRQ_UART3_ERR 0x1000000 /* UART3 Error */
-#define nIRQ_UART3_ERR 0x0
-#define IRQ_HOST_ERR 0x2000000 /* Host DMA Port Error */
-#define nIRQ_HOST_ERR 0x0
-#define IRQ_USB_ERR 0x4000000 /* USB Error */
-#define nIRQ_USB_ERR 0x0
-#define IRQ_PIXC_ERR 0x8000000 /* Pixel Compositor Error */
-#define nIRQ_PIXC_ERR 0x0
-#define IRQ_NFC_ERR 0x10000000 /* Nand Flash Controller Error */
-#define nIRQ_NFC_ERR 0x0
-#define IRQ_ATAPI_ERR 0x20000000 /* ATAPI Error */
-#define nIRQ_ATAPI_ERR 0x0
-#define IRQ_CAN1_ERR 0x40000000 /* CAN1 Error */
-#define nIRQ_CAN1_ERR 0x0
-#define IRQ_DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
-#define nIRQ_DMAR0_ERR 0x0
-#define IRQ_DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
-#define nIRQ_DMAR1_ERR 0x0
-#define IRQ_DMAR0 0x80000000 /* DMAR0 Block */
-#define nIRQ_DMAR0 0x0
-#define IRQ_DMAR1 0x80000000 /* DMAR1 Block */
-#define nIRQ_DMAR1 0x0
+#define CAN0_ERR 0x1 /* CAN0 Error */
+#define DMA18 0x2 /* DMA Channel 18 */
+#define DMA19 0x4 /* DMA Channel 19 */
+#define DMA20 0x8 /* DMA Channel 20 */
+#define DMA21 0x10 /* DMA Channel 21 */
+#define DMA13 0x20 /* DMA Channel 13 */
+#define DMA14 0x40 /* DMA Channel 14 */
+#define DMA5 0x80 /* DMA Channel 5 */
+#define DMA23 0x100 /* DMA Channel 23 */
+#define DMA8 0x200 /* DMA Channel 8 */
+#define DMA9 0x400 /* DMA Channel 9 */
+#define DMA10 0x800 /* DMA Channel 10 */
+#define DMA11 0x1000 /* DMA Channel 11 */
+#define TWI0 0x2000 /* TWI0 */
+#define TWI1 0x4000 /* TWI1 */
+#define CAN0_RX 0x8000 /* CAN0 Receive */
+#define CAN0_TX 0x10000 /* CAN0 Transmit */
+#define MDMA2 0x20000 /* Memory DMA Stream 0 */
+#define MDMA3 0x40000 /* Memory DMA Stream 1 */
+#define MXVR_STAT 0x80000 /* MXVR Status */
+#define MXVR_CM 0x100000 /* MXVR Control Message */
+#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
+#define EPPI1_ERR 0x400000 /* EPPI1 Error */
+#define EPPI2_ERR 0x800000 /* EPPI2 Error */
+#define UART3_ERR 0x1000000 /* UART3 Error */
+#define HOST_ERR 0x2000000 /* Host DMA Port Error */
+#define USB_ERR 0x4000000 /* USB Error */
+#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */
+#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */
+#define ATAPI_ERR 0x20000000 /* ATAPI Error */
+#define CAN1_ERR 0x40000000 /* CAN1 Error */
+#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
+#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
+#define DMAR0 0x80000000 /* DMAR0 Block */
+#define DMAR1 0x80000000 /* DMAR1 Block */
/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
-#define IRQ_DMA15 0x1 /* DMA Channel 15 */
-#define nIRQ_DMA15 0x0
-#define IRQ_DMA16 0x2 /* DMA Channel 16 */
-#define nIRQ_DMA16 0x0
-#define IRQ_DMA17 0x4 /* DMA Channel 17 */
-#define nIRQ_DMA17 0x0
-#define IRQ_DMA22 0x8 /* DMA Channel 22 */
-#define nIRQ_DMA22 0x0
-#define IRQ_CNT 0x10 /* Counter */
-#define nIRQ_CNT 0x0
-#define IRQ_KEY 0x20 /* Keypad */
-#define nIRQ_KEY 0x0
-#define IRQ_CAN1_RX 0x40 /* CAN1 Receive */
-#define nIRQ_CAN1_RX 0x0
-#define IRQ_CAN1_TX 0x80 /* CAN1 Transmit */
-#define nIRQ_CAN1_TX 0x0
-#define IRQ_SDH_MASK0 0x100 /* SDH Mask 0 */
-#define nIRQ_SDH_MASK0 0x0
-#define IRQ_SDH_MASK1 0x200 /* SDH Mask 1 */
-#define nIRQ_SDH_MASK1 0x0
-#define IRQ_USB_EINT 0x400 /* USB Exception */
-#define nIRQ_USB_EINT 0x0
-#define IRQ_USB_INT0 0x800 /* USB Interrupt 0 */
-#define nIRQ_USB_INT0 0x0
-#define IRQ_USB_INT1 0x1000 /* USB Interrupt 1 */
-#define nIRQ_USB_INT1 0x0
-#define IRQ_USB_INT2 0x2000 /* USB Interrupt 2 */
-#define nIRQ_USB_INT2 0x0
-#define IRQ_USB_DMAINT 0x4000 /* USB DMA */
-#define nIRQ_USB_DMAINT 0x0
-#define IRQ_OTPSEC 0x8000 /* OTP Access Complete */
-#define nIRQ_OTPSEC 0x0
-#define IRQ_TIMER0 0x400000 /* Timer 0 */
-#define nIRQ_TIMER0 0x0
-#define IRQ_TIMER1 0x800000 /* Timer 1 */
-#define nIRQ_TIMER1 0x0
-#define IRQ_TIMER2 0x1000000 /* Timer 2 */
-#define nIRQ_TIMER2 0x0
-#define IRQ_TIMER3 0x2000000 /* Timer 3 */
-#define nIRQ_TIMER3 0x0
-#define IRQ_TIMER4 0x4000000 /* Timer 4 */
-#define nIRQ_TIMER4 0x0
-#define IRQ_TIMER5 0x8000000 /* Timer 5 */
-#define nIRQ_TIMER5 0x0
-#define IRQ_TIMER6 0x10000000 /* Timer 6 */
-#define nIRQ_TIMER6 0x0
-#define IRQ_TIMER7 0x20000000 /* Timer 7 */
-#define nIRQ_TIMER7 0x0
-#define IRQ_PINT2 0x40000000 /* Pin Interrupt 2 */
-#define nIRQ_PINT2 0x0
-#define IRQ_PINT3 0x80000000 /* Pin Interrupt 3 */
-#define nIRQ_PINT3 0x0
+#define DMA15 0x1 /* DMA Channel 15 */
+#define DMA16 0x2 /* DMA Channel 16 */
+#define DMA17 0x4 /* DMA Channel 17 */
+#define DMA22 0x8 /* DMA Channel 22 */
+#define CNT 0x10 /* Counter */
+#define KEY 0x20 /* Keypad */
+#define CAN1_RX 0x40 /* CAN1 Receive */
+#define CAN1_TX 0x80 /* CAN1 Transmit */
+#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */
+#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */
+#define USB_EINT 0x400 /* USB Exception */
+#define USB_INT0 0x800 /* USB Interrupt 0 */
+#define USB_INT1 0x1000 /* USB Interrupt 1 */
+#define USB_INT2 0x2000 /* USB Interrupt 2 */
+#define USB_DMAINT 0x4000 /* USB DMA */
+#define OTPSEC 0x8000 /* OTP Access Complete */
+#define TIMER0 0x400000 /* Timer 0 */
+#define TIMER1 0x800000 /* Timer 1 */
+#define TIMER2 0x1000000 /* Timer 2 */
+#define TIMER3 0x2000000 /* Timer 3 */
+#define TIMER4 0x4000000 /* Timer 4 */
+#define TIMER5 0x8000000 /* Timer 5 */
+#define TIMER6 0x10000000 /* Timer 6 */
+#define TIMER7 0x20000000 /* Timer 7 */
+#define PINT2 0x40000000 /* Pin Interrupt 2 */
+#define PINT3 0x80000000 /* Pin Interrupt 3 */
/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
#define DMAEN 0x1 /* DMA Channel Enable */
-#define nDMAEN 0x0
#define WNR 0x2 /* DMA Direction */
-#define nWNR 0x0
-#define WDSIZE 0xc /* Transfer Word Size */
+#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */
+#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */
+#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */
#define DMA2D 0x10 /* DMA Mode */
-#define nDMA2D 0x0
#define RESTART 0x20 /* Work Unit Transitions */
-#define nRESTART 0x0
#define DI_SEL 0x40 /* Data Interrupt Timing Select */
-#define nDI_SEL 0x0
#define DI_EN 0x80 /* Data Interrupt Enable */
-#define nDI_EN 0x0
#define NDSIZE 0xf00 /* Flex Descriptor Size */
#define DMAFLOW 0xf000 /* Next Operation */
/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */
-#define nDMA_DONE 0x0
#define DMA_ERR 0x2 /* DMA Error Interrupt Status */
-#define nDMA_ERR 0x0
#define DFETCH 0x4 /* DMA Descriptor Fetch */
-#define nDFETCH 0x0
#define DMA_RUN 0x8 /* DMA Channel Running */
-#define nDMA_RUN 0x0
/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
#define CTYPE 0x40 /* DMA Channel Type */
-#define nCTYPE 0x0
#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
/* Bit masks for DMACx_TCPER */
/* Bit masks for DMAC1_PERIMUX */
#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
-#define nPMUXSDH 0x0
-/* Bit masks for EBIU_AMGCTL */
+/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
+/* EBIU_AMGCTL Masks */
+#define AMCKEN 0x0001 /* Enable CLKOUT */
+#define AMBEN_NONE 0x0000 /* All Banks Disabled */
+#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
+#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-#define AMCKEN 0x1 /* Async Memory Enable */
-#define nAMCKEN 0x0
-#define AMBEN 0xe /* Async bank enable */
/* Bit masks for EBIU_AMBCTL0 */
#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
-#define nB0RDYEN 0x0
#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
-#define nB0RDYPOL 0x0
#define B0TT 0xc /* Bank 0 transition time */
#define B0ST 0x30 /* Bank 0 Setup time */
#define B0HT 0xc0 /* Bank 0 Hold time */
#define B0RAT 0xf00 /* Bank 0 Read access time */
#define B0WAT 0xf000 /* Bank 0 write access time */
#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
-#define nB1RDYEN 0x0
#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
-#define nB1RDYPOL 0x0
#define B1TT 0xc0000 /* Bank 1 transition time */
#define B1ST 0x300000 /* Bank 1 Setup time */
#define B1HT 0xc00000 /* Bank 1 Hold time */
/* Bit masks for EBIU_AMBCTL1 */
#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
-#define nB2RDYEN 0x0
#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
-#define nB2RDYPOL 0x0
#define B2TT 0xc /* Bank 2 transition time */
#define B2ST 0x30 /* Bank 2 Setup time */
#define B2HT 0xc0 /* Bank 2 Hold time */
#define B2RAT 0xf00 /* Bank 2 Read access time */
#define B2WAT 0xf000 /* Bank 2 write access time */
#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
-#define nB3RDYEN 0x0
#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
-#define nB3RDYPOL 0x0
#define B3TT 0xc0000 /* Bank 3 transition time */
#define B3ST 0x300000 /* Bank 3 Setup time */
#define B3HT 0xc00000 /* Bank 3 Hold time */
/* Bit masks for EBIU_FCTL */
#define TESTSETLOCK 0x1 /* Test set lock */
-#define nTESTSETLOCK 0x0
#define BCLK 0x6 /* Burst clock frequency */
#define PGWS 0x38 /* Page wait states */
#define PGSZ 0x40 /* Page size */
-#define nPGSZ 0x0
#define RDDL 0x380 /* Read data delay */
/* Bit masks for EBIU_ARBSTAT */
#define ARBSTAT 0x1 /* Arbitration status */
-#define nARBSTAT 0x0
#define BGSTAT 0x2 /* Bus grant status */
-#define nBGSTAT 0x0
/* Bit masks for EBIU_DDRCTL0 */
#define BURSTLENGTH 0x7 /* Burst length */
#define CASLATENCY 0x70 /* CAS latency */
#define DLLRESET 0x100 /* DLL Reset */
-#define nDLLRESET 0x0
#define REGE 0x1000 /* Register mode enable */
-#define nREGE 0x0
/* Bit masks for EBIU_DDRCTL3 */
#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */
#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
-#define nDEB1_URGENT 0x0
#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
-#define nDEB2_URGENT 0x0
#define DEB3_URGENT 0x4000 /* DEB3 Urgent */
-#define nDEB3_URGENT 0x0
/* Bit masks for EBIU_ERRMST */
#define DEB1_ERROR 0x1 /* DEB1 Error */
-#define nDEB1_ERROR 0x0
#define DEB2_ERROR 0x2 /* DEB2 Error */
-#define nDEB2_ERROR 0x0
#define DEB3_ERROR 0x4 /* DEB3 Error */
-#define nDEB3_ERROR 0x0
#define CORE_ERROR 0x8 /* Core error */
-#define nCORE_ERROR 0x0
#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
-#define nDEB_MERROR 0x0
#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
-#define nDEB2_MERROR 0x0
#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
-#define nDEB3_MERROR 0x0
#define CORE_MERROR 0x80 /* Core Error (2nd) */
-#define nCORE_MERROR 0x0
/* Bit masks for EBIU_ERRADD */
/* Bit masks for EBIU_RSTCTL */
#define DDRSRESET 0x1 /* DDR soft reset */
-#define nDDRSRESET 0x0
#define PFTCHSRESET 0x4 /* DDR prefetch reset */
-#define nPFTCHSRESET 0x0
#define SRREQ 0x8 /* Self-refresh request */
-#define nSRREQ 0x0
#define SRACK 0x10 /* Self-refresh acknowledge */
-#define nSRACK 0x0
#define MDDRENABLE 0x20 /* Mobile DDR enable */
-#define nMDDRENABLE 0x0
/* Bit masks for EBIU_DDRBRC0 */
/* Bit masks for EBIU_DDRMCEN */
#define B0WCENABLE 0x1 /* Bank 0 write count enable */
-#define nB0WCENABLE 0x0
#define B1WCENABLE 0x2 /* Bank 1 write count enable */
-#define nB1WCENABLE 0x0
#define B2WCENABLE 0x4 /* Bank 2 write count enable */
-#define nB2WCENABLE 0x0
#define B3WCENABLE 0x8 /* Bank 3 write count enable */
-#define nB3WCENABLE 0x0
#define B4WCENABLE 0x10 /* Bank 4 write count enable */
-#define nB4WCENABLE 0x0
#define B5WCENABLE 0x20 /* Bank 5 write count enable */
-#define nB5WCENABLE 0x0
#define B6WCENABLE 0x40 /* Bank 6 write count enable */
-#define nB6WCENABLE 0x0
#define B7WCENABLE 0x80 /* Bank 7 write count enable */
-#define nB7WCENABLE 0x0
#define B0RCENABLE 0x100 /* Bank 0 read count enable */
-#define nB0RCENABLE 0x0
#define B1RCENABLE 0x200 /* Bank 1 read count enable */
-#define nB1RCENABLE 0x0
#define B2RCENABLE 0x400 /* Bank 2 read count enable */
-#define nB2RCENABLE 0x0
#define B3RCENABLE 0x800 /* Bank 3 read count enable */
-#define nB3RCENABLE 0x0
#define B4RCENABLE 0x1000 /* Bank 4 read count enable */
-#define nB4RCENABLE 0x0
#define B5RCENABLE 0x2000 /* Bank 5 read count enable */
-#define nB5RCENABLE 0x0
#define B6RCENABLE 0x4000 /* Bank 6 read count enable */
-#define nB6RCENABLE 0x0
#define B7RCENABLE 0x8000 /* Bank 7 read count enable */
-#define nB7RCENABLE 0x0
#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
-#define nROWACTCENABLE 0x0
#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
-#define nRWTCENABLE 0x0
#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
-#define nARCENABLE 0x0
#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
-#define nGC0ENABLE 0x0
#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
-#define nGC1ENABLE 0x0
#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
-#define nGC2ENABLE 0x0
#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
-#define nGC3ENABLE 0x0
#define GCCONTROL 0x3000000 /* DDR Grant Count Control */
/* Bit masks for EBIU_DDRMCCL */
#define CB0WCOUNT 0x1 /* Clear write count 0 */
-#define nCB0WCOUNT 0x0
#define CB1WCOUNT 0x2 /* Clear write count 1 */
-#define nCB1WCOUNT 0x0
#define CB2WCOUNT 0x4 /* Clear write count 2 */
-#define nCB2WCOUNT 0x0
#define CB3WCOUNT 0x8 /* Clear write count 3 */
-#define nCB3WCOUNT 0x0
#define CB4WCOUNT 0x10 /* Clear write count 4 */
-#define nCB4WCOUNT 0x0
#define CB5WCOUNT 0x20 /* Clear write count 5 */
-#define nCB5WCOUNT 0x0
#define CB6WCOUNT 0x40 /* Clear write count 6 */
-#define nCB6WCOUNT 0x0
#define CB7WCOUNT 0x80 /* Clear write count 7 */
-#define nCB7WCOUNT 0x0
#define CBRCOUNT 0x100 /* Clear read count 0 */
-#define nCBRCOUNT 0x0
#define CB1RCOUNT 0x200 /* Clear read count 1 */
-#define nCB1RCOUNT 0x0
#define CB2RCOUNT 0x400 /* Clear read count 2 */
-#define nCB2RCOUNT 0x0
#define CB3RCOUNT 0x800 /* Clear read count 3 */
-#define nCB3RCOUNT 0x0
#define CB4RCOUNT 0x1000 /* Clear read count 4 */
-#define nCB4RCOUNT 0x0
#define CB5RCOUNT 0x2000 /* Clear read count 5 */
-#define nCB5RCOUNT 0x0
#define CB6RCOUNT 0x4000 /* Clear read count 6 */
-#define nCB6RCOUNT 0x0
#define CB7RCOUNT 0x8000 /* Clear read count 7 */
-#define nCB7RCOUNT 0x0
#define CRACOUNT 0x10000 /* Clear row activation count */
-#define nCRACOUNT 0x0
#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
-#define nCRWTACOUNT 0x0
#define CARCOUNT 0x40000 /* Clear auto-refresh count */
-#define nCARCOUNT 0x0
#define CG0COUNT 0x100000 /* Clear grant count 0 */
-#define nCG0COUNT 0x0
#define CG1COUNT 0x200000 /* Clear grant count 1 */
-#define nCG1COUNT 0x0
#define CG2COUNT 0x400000 /* Clear grant count 2 */
-#define nCG2COUNT 0x0
#define CG3COUNT 0x800000 /* Clear grant count 3 */
-#define nCG3COUNT 0x0
/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
#define Px0 0x1 /* GPIO 0 */
-#define nPx0 0x0
#define Px1 0x2 /* GPIO 1 */
-#define nPx1 0x0
#define Px2 0x4 /* GPIO 2 */
-#define nPx2 0x0
#define Px3 0x8 /* GPIO 3 */
-#define nPx3 0x0
#define Px4 0x10 /* GPIO 4 */
-#define nPx4 0x0
#define Px5 0x20 /* GPIO 5 */
-#define nPx5 0x0
#define Px6 0x40 /* GPIO 6 */
-#define nPx6 0x0
#define Px7 0x80 /* GPIO 7 */
-#define nPx7 0x0
#define Px8 0x100 /* GPIO 8 */
-#define nPx8 0x0
#define Px9 0x200 /* GPIO 9 */
-#define nPx9 0x0
#define Px10 0x400 /* GPIO 10 */
-#define nPx10 0x0
#define Px11 0x800 /* GPIO 11 */
-#define nPx11 0x0
#define Px12 0x1000 /* GPIO 12 */
-#define nPx12 0x0
#define Px13 0x2000 /* GPIO 13 */
-#define nPx13 0x0
#define Px14 0x4000 /* GPIO 14 */
-#define nPx14 0x0
#define Px15 0x8000 /* GPIO 15 */
-#define nPx15 0x0
/* Bit masks for PORTA_MUX - PORTJ_MUX */
/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
#define IB0 0x1 /* Interrupt Bit 0 */
-#define nIB0 0x0
#define IB1 0x2 /* Interrupt Bit 1 */
-#define nIB1 0x0
#define IB2 0x4 /* Interrupt Bit 2 */
-#define nIB2 0x0
#define IB3 0x8 /* Interrupt Bit 3 */
-#define nIB3 0x0
#define IB4 0x10 /* Interrupt Bit 4 */
-#define nIB4 0x0
#define IB5 0x20 /* Interrupt Bit 5 */
-#define nIB5 0x0
#define IB6 0x40 /* Interrupt Bit 6 */
-#define nIB6 0x0
#define IB7 0x80 /* Interrupt Bit 7 */
-#define nIB7 0x0
#define IB8 0x100 /* Interrupt Bit 8 */
-#define nIB8 0x0
#define IB9 0x200 /* Interrupt Bit 9 */
-#define nIB9 0x0
#define IB10 0x400 /* Interrupt Bit 10 */
-#define nIB10 0x0
#define IB11 0x800 /* Interrupt Bit 11 */
-#define nIB11 0x0
#define IB12 0x1000 /* Interrupt Bit 12 */
-#define nIB12 0x0
#define IB13 0x2000 /* Interrupt Bit 13 */
-#define nIB13 0x0
#define IB14 0x4000 /* Interrupt Bit 14 */
-#define nIB14 0x0
#define IB15 0x8000 /* Interrupt Bit 15 */
-#define nIB15 0x0
/* Bit masks for TIMERx_CONFIG */
#define TMODE 0x3 /* Timer Mode */
#define PULSE_HI 0x4 /* Pulse Polarity */
-#define nPULSE_HI 0x0
#define PERIOD_CNT 0x8 /* Period Count */
-#define nPERIOD_CNT 0x0
#define IRQ_ENA 0x10 /* Interrupt Request Enable */
-#define nIRQ_ENA 0x0
#define TIN_SEL 0x20 /* Timer Input Select */
-#define nTIN_SEL 0x0
#define OUT_DIS 0x40 /* Output Pad Disable */
-#define nOUT_DIS 0x0
#define CLK_SEL 0x80 /* Timer Clock Select */
-#define nCLK_SEL 0x0
#define TOGGLE_HI 0x100 /* Toggle Mode */
-#define nTOGGLE_HI 0x0
#define EMU_RUN 0x200 /* Emulation Behavior Select */
-#define nEMU_RUN 0x0
#define ERR_TYP 0xc000 /* Error Type */
/* Bit masks for TIMER_ENABLE0 */
#define TIMEN0 0x1 /* Timer 0 Enable */
-#define nTIMEN0 0x0
#define TIMEN1 0x2 /* Timer 1 Enable */
-#define nTIMEN1 0x0
#define TIMEN2 0x4 /* Timer 2 Enable */
-#define nTIMEN2 0x0
#define TIMEN3 0x8 /* Timer 3 Enable */
-#define nTIMEN3 0x0
#define TIMEN4 0x10 /* Timer 4 Enable */
-#define nTIMEN4 0x0
#define TIMEN5 0x20 /* Timer 5 Enable */
-#define nTIMEN5 0x0
#define TIMEN6 0x40 /* Timer 6 Enable */
-#define nTIMEN6 0x0
#define TIMEN7 0x80 /* Timer 7 Enable */
-#define nTIMEN7 0x0
/* Bit masks for TIMER_DISABLE0 */
#define TIMDIS0 0x1 /* Timer 0 Disable */
-#define nTIMDIS0 0x0
#define TIMDIS1 0x2 /* Timer 1 Disable */
-#define nTIMDIS1 0x0
#define TIMDIS2 0x4 /* Timer 2 Disable */
-#define nTIMDIS2 0x0
#define TIMDIS3 0x8 /* Timer 3 Disable */
-#define nTIMDIS3 0x0
#define TIMDIS4 0x10 /* Timer 4 Disable */
-#define nTIMDIS4 0x0
#define TIMDIS5 0x20 /* Timer 5 Disable */
-#define nTIMDIS5 0x0
#define TIMDIS6 0x40 /* Timer 6 Disable */
-#define nTIMDIS6 0x0
#define TIMDIS7 0x80 /* Timer 7 Disable */
-#define nTIMDIS7 0x0
/* Bit masks for TIMER_STATUS0 */
#define TIMIL0 0x1 /* Timer 0 Interrupt */
-#define nTIMIL0 0x0
#define TIMIL1 0x2 /* Timer 1 Interrupt */
-#define nTIMIL1 0x0
#define TIMIL2 0x4 /* Timer 2 Interrupt */
-#define nTIMIL2 0x0
#define TIMIL3 0x8 /* Timer 3 Interrupt */
-#define nTIMIL3 0x0
#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
-#define nTOVF_ERR0 0x0
#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
-#define nTOVF_ERR1 0x0
#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
-#define nTOVF_ERR2 0x0
#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
-#define nTOVF_ERR3 0x0
#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
-#define nTRUN0 0x0
#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
-#define nTRUN1 0x0
#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
-#define nTRUN2 0x0
#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
-#define nTRUN3 0x0
#define TIMIL4 0x10000 /* Timer 4 Interrupt */
-#define nTIMIL4 0x0
#define TIMIL5 0x20000 /* Timer 5 Interrupt */
-#define nTIMIL5 0x0
#define TIMIL6 0x40000 /* Timer 6 Interrupt */
-#define nTIMIL6 0x0
#define TIMIL7 0x80000 /* Timer 7 Interrupt */
-#define nTIMIL7 0x0
#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
-#define nTOVF_ERR4 0x0
#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
-#define nTOVF_ERR5 0x0
#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
-#define nTOVF_ERR6 0x0
#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
-#define nTOVF_ERR7 0x0
#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define nTRUN4 0x0
#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define nTRUN5 0x0
#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define nTRUN6 0x0
#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-#define nTRUN7 0x0
/* Bit masks for WDOG_CTL */
#define WDEV 0x6 /* Watchdog Event */
#define WDEN 0xff0 /* Watchdog Enable */
#define WDRO 0x8000 /* Watchdog Rolled Over */
-#define nWDRO 0x0
/* Bit masks for CNT_CONFIG */
#define CNTE 0x1 /* Counter Enable */
-#define nCNTE 0x0
#define DEBE 0x2 /* Debounce Enable */
-#define nDEBE 0x0
#define CDGINV 0x10 /* CDG Pin Polarity Invert */
-#define nCDGINV 0x0
#define CUDINV 0x20 /* CUD Pin Polarity Invert */
-#define nCUDINV 0x0
#define CZMINV 0x40 /* CZM Pin Polarity Invert */
-#define nCZMINV 0x0
#define CNTMODE 0x700 /* Counter Operating Mode */
#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
-#define nZMZC 0x0
#define BNDMODE 0x3000 /* Boundary register Mode */
#define INPDIS 0x8000 /* CUG and CDG Input Disable */
-#define nINPDIS 0x0
/* Bit masks for CNT_IMASK */
#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
-#define nICIE 0x0
#define UCIE 0x2 /* Up count Interrupt Enable */
-#define nUCIE 0x0
#define DCIE 0x4 /* Down count Interrupt Enable */
-#define nDCIE 0x0
#define MINCIE 0x8 /* Min Count Interrupt Enable */
-#define nMINCIE 0x0
#define MAXCIE 0x10 /* Max Count Interrupt Enable */
-#define nMAXCIE 0x0
#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
-#define nCOV31IE 0x0
#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
-#define nCOV15IE 0x0
#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
-#define nCZEROIE 0x0
#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
-#define nCZMIE 0x0
#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
-#define nCZMEIE 0x0
#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
-#define nCZMZIE 0x0
/* Bit masks for CNT_STATUS */
#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
-#define nICII 0x0
#define UCII 0x2 /* Up count Interrupt Identifier */
-#define nUCII 0x0
#define DCII 0x4 /* Down count Interrupt Identifier */
-#define nDCII 0x0
#define MINCII 0x8 /* Min Count Interrupt Identifier */
-#define nMINCII 0x0
#define MAXCII 0x10 /* Max Count Interrupt Identifier */
-#define nMAXCII 0x0
#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
-#define nCOV31II 0x0
#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
-#define nCOV15II 0x0
#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
-#define nCZEROII 0x0
#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
-#define nCZMII 0x0
#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
-#define nCZMEII 0x0
#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
-#define nCZMZII 0x0
/* Bit masks for CNT_COMMAND */
#define W1LMIN 0xf0 /* Load Min Register */
#define W1LMAX 0xf00 /* Load Max Register */
#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
-#define nW1ZMONCE 0x0
/* Bit masks for CNT_DEBOUNCE */
/* Bit masks for RTC_ICTL */
#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */
-#define nSTOPWATCH_INTERRUPT_ENABLE 0x0
#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */
-#define nALARM_INTERRUPT_ENABLE 0x0
#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */
-#define nSECONDS_INTERRUPT_ENABLE 0x0
#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */
-#define nMINUTES_INTERRUPT_ENABLE 0x0
#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */
-#define nHOURS_INTERRUPT_ENABLE 0x0
#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */
-#define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x0
#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */
-#define nDAY_ALARM_INTERRUPT_ENABLE 0x0
#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */
-#define nWRITE_COMPLETE_INTERRUPT_ENABLE 0x0
/* Bit masks for RTC_ISTAT */
#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */
-#define nSTOPWATCH_EVENT_FLAG 0x0
#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */
-#define nALARM_EVENT_FLAG 0x0
#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */
-#define nSECONDS_EVENT_FLAG 0x0
#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */
-#define nMINUTES_EVENT_FLAG 0x0
#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */
-#define nHOURS_EVENT_FLAG 0x0
#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */
-#define nTWENTY_FOUR_HOURS_EVENT_FLAG 0x0
#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */
-#define nDAY_ALARM_EVENT_FLAG 0x0
#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */
-#define nWRITE_PENDING__STATUS 0x0
#define WRITE_COMPLETE 0x8000 /* Write Complete */
-#define nWRITE_COMPLETE 0x0
/* Bit masks for RTC_SWCNT */
/* Bit masks for RTC_PREN */
#define PREN 0x1 /* Prescaler Enable */
-#define nPREN 0x0
/* Bit masks for OTP_CONTROL */
#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
-#define nFIEN 0x0
#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
-#define nFTESTDEC 0x0
#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
-#define nFWRTEST 0x0
#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
-#define nFRDEN 0x0
#define FWREN 0x8000 /* OTP/Fuse Write Enable */
-#define nFWREN 0x0
/* Bit masks for OTP_BEN */
/* Bit masks for OTP_STATUS */
#define FCOMP 0x1 /* OTP/Fuse Access Complete */
-#define nFCOMP 0x0
#define FERROR 0x2 /* OTP/Fuse Access Error */
-#define nFERROR 0x0
#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
-#define nMMRGLOAD 0x0
#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
-#define nMMRGLOCK 0x0
#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
-#define nFPGMEN 0x0
/* Bit masks for OTP_TIMING */
/* Bit masks for SECURE_SYSSWT */
#define EMUDABL 0x1 /* Emulation Disable. */
-#define nEMUDABL 0x0
#define RSTDABL 0x2 /* Reset Disable */
-#define nRSTDABL 0x0
#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define nDMA0OVR 0x0
#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define nDMA1OVR 0x0
#define EMUOVR 0x4000 /* Emulation Override */
-#define nEMUOVR 0x0
#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define nOTPSEN 0x0
#define L2DABL 0x70000 /* L2 Memory Disable. */
/* Bit masks for SECURE_CONTROL */
#define SECURE0 0x1 /* SECURE 0 */
-#define nSECURE0 0x0
#define SECURE1 0x2 /* SECURE 1 */
-#define nSECURE1 0x0
#define SECURE2 0x4 /* SECURE 2 */
-#define nSECURE2 0x0
#define SECURE3 0x8 /* SECURE 3 */
-#define nSECURE3 0x0
/* Bit masks for SECURE_STATUS */
#define SECMODE 0x3 /* Secured Mode Control State */
#define NMI 0x4 /* Non Maskable Interrupt */
-#define nNMI 0x0
#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define nAFVALID 0x0
#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define nAFEXIT 0x0
#define SECSTAT 0xe0 /* Secure Status */
/* Bit masks for PLL_DIV */
#define MSEL 0x7e00 /* Multiplier Select */
#define BYPASS 0x100 /* PLL Bypass Enable */
-#define nBYPASS 0x0
#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */
-#define nOUTPUT_DELAY 0x0
#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */
-#define nINPUT_DELAY 0x0
#define PDWN 0x20 /* Power Down */
-#define nPDWN 0x0
#define STOPCK 0x8 /* Stop Clock */
-#define nSTOPCK 0x0
#define PLL_OFF 0x2 /* Disable PLL */
-#define nPLL_OFF 0x0
#define DF 0x1 /* Divide Frequency */
-#define nDF 0x0
/* Bit masks for PLL_STAT */
#define PLL_LOCKED 0x20 /* PLL Locked Status */
-#define nPLL_LOCKED 0x0
#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
-#define nACTIVE_PLLDISABLED 0x0
#define FULL_ON 0x2 /* Full-On Mode */
-#define nFULL_ON 0x0
#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */
-#define nACTIVE_PLLENABLED 0x0
#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */
-#define nRTCWS 0x0
#define CANWS 0x800 /* CAN Wake-Up Status */
-#define nCANWS 0x0
#define USBWS 0x2000 /* USB Wake-Up Status */
-#define nUSBWS 0x0
#define KPADWS 0x4000 /* Keypad Wake-Up Status */
-#define nKPADWS 0x0
#define ROTWS 0x8000 /* Rotary Wake-Up Status */
-#define nROTWS 0x0
#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
-#define nGPWS 0x0
/* Bit masks for VR_CTL */
#define GAIN 0xc /* Voltage Output Level Gain */
#define VLEV 0xf0 /* Internal Voltage Level */
#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */
-#define nSCKELOW 0x0
#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */
-#define nWAKE 0x0
#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */
-#define nCANWE 0x0
#define GPWE 0x400 /* General-Purpose Wake-Up Enable */
-#define nGPWE 0x0
#define USBWE 0x800 /* USB Wake-Up Enable */
-#define nUSBWE 0x0
#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
-#define nKPADWE 0x0
#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
-#define nROTWE 0x0
/* Bit masks for NFC_CTL */
#define WR_DLY 0xf /* Write Strobe Delay */
#define RD_DLY 0xf0 /* Read Strobe Delay */
#define NWIDTH 0x100 /* NAND Data Width */
-#define nNWIDTH 0x0
#define PG_SIZE 0x200 /* Page Size */
-#define nPG_SIZE 0x0
/* Bit masks for NFC_STAT */
#define NBUSY 0x1 /* Not Busy */
-#define nNBUSY 0x0
#define WB_FULL 0x2 /* Write Buffer Full */
-#define nWB_FULL 0x0
#define PG_WR_STAT 0x4 /* Page Write Pending */
-#define nPG_WR_STAT 0x0
#define PG_RD_STAT 0x8 /* Page Read Pending */
-#define nPG_RD_STAT 0x0
#define WB_EMPTY 0x10 /* Write Buffer Empty */
-#define nWB_EMPTY 0x0
/* Bit masks for NFC_IRQSTAT */
#define NBUSYIRQ 0x1 /* Not Busy IRQ */
-#define nNBUSYIRQ 0x0
#define WB_OVF 0x2 /* Write Buffer Overflow */
-#define nWB_OVF 0x0
#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
-#define nWB_EDGE 0x0
#define RD_RDY 0x8 /* Read Data Ready */
-#define nRD_RDY 0x0
#define WR_DONE 0x10 /* Page Write Done */
-#define nWR_DONE 0x0
/* Bit masks for NFC_IRQMASK */
#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
-#define nMASK_BUSYIRQ 0x0
#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
-#define nMASK_WBOVF 0x0
#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
-#define nMASK_WBEMPTY 0x0
#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
-#define nMASK_RDRDY 0x0
#define MASK_WRDONE 0x10 /* Mask Write Done */
-#define nMASK_WRDONE 0x0
/* Bit masks for NFC_RST */
#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
-#define nECC_RST 0x0
/* Bit masks for NFC_PGCTL */
#define PG_RD_START 0x1 /* Page Read Start */
-#define nPG_RD_START 0x0
#define PG_WR_START 0x2 /* Page Write Start */
-#define nPG_WR_START 0x0
/* Bit masks for NFC_ECC0 */
/* Bit masks for CAN0_CONTROL */
#define SRS 0x1 /* Software Reset */
-#define nSRS 0x0
#define DNM 0x2 /* DeviceNet Mode */
-#define nDNM 0x0
#define ABO 0x4 /* Auto Bus On */
-#define nABO 0x0
#define WBA 0x10 /* Wakeup On CAN Bus Activity */
-#define nWBA 0x0
#define SMR 0x20 /* Sleep Mode Request */
-#define nSMR 0x0
#define CSR 0x40 /* CAN Suspend Mode Request */
-#define nCSR 0x0
#define CCR 0x80 /* CAN Configuration Mode Request */
-#define nCCR 0x0
/* Bit masks for CAN0_STATUS */
#define WT 0x1 /* CAN Transmit Warning Flag */
-#define nWT 0x0
#define WR 0x2 /* CAN Receive Warning Flag */
-#define nWR 0x0
#define EP 0x4 /* CAN Error Passive Mode */
-#define nEP 0x0
#define EBO 0x8 /* CAN Error Bus Off Mode */
-#define nEBO 0x0
#define CSA 0x40 /* CAN Suspend Mode Acknowledge */
-#define nCSA 0x0
#define CCA 0x80 /* CAN Configuration Mode Acknowledge */
-#define nCCA 0x0
#define MBPTR 0x1f00 /* Mailbox Pointer */
#define TRM 0x4000 /* Transmit Mode Status */
-#define nTRM 0x0
#define REC 0x8000 /* Receive Mode Status */
-#define nREC 0x0
/* Bit masks for CAN0_DEBUG */
#define DEC 0x1 /* Disable Transmit/Receive Error Counters */
-#define nDEC 0x0
#define DRI 0x2 /* Disable CANRX Input Pin */
-#define nDRI 0x0
#define DTO 0x4 /* Disable CANTX Output Pin */
-#define nDTO 0x0
#define DIL 0x8 /* Disable Internal Loop */
-#define nDIL 0x0
#define MAA 0x10 /* Mode Auto-Acknowledge */
-#define nMAA 0x0
#define MRB 0x20 /* Mode Read Back */
-#define nMRB 0x0
#define CDE 0x8000 /* CAN Debug Mode Enable */
-#define nCDE 0x0
/* Bit masks for CAN0_CLOCK */
#define SJW 0x300 /* Synchronization Jump Width */
#define SAM 0x80 /* Sampling */
-#define nSAM 0x0
#define TSEG2 0x70 /* Time Segment 2 */
#define TSEG1 0xf /* Time Segment 1 */
/* Bit masks for CAN0_INTR */
#define CANRX 0x80 /* Serial Input From Transceiver */
-#define nCANRX 0x0
#define CANTX 0x40 /* Serial Output To Transceiver */
-#define nCANTX 0x0
#define SMACK 0x8 /* Sleep Mode Acknowledge */
-#define nSMACK 0x0
#define GIRQ 0x4 /* Global Interrupt Request Status */
-#define nGIRQ 0x0
#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */
-#define nMBTIRQ 0x0
#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */
-#define nMBRIRQ 0x0
/* Bit masks for CAN0_GIM */
#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */
-#define nEWTIM 0x0
#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */
-#define nEWRIM 0x0
#define EPIM 0x4 /* Error Passive Interrupt Mask */
-#define nEPIM 0x0
#define BOIM 0x8 /* Bus Off Interrupt Mask */
-#define nBOIM 0x0
#define WUIM 0x10 /* Wakeup Interrupt Mask */
-#define nWUIM 0x0
#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */
-#define nUIAIM 0x0
#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */
-#define nAAIM 0x0
#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */
-#define nRMLIM 0x0
#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */
-#define nUCEIM 0x0
#define ADIM 0x400 /* Access Denied Interrupt Mask */
-#define nADIM 0x0
/* Bit masks for CAN0_GIS */
#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */
-#define nEWTIS 0x0
#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */
-#define nEWRIS 0x0
#define EPIS 0x4 /* Error Passive Interrupt Status */
-#define nEPIS 0x0
#define BOIS 0x8 /* Bus Off Interrupt Status */
-#define nBOIS 0x0
#define WUIS 0x10 /* Wakeup Interrupt Status */
-#define nWUIS 0x0
#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */
-#define nUIAIS 0x0
#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */
-#define nAAIS 0x0
#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */
-#define nRMLIS 0x0
#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */
-#define nUCEIS 0x0
#define ADIS 0x400 /* Access Denied Interrupt Status */
-#define nADIS 0x0
/* Bit masks for CAN0_GIF */
#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */
-#define nEWTIF 0x0
#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */
-#define nEWRIF 0x0
#define EPIF 0x4 /* Error Passive Interrupt Flag */
-#define nEPIF 0x0
#define BOIF 0x8 /* Bus Off Interrupt Flag */
-#define nBOIF 0x0
#define WUIF 0x10 /* Wakeup Interrupt Flag */
-#define nWUIF 0x0
#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */
-#define nUIAIF 0x0
#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */
-#define nAAIF 0x0
#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */
-#define nRMLIF 0x0
#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */
-#define nUCEIF 0x0
#define ADIF 0x400 /* Access Denied Interrupt Flag */
-#define nADIF 0x0
/* Bit masks for CAN0_MBTD */
#define TDR 0x80 /* Temporary Disable Request */
-#define nTDR 0x0
#define TDA 0x40 /* Temporary Disable Acknowledge */
-#define nTDA 0x0
#define TDPTR 0x1f /* Temporary Disable Pointer */
/* Bit masks for CAN0_UCCNF */
#define UCCNF 0xf /* Universal Counter Configuration */
#define UCRC 0x20 /* Universal Counter Reload/Clear */
-#define nUCRC 0x0
#define UCCT 0x40 /* Universal Counter CAN Trigger */
-#define nUCCT 0x0
#define UCE 0x80 /* Universal Counter Enable */
-#define nUCE 0x0
/* Bit masks for CAN0_UCCNT */
/* Bit masks for CAN0_ESR */
#define FER 0x80 /* Form Error */
-#define nFER 0x0
#define BEF 0x40 /* Bit Error Flag */
-#define nBEF 0x0
#define SA0 0x20 /* Stuck At Dominant */
-#define nSA0 0x0
#define CRCE 0x10 /* CRC Error */
-#define nCRCE 0x0
#define SER 0x8 /* Stuff Bit Error */
-#define nSER 0x0
#define ACKE 0x4 /* Acknowledge Error */
-#define nACKE 0x0
/* Bit masks for CAN0_EWR */
/* Bit masks for CAN0_AMxx_H */
#define FDF 0x8000 /* Filter On Data Field */
-#define nFDF 0x0
#define FMD 0x4000 /* Full Mask Data */
-#define nFMD 0x0
#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */
-#define nAMIDE 0x0
#define BASEID 0x1ffc /* Base Identifier */
#define EXTID_HI 0x3 /* Extended Identifier High Bits */
/* Bit masks for CAN0_MBxx_ID1 */
#define AME 0x8000 /* Acceptance Mask Enable */
-#define nAME 0x0
#define RTR 0x4000 /* Remote Transmission Request */
-#define nRTR 0x0
#define IDE 0x2000 /* Identifier Extension */
-#define nIDE 0x0
#define BASEID 0x1ffc /* Base Identifier */
#define EXTID_HI 0x3 /* Extended Identifier High Bits */
/* Bit masks for CAN0_MC1 */
#define MC0 0x1 /* Mailbox 0 Enable */
-#define nMC0 0x0
#define MC1 0x2 /* Mailbox 1 Enable */
-#define nMC1 0x0
#define MC2 0x4 /* Mailbox 2 Enable */
-#define nMC2 0x0
#define MC3 0x8 /* Mailbox 3 Enable */
-#define nMC3 0x0
#define MC4 0x10 /* Mailbox 4 Enable */
-#define nMC4 0x0
#define MC5 0x20 /* Mailbox 5 Enable */
-#define nMC5 0x0
#define MC6 0x40 /* Mailbox 6 Enable */
-#define nMC6 0x0
#define MC7 0x80 /* Mailbox 7 Enable */
-#define nMC7 0x0
#define MC8 0x100 /* Mailbox 8 Enable */
-#define nMC8 0x0
#define MC9 0x200 /* Mailbox 9 Enable */
-#define nMC9 0x0
#define MC10 0x400 /* Mailbox 10 Enable */
-#define nMC10 0x0
#define MC11 0x800 /* Mailbox 11 Enable */
-#define nMC11 0x0
#define MC12 0x1000 /* Mailbox 12 Enable */
-#define nMC12 0x0
#define MC13 0x2000 /* Mailbox 13 Enable */
-#define nMC13 0x0
#define MC14 0x4000 /* Mailbox 14 Enable */
-#define nMC14 0x0
#define MC15 0x8000 /* Mailbox 15 Enable */
-#define nMC15 0x0
/* Bit masks for CAN0_MC2 */
#define MC16 0x1 /* Mailbox 16 Enable */
-#define nMC16 0x0
#define MC17 0x2 /* Mailbox 17 Enable */
-#define nMC17 0x0
#define MC18 0x4 /* Mailbox 18 Enable */
-#define nMC18 0x0
#define MC19 0x8 /* Mailbox 19 Enable */
-#define nMC19 0x0
#define MC20 0x10 /* Mailbox 20 Enable */
-#define nMC20 0x0
#define MC21 0x20 /* Mailbox 21 Enable */
-#define nMC21 0x0
#define MC22 0x40 /* Mailbox 22 Enable */
-#define nMC22 0x0
#define MC23 0x80 /* Mailbox 23 Enable */
-#define nMC23 0x0
#define MC24 0x100 /* Mailbox 24 Enable */
-#define nMC24 0x0
#define MC25 0x200 /* Mailbox 25 Enable */
-#define nMC25 0x0
#define MC26 0x400 /* Mailbox 26 Enable */
-#define nMC26 0x0
#define MC27 0x800 /* Mailbox 27 Enable */
-#define nMC27 0x0
#define MC28 0x1000 /* Mailbox 28 Enable */
-#define nMC28 0x0
#define MC29 0x2000 /* Mailbox 29 Enable */
-#define nMC29 0x0
#define MC30 0x4000 /* Mailbox 30 Enable */
-#define nMC30 0x0
#define MC31 0x8000 /* Mailbox 31 Enable */
-#define nMC31 0x0
/* Bit masks for CAN0_MD1 */
#define MD0 0x1 /* Mailbox 0 Receive Enable */
-#define nMD0 0x0
#define MD1 0x2 /* Mailbox 1 Receive Enable */
-#define nMD1 0x0
#define MD2 0x4 /* Mailbox 2 Receive Enable */
-#define nMD2 0x0
#define MD3 0x8 /* Mailbox 3 Receive Enable */
-#define nMD3 0x0
#define MD4 0x10 /* Mailbox 4 Receive Enable */
-#define nMD4 0x0
#define MD5 0x20 /* Mailbox 5 Receive Enable */
-#define nMD5 0x0
#define MD6 0x40 /* Mailbox 6 Receive Enable */
-#define nMD6 0x0
#define MD7 0x80 /* Mailbox 7 Receive Enable */
-#define nMD7 0x0
#define MD8 0x100 /* Mailbox 8 Receive Enable */
-#define nMD8 0x0
#define MD9 0x200 /* Mailbox 9 Receive Enable */
-#define nMD9 0x0
#define MD10 0x400 /* Mailbox 10 Receive Enable */
-#define nMD10 0x0
#define MD11 0x800 /* Mailbox 11 Receive Enable */
-#define nMD11 0x0
#define MD12 0x1000 /* Mailbox 12 Receive Enable */
-#define nMD12 0x0
#define MD13 0x2000 /* Mailbox 13 Receive Enable */
-#define nMD13 0x0
#define MD14 0x4000 /* Mailbox 14 Receive Enable */
-#define nMD14 0x0
#define MD15 0x8000 /* Mailbox 15 Receive Enable */
-#define nMD15 0x0
/* Bit masks for CAN0_MD2 */
#define MD16 0x1 /* Mailbox 16 Receive Enable */
-#define nMD16 0x0
#define MD17 0x2 /* Mailbox 17 Receive Enable */
-#define nMD17 0x0
#define MD18 0x4 /* Mailbox 18 Receive Enable */
-#define nMD18 0x0
#define MD19 0x8 /* Mailbox 19 Receive Enable */
-#define nMD19 0x0
#define MD20 0x10 /* Mailbox 20 Receive Enable */
-#define nMD20 0x0
#define MD21 0x20 /* Mailbox 21 Receive Enable */
-#define nMD21 0x0
#define MD22 0x40 /* Mailbox 22 Receive Enable */
-#define nMD22 0x0
#define MD23 0x80 /* Mailbox 23 Receive Enable */
-#define nMD23 0x0
#define MD24 0x100 /* Mailbox 24 Receive Enable */
-#define nMD24 0x0
#define MD25 0x200 /* Mailbox 25 Receive Enable */
-#define nMD25 0x0
#define MD26 0x400 /* Mailbox 26 Receive Enable */
-#define nMD26 0x0
#define MD27 0x800 /* Mailbox 27 Receive Enable */
-#define nMD27 0x0
#define MD28 0x1000 /* Mailbox 28 Receive Enable */
-#define nMD28 0x0
#define MD29 0x2000 /* Mailbox 29 Receive Enable */
-#define nMD29 0x0
#define MD30 0x4000 /* Mailbox 30 Receive Enable */
-#define nMD30 0x0
#define MD31 0x8000 /* Mailbox 31 Receive Enable */
-#define nMD31 0x0
/* Bit masks for CAN0_RMP1 */
#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */
-#define nRMP0 0x0
#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */
-#define nRMP1 0x0
#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */
-#define nRMP2 0x0
#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */
-#define nRMP3 0x0
#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */
-#define nRMP4 0x0
#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */
-#define nRMP5 0x0
#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */
-#define nRMP6 0x0
#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */
-#define nRMP7 0x0
#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */
-#define nRMP8 0x0
#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */
-#define nRMP9 0x0
#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */
-#define nRMP10 0x0
#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */
-#define nRMP11 0x0
#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */
-#define nRMP12 0x0
#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */
-#define nRMP13 0x0
#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */
-#define nRMP14 0x0
#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */
-#define nRMP15 0x0
/* Bit masks for CAN0_RMP2 */
#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */
-#define nRMP16 0x0
#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */
-#define nRMP17 0x0
#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */
-#define nRMP18 0x0
#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */
-#define nRMP19 0x0
#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */
-#define nRMP20 0x0
#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */
-#define nRMP21 0x0
#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */
-#define nRMP22 0x0
#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */
-#define nRMP23 0x0
#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */
-#define nRMP24 0x0
#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */
-#define nRMP25 0x0
#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */
-#define nRMP26 0x0
#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */
-#define nRMP27 0x0
#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */
-#define nRMP28 0x0
#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */
-#define nRMP29 0x0
#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */
-#define nRMP30 0x0
#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */
-#define nRMP31 0x0
/* Bit masks for CAN0_RML1 */
#define RML0 0x1 /* Mailbox 0 Receive Message Lost */
-#define nRML0 0x0
#define RML1 0x2 /* Mailbox 1 Receive Message Lost */
-#define nRML1 0x0
#define RML2 0x4 /* Mailbox 2 Receive Message Lost */
-#define nRML2 0x0
#define RML3 0x8 /* Mailbox 3 Receive Message Lost */
-#define nRML3 0x0
#define RML4 0x10 /* Mailbox 4 Receive Message Lost */
-#define nRML4 0x0
#define RML5 0x20 /* Mailbox 5 Receive Message Lost */
-#define nRML5 0x0
#define RML6 0x40 /* Mailbox 6 Receive Message Lost */
-#define nRML6 0x0
#define RML7 0x80 /* Mailbox 7 Receive Message Lost */
-#define nRML7 0x0
#define RML8 0x100 /* Mailbox 8 Receive Message Lost */
-#define nRML8 0x0
#define RML9 0x200 /* Mailbox 9 Receive Message Lost */
-#define nRML9 0x0
#define RML10 0x400 /* Mailbox 10 Receive Message Lost */
-#define nRML10 0x0
#define RML11 0x800 /* Mailbox 11 Receive Message Lost */
-#define nRML11 0x0
#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */
-#define nRML12 0x0
#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */
-#define nRML13 0x0
#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */
-#define nRML14 0x0
#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */
-#define nRML15 0x0
/* Bit masks for CAN0_RML2 */
#define RML16 0x1 /* Mailbox 16 Receive Message Lost */
-#define nRML16 0x0
#define RML17 0x2 /* Mailbox 17 Receive Message Lost */
-#define nRML17 0x0
#define RML18 0x4 /* Mailbox 18 Receive Message Lost */
-#define nRML18 0x0
#define RML19 0x8 /* Mailbox 19 Receive Message Lost */
-#define nRML19 0x0
#define RML20 0x10 /* Mailbox 20 Receive Message Lost */
-#define nRML20 0x0
#define RML21 0x20 /* Mailbox 21 Receive Message Lost */
-#define nRML21 0x0
#define RML22 0x40 /* Mailbox 22 Receive Message Lost */
-#define nRML22 0x0
#define RML23 0x80 /* Mailbox 23 Receive Message Lost */
-#define nRML23 0x0
#define RML24 0x100 /* Mailbox 24 Receive Message Lost */
-#define nRML24 0x0
#define RML25 0x200 /* Mailbox 25 Receive Message Lost */
-#define nRML25 0x0
#define RML26 0x400 /* Mailbox 26 Receive Message Lost */
-#define nRML26 0x0
#define RML27 0x800 /* Mailbox 27 Receive Message Lost */
-#define nRML27 0x0
#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */
-#define nRML28 0x0
#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */
-#define nRML29 0x0
#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */
-#define nRML30 0x0
#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */
-#define nRML31 0x0
/* Bit masks for CAN0_OPSS1 */
#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS0 0x0
#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS1 0x0
#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS2 0x0
#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS3 0x0
#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS4 0x0
#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS5 0x0
#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS6 0x0
#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS7 0x0
#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS8 0x0
#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS9 0x0
#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS10 0x0
#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS11 0x0
#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS12 0x0
#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS13 0x0
#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS14 0x0
#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS15 0x0
/* Bit masks for CAN0_OPSS2 */
#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS16 0x0
#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS17 0x0
#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS18 0x0
#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS19 0x0
#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS20 0x0
#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS21 0x0
#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS22 0x0
#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS23 0x0
#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS24 0x0
#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS25 0x0
#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS26 0x0
#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS27 0x0
#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS28 0x0
#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS29 0x0
#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS30 0x0
#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
-#define nOPSS31 0x0
/* Bit masks for CAN0_TRS1 */
#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */
-#define nTRS0 0x0
#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */
-#define nTRS1 0x0
#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */
-#define nTRS2 0x0
#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */
-#define nTRS3 0x0
#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */
-#define nTRS4 0x0
#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */
-#define nTRS5 0x0
#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */
-#define nTRS6 0x0
#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */
-#define nTRS7 0x0
#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */
-#define nTRS8 0x0
#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */
-#define nTRS9 0x0
#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */
-#define nTRS10 0x0
#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */
-#define nTRS11 0x0
#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */
-#define nTRS12 0x0
#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */
-#define nTRS13 0x0
#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */
-#define nTRS14 0x0
#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */
-#define nTRS15 0x0
/* Bit masks for CAN0_TRS2 */
#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */
-#define nTRS16 0x0
#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */
-#define nTRS17 0x0
#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */
-#define nTRS18 0x0
#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */
-#define nTRS19 0x0
#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */
-#define nTRS20 0x0
#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */
-#define nTRS21 0x0
#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */
-#define nTRS22 0x0
#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */
-#define nTRS23 0x0
#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */
-#define nTRS24 0x0
#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */
-#define nTRS25 0x0
#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */
-#define nTRS26 0x0
#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */
-#define nTRS27 0x0
#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */
-#define nTRS28 0x0
#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */
-#define nTRS29 0x0
#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */
-#define nTRS30 0x0
#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */
-#define nTRS31 0x0
/* Bit masks for CAN0_TRR1 */
#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */
-#define nTRR0 0x0
#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */
-#define nTRR1 0x0
#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */
-#define nTRR2 0x0
#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */
-#define nTRR3 0x0
#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */
-#define nTRR4 0x0
#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */
-#define nTRR5 0x0
#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */
-#define nTRR6 0x0
#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */
-#define nTRR7 0x0
#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */
-#define nTRR8 0x0
#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */
-#define nTRR9 0x0
#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */
-#define nTRR10 0x0
#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */
-#define nTRR11 0x0
#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */
-#define nTRR12 0x0
#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */
-#define nTRR13 0x0
#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */
-#define nTRR14 0x0
#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */
-#define nTRR15 0x0
/* Bit masks for CAN0_TRR2 */
#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */
-#define nTRR16 0x0
#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */
-#define nTRR17 0x0
#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */
-#define nTRR18 0x0
#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */
-#define nTRR19 0x0
#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */
-#define nTRR20 0x0
#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */
-#define nTRR21 0x0
#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */
-#define nTRR22 0x0
#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */
-#define nTRR23 0x0
#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */
-#define nTRR24 0x0
#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */
-#define nTRR25 0x0
#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */
-#define nTRR26 0x0
#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */
-#define nTRR27 0x0
#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */
-#define nTRR28 0x0
#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */
-#define nTRR29 0x0
#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */
-#define nTRR30 0x0
#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */
-#define nTRR31 0x0
/* Bit masks for CAN0_AA1 */
#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */
-#define nAA0 0x0
#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */
-#define nAA1 0x0
#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */
-#define nAA2 0x0
#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */
-#define nAA3 0x0
#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */
-#define nAA4 0x0
#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */
-#define nAA5 0x0
#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */
-#define nAA6 0x0
#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */
-#define nAA7 0x0
#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */
-#define nAA8 0x0
#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */
-#define nAA9 0x0
#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */
-#define nAA10 0x0
#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */
-#define nAA11 0x0
#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */
-#define nAA12 0x0
#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */
-#define nAA13 0x0
#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */
-#define nAA14 0x0
#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */
-#define nAA15 0x0
/* Bit masks for CAN0_AA2 */
#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */
-#define nAA16 0x0
#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */
-#define nAA17 0x0
#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */
-#define nAA18 0x0
#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */
-#define nAA19 0x0
#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */
-#define nAA20 0x0
#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */
-#define nAA21 0x0
#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */
-#define nAA22 0x0
#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */
-#define nAA23 0x0
#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */
-#define nAA24 0x0
#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */
-#define nAA25 0x0
#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */
-#define nAA26 0x0
#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */
-#define nAA27 0x0
#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */
-#define nAA28 0x0
#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */
-#define nAA29 0x0
#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */
-#define nAA30 0x0
#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */
-#define nAA31 0x0
/* Bit masks for CAN0_TA1 */
#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */
-#define nTA0 0x0
#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */
-#define nTA1 0x0
#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */
-#define nTA2 0x0
#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */
-#define nTA3 0x0
#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */
-#define nTA4 0x0
#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */
-#define nTA5 0x0
#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */
-#define nTA6 0x0
#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */
-#define nTA7 0x0
#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */
-#define nTA8 0x0
#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */
-#define nTA9 0x0
#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */
-#define nTA10 0x0
#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */
-#define nTA11 0x0
#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */
-#define nTA12 0x0
#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */
-#define nTA13 0x0
#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */
-#define nTA14 0x0
#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */
-#define nTA15 0x0
/* Bit masks for CAN0_TA2 */
#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */
-#define nTA16 0x0
#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */
-#define nTA17 0x0
#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */
-#define nTA18 0x0
#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */
-#define nTA19 0x0
#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */
-#define nTA20 0x0
#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */
-#define nTA21 0x0
#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */
-#define nTA22 0x0
#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */
-#define nTA23 0x0
#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */
-#define nTA24 0x0
#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */
-#define nTA25 0x0
#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */
-#define nTA26 0x0
#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */
-#define nTA27 0x0
#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */
-#define nTA28 0x0
#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */
-#define nTA29 0x0
#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */
-#define nTA30 0x0
#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */
-#define nTA31 0x0
/* Bit masks for CAN0_RFH1 */
#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */
-#define nRFH0 0x0
#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */
-#define nRFH1 0x0
#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */
-#define nRFH2 0x0
#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */
-#define nRFH3 0x0
#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */
-#define nRFH4 0x0
#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */
-#define nRFH5 0x0
#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */
-#define nRFH6 0x0
#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */
-#define nRFH7 0x0
#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */
-#define nRFH8 0x0
#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */
-#define nRFH9 0x0
#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */
-#define nRFH10 0x0
#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */
-#define nRFH11 0x0
#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */
-#define nRFH12 0x0
#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */
-#define nRFH13 0x0
#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */
-#define nRFH14 0x0
#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */
-#define nRFH15 0x0
/* Bit masks for CAN0_RFH2 */
#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */
-#define nRFH16 0x0
#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */
-#define nRFH17 0x0
#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */
-#define nRFH18 0x0
#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */
-#define nRFH19 0x0
#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */
-#define nRFH20 0x0
#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */
-#define nRFH21 0x0
#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */
-#define nRFH22 0x0
#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */
-#define nRFH23 0x0
#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */
-#define nRFH24 0x0
#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */
-#define nRFH25 0x0
#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */
-#define nRFH26 0x0
#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */
-#define nRFH27 0x0
#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */
-#define nRFH28 0x0
#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */
-#define nRFH29 0x0
#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */
-#define nRFH30 0x0
#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */
-#define nRFH31 0x0
/* Bit masks for CAN0_MBIM1 */
#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */
-#define nMBIM0 0x0
#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */
-#define nMBIM1 0x0
#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */
-#define nMBIM2 0x0
#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */
-#define nMBIM3 0x0
#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */
-#define nMBIM4 0x0
#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */
-#define nMBIM5 0x0
#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */
-#define nMBIM6 0x0
#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */
-#define nMBIM7 0x0
#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */
-#define nMBIM8 0x0
#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */
-#define nMBIM9 0x0
#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */
-#define nMBIM10 0x0
#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */
-#define nMBIM11 0x0
#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */
-#define nMBIM12 0x0
#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */
-#define nMBIM13 0x0
#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */
-#define nMBIM14 0x0
#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */
-#define nMBIM15 0x0
/* Bit masks for CAN0_MBIM2 */
#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */
-#define nMBIM16 0x0
#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */
-#define nMBIM17 0x0
#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */
-#define nMBIM18 0x0
#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */
-#define nMBIM19 0x0
#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */
-#define nMBIM20 0x0
#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */
-#define nMBIM21 0x0
#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */
-#define nMBIM22 0x0
#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */
-#define nMBIM23 0x0
#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */
-#define nMBIM24 0x0
#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */
-#define nMBIM25 0x0
#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */
-#define nMBIM26 0x0
#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */
-#define nMBIM27 0x0
#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */
-#define nMBIM28 0x0
#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */
-#define nMBIM29 0x0
#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */
-#define nMBIM30 0x0
#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */
-#define nMBIM31 0x0
/* Bit masks for CAN0_MBTIF1 */
#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */
-#define nMBTIF0 0x0
#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */
-#define nMBTIF1 0x0
#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */
-#define nMBTIF2 0x0
#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */
-#define nMBTIF3 0x0
#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */
-#define nMBTIF4 0x0
#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */
-#define nMBTIF5 0x0
#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */
-#define nMBTIF6 0x0
#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */
-#define nMBTIF7 0x0
#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */
-#define nMBTIF8 0x0
#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */
-#define nMBTIF9 0x0
#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */
-#define nMBTIF10 0x0
#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */
-#define nMBTIF11 0x0
#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */
-#define nMBTIF12 0x0
#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */
-#define nMBTIF13 0x0
#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */
-#define nMBTIF14 0x0
#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */
-#define nMBTIF15 0x0
/* Bit masks for CAN0_MBTIF2 */
#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */
-#define nMBTIF16 0x0
#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */
-#define nMBTIF17 0x0
#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */
-#define nMBTIF18 0x0
#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */
-#define nMBTIF19 0x0
#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */
-#define nMBTIF20 0x0
#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */
-#define nMBTIF21 0x0
#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */
-#define nMBTIF22 0x0
#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */
-#define nMBTIF23 0x0
#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */
-#define nMBTIF24 0x0
#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */
-#define nMBTIF25 0x0
#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */
-#define nMBTIF26 0x0
#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */
-#define nMBTIF27 0x0
#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */
-#define nMBTIF28 0x0
#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */
-#define nMBTIF29 0x0
#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */
-#define nMBTIF30 0x0
#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */
-#define nMBTIF31 0x0
/* Bit masks for CAN0_MBRIF1 */
#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */
-#define nMBRIF0 0x0
#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */
-#define nMBRIF1 0x0
#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */
-#define nMBRIF2 0x0
#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */
-#define nMBRIF3 0x0
#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */
-#define nMBRIF4 0x0
#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */
-#define nMBRIF5 0x0
#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */
-#define nMBRIF6 0x0
#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */
-#define nMBRIF7 0x0
#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */
-#define nMBRIF8 0x0
#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */
-#define nMBRIF9 0x0
#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */
-#define nMBRIF10 0x0
#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */
-#define nMBRIF11 0x0
#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */
-#define nMBRIF12 0x0
#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */
-#define nMBRIF13 0x0
#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */
-#define nMBRIF14 0x0
#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */
-#define nMBRIF15 0x0
/* Bit masks for CAN0_MBRIF2 */
#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */
-#define nMBRIF16 0x0
#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */
-#define nMBRIF17 0x0
#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */
-#define nMBRIF18 0x0
#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */
-#define nMBRIF19 0x0
#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */
-#define nMBRIF20 0x0
#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */
-#define nMBRIF21 0x0
#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */
-#define nMBRIF22 0x0
#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */
-#define nMBRIF23 0x0
#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */
-#define nMBRIF24 0x0
#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */
-#define nMBRIF25 0x0
#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */
-#define nMBRIF26 0x0
#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */
-#define nMBRIF27 0x0
#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */
-#define nMBRIF28 0x0
#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */
-#define nMBRIF29 0x0
#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */
-#define nMBRIF30 0x0
#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */
-#define nMBRIF31 0x0
/* Bit masks for EPPIx_STATUS */
#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
-#define nCFIFO_ERR 0x0
#define YFIFO_ERR 0x2 /* Luma FIFO Error */
-#define nYFIFO_ERR 0x0
#define LTERR_OVR 0x4 /* Line Track Overflow */
-#define nLTERR_OVR 0x0
#define LTERR_UNDR 0x8 /* Line Track Underflow */
-#define nLTERR_UNDR 0x0
#define FTERR_OVR 0x10 /* Frame Track Overflow */
-#define nFTERR_OVR 0x0
#define FTERR_UNDR 0x20 /* Frame Track Underflow */
-#define nFTERR_UNDR 0x0
#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
-#define nERR_NCOR 0x0
#define DMA1URQ 0x80 /* DMA1 Urgent Request */
-#define nDMA1URQ 0x0
#define DMA0URQ 0x100 /* DMA0 Urgent Request */
-#define nDMA0URQ 0x0
#define ERR_DET 0x4000 /* Preamble Error Detected */
-#define nERR_DET 0x0
#define FLD 0x8000 /* Field */
-#define nFLD 0x0
/* Bit masks for EPPIx_CONTROL */
#define EPPI_EN 0x1 /* Enable */
-#define nEPPI_EN 0x0
#define EPPI_DIR 0x2 /* Direction */
-#define nEPPI_DIR 0x0
#define XFR_TYPE 0xc /* Operating Mode */
#define FS_CFG 0x30 /* Frame Sync Configuration */
#define FLD_SEL 0x40 /* Field Select/Trigger */
-#define nFLD_SEL 0x0
#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */
-#define nITU_TYPE 0x0
#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */
-#define nBLANKGEN 0x0
#define ICLKGEN 0x200 /* Internal Clock Generation */
-#define nICLKGEN 0x0
#define IFSGEN 0x400 /* Internal Frame Sync Generation */
-#define nIFSGEN 0x0
#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */
#define POLS 0x6000 /* Frame Sync Polarity */
#define DLENGTH 0x38000 /* Data Length */
#define SKIP_EN 0x40000 /* Skip Enable */
-#define nSKIP_EN 0x0
#define SKIP_EO 0x80000 /* Skip Even or Odd */
-#define nSKIP_EO 0x0
#define PACKEN 0x100000 /* Packing/Unpacking Enable */
-#define nPACKEN 0x0
#define SWAPEN 0x200000 /* Swap Enable */
-#define nSWAPEN 0x0
#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */
-#define nSIGN_EXT 0x0
#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */
-#define nSPLT_EVEN_ODD 0x0
#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
-#define nSUBSPLT_ODD 0x0
#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */
-#define nDMACFG 0x0
#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */
-#define nRGB_FMT_EN 0x0
#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
/* Bit masks for SPIx_CTL */
#define SPE 0x4000 /* SPI Enable */
-#define nSPE 0x0
#define WOM 0x2000 /* Write Open Drain Master */
-#define nWOM 0x0
#define MSTR 0x1000 /* Master Mode */
-#define nMSTR 0x0
#define CPOL 0x800 /* Clock Polarity */
-#define nCPOL 0x0
#define CPHA 0x400 /* Clock Phase */
-#define nCPHA 0x0
#define LSBF 0x200 /* LSB First */
-#define nLSBF 0x0
#define SIZE 0x100 /* Size of Words */
-#define nSIZE 0x0
#define EMISO 0x20 /* Enable MISO Output */
-#define nEMISO 0x0
#define PSSE 0x10 /* Slave-Select Enable */
-#define nPSSE 0x0
#define GM 0x8 /* Get More Data */
-#define nGM 0x0
#define SZ 0x4 /* Send Zero */
-#define nSZ 0x0
#define TIMOD 0x3 /* Transfer Initiation Mode */
/* Bit masks for SPIx_FLG */
#define FLS1 0x2 /* Slave Select Enable 1 */
-#define nFLS1 0x0
#define FLS2 0x4 /* Slave Select Enable 2 */
-#define nFLS2 0x0
#define FLS3 0x8 /* Slave Select Enable 3 */
-#define nFLS3 0x0
#define FLG1 0x200 /* Slave Select Value 1 */
-#define nFLG1 0x0
#define FLG2 0x400 /* Slave Select Value 2 */
-#define nFLG2 0x0
#define FLG3 0x800 /* Slave Select Value 3 */
-#define nFLG3 0x0
/* Bit masks for SPIx_STAT */
#define TXCOL 0x40 /* Transmit Collision Error */
-#define nTXCOL 0x0
#define RXS 0x20 /* RDBR Data Buffer Status */
-#define nRXS 0x0
#define RBSY 0x10 /* Receive Error */
-#define nRBSY 0x0
#define TXS 0x8 /* TDBR Data Buffer Status */
-#define nTXS 0x0
#define TXE 0x4 /* Transmission Error */
-#define nTXE 0x0
#define MODF 0x2 /* Mode Fault Error */
-#define nMODF 0x0
#define SPIF 0x1 /* SPI Finished */
-#define nSPIF 0x0
/* Bit masks for SPIx_TDBR */
#define PRESCALE 0x7f /* Prescale Value */
#define TWI_ENA 0x80 /* TWI Enable */
-#define nTWI_ENA 0x0
#define SCCB 0x200 /* Serial Camera Control Bus */
-#define nSCCB 0x0
/* Bit maskes for TWIx_CLKDIV */
/* Bit maskes for TWIx_SLAVE_CTL */
#define SEN 0x1 /* Slave Enable */
-#define nSEN 0x0
#define STDVAL 0x4 /* Slave Transmit Data Valid */
-#define nSTDVAL 0x0
#define NAK 0x8 /* Not Acknowledge */
-#define nNAK 0x0
#define GEN 0x10 /* General Call Enable */
-#define nGEN 0x0
/* Bit maskes for TWIx_SLAVE_ADDR */
/* Bit maskes for TWIx_SLAVE_STAT */
#define SDIR 0x1 /* Slave Transfer Direction */
-#define nSDIR 0x0
#define GCALL 0x2 /* General Call */
-#define nGCALL 0x0
/* Bit maskes for TWIx_MASTER_CTL */
#define MEN 0x1 /* Master Mode Enable */
-#define nMEN 0x0
#define MDIR 0x4 /* Master Transfer Direction */
-#define nMDIR 0x0
#define FAST 0x8 /* Fast Mode */
-#define nFAST 0x0
#define STOP 0x10 /* Issue Stop Condition */
-#define nSTOP 0x0
#define RSTART 0x20 /* Repeat Start */
-#define nRSTART 0x0
#define DCNT 0x3fc0 /* Data Transfer Count */
#define SDAOVR 0x4000 /* Serial Data Override */
-#define nSDAOVR 0x0
#define SCLOVR 0x8000 /* Serial Clock Override */
-#define nSCLOVR 0x0
/* Bit maskes for TWIx_MASTER_ADDR */
/* Bit maskes for TWIx_MASTER_STAT */
#define MPROG 0x1 /* Master Transfer in Progress */
-#define nMPROG 0x0
#define LOSTARB 0x2 /* Lost Arbitration */
-#define nLOSTARB 0x0
#define ANAK 0x4 /* Address Not Acknowledged */
-#define nANAK 0x0
#define DNAK 0x8 /* Data Not Acknowledged */
-#define nDNAK 0x0
#define BUFRDERR 0x10 /* Buffer Read Error */
-#define nBUFRDERR 0x0
#define BUFWRERR 0x20 /* Buffer Write Error */
-#define nBUFWRERR 0x0
#define SDASEN 0x40 /* Serial Data Sense */
-#define nSDASEN 0x0
#define SCLSEN 0x80 /* Serial Clock Sense */
-#define nSCLSEN 0x0
#define BUSBUSY 0x100 /* Bus Busy */
-#define nBUSBUSY 0x0
/* Bit maskes for TWIx_FIFO_CTL */
#define XMTFLUSH 0x1 /* Transmit Buffer Flush */
-#define nXMTFLUSH 0x0
#define RCVFLUSH 0x2 /* Receive Buffer Flush */
-#define nRCVFLUSH 0x0
#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
-#define nXMTINTLEN 0x0
#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
-#define nRCVINTLEN 0x0
/* Bit maskes for TWIx_FIFO_STAT */
/* Bit maskes for TWIx_INT_MASK */
#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
-#define nSINITM 0x0
#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
-#define nSCOMPM 0x0
#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
-#define nSERRM 0x0
#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
-#define nSOVFM 0x0
#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
-#define nMCOMPM 0x0
#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
-#define nMERRM 0x0
#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
-#define nXMTSERVM 0x0
#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
-#define nRCVSERVM 0x0
/* Bit maskes for TWIx_INT_STAT */
#define SINIT 0x1 /* Slave Transfer Initiated */
-#define nSINIT 0x0
#define SCOMP 0x2 /* Slave Transfer Complete */
-#define nSCOMP 0x0
#define SERR 0x4 /* Slave Transfer Error */
-#define nSERR 0x0
#define SOVF 0x8 /* Slave Overflow */
-#define nSOVF 0x0
#define MCOMP 0x10 /* Master Transfer Complete */
-#define nMCOMP 0x0
#define MERR 0x20 /* Master Transfer Error */
-#define nMERR 0x0
#define XMTSERV 0x40 /* Transmit FIFO Service */
-#define nXMTSERV 0x0
#define RCVSERV 0x80 /* Receive FIFO Service */
-#define nRCVSERV 0x0
/* Bit maskes for TWIx_XMT_DATA8 */
/* Bit masks for SPORTx_TCR1 */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
-#define nTCKFE 0x0
#define LATFS 0x2000 /* Late Transmit Frame Sync */
-#define nLATFS 0x0
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
-#define nLTFS 0x0
#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */
-#define nDITFS 0x0
#define TFSR 0x400 /* Transmit Frame Sync Required Select */
-#define nTFSR 0x0
#define ITFS 0x200 /* Internal Transmit Frame Sync Select */
-#define nITFS 0x0
#define TLSBIT 0x10 /* Transmit Bit Order */
-#define nTLSBIT 0x0
#define TDTYPE 0xc /* Data Formatting Type Select */
#define ITCLK 0x2 /* Internal Transmit Clock Select */
-#define nITCLK 0x0
#define TSPEN 0x1 /* Transmit Enable */
-#define nTSPEN 0x0
/* Bit masks for SPORTx_TCR2 */
#define TRFST 0x400 /* Left/Right Order */
-#define nTRFST 0x0
#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */
-#define nTSFSE 0x0
#define TXSE 0x100 /* TxSEC Enable */
-#define nTXSE 0x0
#define SLEN_T 0x1f /* SPORT Word Length */
/* Bit masks for SPORTx_RCR1 */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
-#define nRCKFE 0x0
#define LARFS 0x2000 /* Late Receive Frame Sync */
-#define nLARFS 0x0
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
-#define nLRFS 0x0
#define RFSR 0x400 /* Receive Frame Sync Required Select */
-#define nRFSR 0x0
#define IRFS 0x200 /* Internal Receive Frame Sync Select */
-#define nIRFS 0x0
#define RLSBIT 0x10 /* Receive Bit Order */
-#define nRLSBIT 0x0
#define RDTYPE 0xc /* Data Formatting Type Select */
#define IRCLK 0x2 /* Internal Receive Clock Select */
-#define nIRCLK 0x0
#define RSPEN 0x1 /* Receive Enable */
-#define nRSPEN 0x0
/* Bit masks for SPORTx_RCR2 */
#define RRFST 0x400 /* Left/Right Order */
-#define nRRFST 0x0
#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */
-#define nRSFSE 0x0
#define RXSE 0x100 /* RxSEC Enable */
-#define nRXSE 0x0
#define SLEN_R 0x1f /* SPORT Word Length */
/* Bit masks for SPORTx_STAT */
#define TXHRE 0x40 /* Transmit Hold Register Empty */
-#define nTXHRE 0x0
#define TOVF 0x20 /* Sticky Transmit Overflow Status */
-#define nTOVF 0x0
#define TUVF 0x10 /* Sticky Transmit Underflow Status */
-#define nTUVF 0x0
#define TXF 0x8 /* Transmit FIFO Full Status */
-#define nTXF 0x0
#define ROVF 0x4 /* Sticky Receive Overflow Status */
-#define nROVF 0x0
#define RUVF 0x2 /* Sticky Receive Underflow Status */
-#define nRUVF 0x0
#define RXNE 0x1 /* Receive FIFO Not Empty Status */
-#define nRXNE 0x0
/* Bit masks for SPORTx_MCMC1 */
#define MFD 0xf000 /* Multi channel Frame Delay */
#define FSDR 0x80 /* Frame Sync to Data Relationship */
-#define nFSDR 0x0
#define MCMEM 0x10 /* Multi channel Frame Mode Enable */
-#define nMCMEM 0x0
#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
-#define nMCDRXPE 0x0
#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
-#define nMCDTXPE 0x0
#define MCCRM 0x3 /* 2X Clock Recovery Mode */
/* Bit masks for SPORTx_CHNL */
#define WLS 0x3 /* Word Length Select */
#endif
#define STB 0x4 /* Stop Bits */
-#define nSTB 0x0
#define PEN 0x8 /* Parity Enable */
-#define nPEN 0x0
#define EPS 0x10 /* Even Parity Select */
-#define nEPS 0x0
#define STP 0x20 /* Sticky Parity */
-#define nSTP 0x0
#define SB 0x40 /* Set Break */
-#define nSB 0x0
/* Bit masks for UARTx_MCR */
#define XOFF 0x1 /* Transmitter Off */
-#define nXOFF 0x0
#define MRTS 0x2 /* Manual Request To Send */
-#define nMRTS 0x0
#define RFIT 0x4 /* Receive FIFO IRQ Threshold */
-#define nRFIT 0x0
#define RFRT 0x8 /* Receive FIFO RTS Threshold */
-#define nRFRT 0x0
#define LOOP_ENA 0x10 /* Loopback Mode Enable */
-#define nLOOP_ENA 0x0
#define FCPOL 0x20 /* Flow Control Pin Polarity */
-#define nFCPOL 0x0
#define ARTS 0x40 /* Automatic Request To Send */
-#define nARTS 0x0
#define ACTS 0x80 /* Automatic Clear To Send */
-#define nACTS 0x0
/* Bit masks for UARTx_LSR */
#define DR 0x1 /* Data Ready */
-#define nDR 0x0
#define OE 0x2 /* Overrun Error */
-#define nOE 0x0
#define PE 0x4 /* Parity Error */
-#define nPE 0x0
#define FE 0x8 /* Framing Error */
-#define nFE 0x0
#define BI 0x10 /* Break Interrupt */
-#define nBI 0x0
#define THRE 0x20 /* THR Empty */
-#define nTHRE 0x0
#define TEMT 0x40 /* Transmitter Empty */
-#define nTEMT 0x0
#define TFI 0x80 /* Transmission Finished Indicator */
-#define nTFI 0x0
/* Bit masks for UARTx_MSR */
#define SCTS 0x1 /* Sticky CTS */
-#define nSCTS 0x0
#define CTS 0x10 /* Clear To Send */
-#define nCTS 0x0
#define RFCS 0x20 /* Receive FIFO Count Status */
-#define nRFCS 0x0
-
-/* Bit masks for UARTx_IER_SET */
-
-#define ERBFI_S 0x1 /* Enable Receive Buffer Full Interrupt */
-#define nERBFI_S 0x0
-#define ETBEI_S 0x2 /* Enable Transmit Buffer Empty Interrupt */
-#define nETBEI_S 0x0
-#define ELSI_S 0x4 /* Enable Receive Status Interrupt */
-#define nELSI_S 0x0
-#define EDSSI_S 0x8 /* Enable Modem Status Interrupt */
-#define nEDSSI_S 0x0
-#define EDTPTI_S 0x10 /* Enable DMA Transmit PIRQ Interrupt */
-#define nEDTPTI_S 0x0
-#define ETFI_S 0x20 /* Enable Transmission Finished Interrupt */
-#define nETFI_S 0x0
-#define ERFCI_S 0x40 /* Enable Receive FIFO Count Interrupt */
-#define nERFCI_S 0x0
-
-/* Bit masks for UARTx_IER_CLEAR */
-
-#define ERBFI_C 0x1 /* Enable Receive Buffer Full Interrupt */
-#define nERBFI_C 0x0
-#define ETBEI_C 0x2 /* Enable Transmit Buffer Empty Interrupt */
-#define nETBEI_C 0x0
-#define ELSI_C 0x4 /* Enable Receive Status Interrupt */
-#define nELSI_C 0x0
-#define EDSSI_C 0x8 /* Enable Modem Status Interrupt */
-#define nEDSSI_C 0x0
-#define EDTPTI_C 0x10 /* Enable DMA Transmit PIRQ Interrupt */
-#define nEDTPTI_C 0x0
-#define ETFI_C 0x20 /* Enable Transmission Finished Interrupt */
-#define nETFI_C 0x0
-#define ERFCI_C 0x40 /* Enable Receive FIFO Count Interrupt */
-#define nERFCI_C 0x0
+
+/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
+
+#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */
+#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI 0x4 /* Enable Receive Status Interrupt */
+#define EDSSI 0x8 /* Enable Modem Status Interrupt */
+#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
+#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
+#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
/* Bit masks for UARTx_GCTL */
#define UCEN 0x1 /* UART Enable */
-#define nUCEN 0x0
#define IREN 0x2 /* IrDA Mode Enable */
-#define nIREN 0x0
#define TPOLC 0x4 /* IrDA TX Polarity Change */
-#define nTPOLC 0x0
#define RPOLC 0x8 /* IrDA RX Polarity Change */
-#define nRPOLC 0x0
#define FPE 0x10 /* Force Parity Error */
-#define nFPE 0x0
#define FFE 0x20 /* Force Framing Error */
-#define nFFE 0x0
#define EDBO 0x40 /* Enable Divide-by-One */
-#define nEDBO 0x0
#define EGLSI 0x80 /* Enable Global LS Interrupt */
-#define nEGLSI 0x0
/* ******************************************* */
#define CH_UART1_TX 9
#define CH_ATAPI_RX 10
#define CH_ATAPI_TX 11
-
#define CH_EPPI0 12
#define CH_EPPI1 13
#define CH_EPPI2 14
#define CH_SDH 22
#define CH_SPI2 23
-#define MAX_BLACKFIN_DMA_CHANNEL CH_SPI2
+#define CH_MEM_STREAM0_DEST 24
+#define CH_MEM_STREAM0_SRC 25
+#define CH_MEM_STREAM1_DEST 26
+#define CH_MEM_STREAM1_SRC 27
+#define CH_MEM_STREAM2_DEST 28
+#define CH_MEM_STREAM2_SRC 29
+#define CH_MEM_STREAM3_DEST 30
+#define CH_MEM_STREAM3_SRC 31
+
+#define MAX_BLACKFIN_DMA_CHANNEL 32
+extern int channel2irq(unsigned int channel);
+extern struct dma_register *base_addr[];
#endif
--- /dev/null
+/*
+ * File: include/asm-blackfin/mach-bf548/gpio.h
+ * Based on:
+ * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ * Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+
+#define GPIO_PA0 0
+#define GPIO_PA1 1
+#define GPIO_PA2 2
+#define GPIO_PA3 3
+#define GPIO_PA4 4
+#define GPIO_PA5 5
+#define GPIO_PA6 6
+#define GPIO_PA7 7
+#define GPIO_PA8 8
+#define GPIO_PA9 9
+#define GPIO_PA10 10
+#define GPIO_PA11 11
+#define GPIO_PA12 12
+#define GPIO_PA13 13
+#define GPIO_PA14 14
+#define GPIO_PA15 15
+#define GPIO_PB0 16
+#define GPIO_PB1 17
+#define GPIO_PB2 18
+#define GPIO_PB3 19
+#define GPIO_PB4 20
+#define GPIO_PB5 21
+#define GPIO_PB6 22
+#define GPIO_PB7 23
+#define GPIO_PB8 24
+#define GPIO_PB9 25
+#define GPIO_PB10 26
+#define GPIO_PB11 27
+#define GPIO_PB12 28
+#define GPIO_PB13 29
+#define GPIO_PB14 30
+#define GPIO_PB15 31 /* N/A */
+#define GPIO_PC0 32
+#define GPIO_PC1 33
+#define GPIO_PC2 34
+#define GPIO_PC3 35
+#define GPIO_PC4 36
+#define GPIO_PC5 37
+#define GPIO_PC6 38
+#define GPIO_PC7 39
+#define GPIO_PC8 40
+#define GPIO_PC9 41
+#define GPIO_PC10 42
+#define GPIO_PC11 43
+#define GPIO_PC12 44
+#define GPIO_PC13 45
+#define GPIO_PC14 46 /* N/A */
+#define GPIO_PC15 47 /* N/A */
+#define GPIO_PD0 48
+#define GPIO_PD1 49
+#define GPIO_PD2 50
+#define GPIO_PD3 51
+#define GPIO_PD4 52
+#define GPIO_PD5 53
+#define GPIO_PD6 54
+#define GPIO_PD7 55
+#define GPIO_PD8 56
+#define GPIO_PD9 57
+#define GPIO_PD10 58
+#define GPIO_PD11 59
+#define GPIO_PD12 60
+#define GPIO_PD13 61
+#define GPIO_PD14 62
+#define GPIO_PD15 63
+#define GPIO_PE0 64
+#define GPIO_PE1 65
+#define GPIO_PE2 66
+#define GPIO_PE3 67
+#define GPIO_PE4 68
+#define GPIO_PE5 69
+#define GPIO_PE6 70
+#define GPIO_PE7 71
+#define GPIO_PE8 72
+#define GPIO_PE9 73
+#define GPIO_PE10 74
+#define GPIO_PE11 75
+#define GPIO_PE12 76
+#define GPIO_PE13 77
+#define GPIO_PE14 78
+#define GPIO_PE15 79
+#define GPIO_PF0 80
+#define GPIO_PF1 81
+#define GPIO_PF2 82
+#define GPIO_PF3 83
+#define GPIO_PF4 84
+#define GPIO_PF5 85
+#define GPIO_PF6 86
+#define GPIO_PF7 87
+#define GPIO_PF8 88
+#define GPIO_PF9 89
+#define GPIO_PF10 90
+#define GPIO_PF11 91
+#define GPIO_PF12 92
+#define GPIO_PF13 93
+#define GPIO_PF14 94
+#define GPIO_PF15 95
+#define GPIO_PG0 96
+#define GPIO_PG1 97
+#define GPIO_PG2 98
+#define GPIO_PG3 99
+#define GPIO_PG4 100
+#define GPIO_PG5 101
+#define GPIO_PG6 102
+#define GPIO_PG7 103
+#define GPIO_PG8 104
+#define GPIO_PG9 105
+#define GPIO_PG10 106
+#define GPIO_PG11 107
+#define GPIO_PG12 108
+#define GPIO_PG13 109
+#define GPIO_PG14 110
+#define GPIO_PG15 111
+#define GPIO_PH0 112
+#define GPIO_PH1 113
+#define GPIO_PH2 114
+#define GPIO_PH3 115
+#define GPIO_PH4 116
+#define GPIO_PH5 117
+#define GPIO_PH6 118
+#define GPIO_PH7 119
+#define GPIO_PH8 120
+#define GPIO_PH9 121
+#define GPIO_PH10 122
+#define GPIO_PH11 123
+#define GPIO_PH12 124
+#define GPIO_PH13 125
+#define GPIO_PH14 126 /* N/A */
+#define GPIO_PH15 127 /* N/A */
+#define GPIO_PI0 128
+#define GPIO_PI1 129
+#define GPIO_PI2 130
+#define GPIO_PI3 131
+#define GPIO_PI4 132
+#define GPIO_PI5 133
+#define GPIO_PI6 134
+#define GPIO_PI7 135
+#define GPIO_PI8 136
+#define GPIO_PI9 137
+#define GPIO_PI10 138
+#define GPIO_PI11 139
+#define GPIO_PI12 140
+#define GPIO_PI13 141
+#define GPIO_PI14 142
+#define GPIO_PI15 143
+#define GPIO_PJ0 144
+#define GPIO_PJ1 145
+#define GPIO_PJ2 146
+#define GPIO_PJ3 147
+#define GPIO_PJ4 148
+#define GPIO_PJ5 149
+#define GPIO_PJ6 150
+#define GPIO_PJ7 151
+#define GPIO_PJ8 152
+#define GPIO_PJ9 153
+#define GPIO_PJ10 154
+#define GPIO_PJ11 155
+#define GPIO_PJ12 156
+#define GPIO_PJ13 157
+#define GPIO_PJ14 158
+#define GPIO_PJ15 159
+
+#define MAX_BLACKFIN_GPIOS 160
+
+struct gpio_port_t {
+ unsigned short port_fer;
+ unsigned short dummy1;
+ unsigned short port_data;
+ unsigned short dummy2;
+ unsigned short port_set;
+ unsigned short dummy3;
+ unsigned short port_clear;
+ unsigned short dummy4;
+ unsigned short port_dir_set;
+ unsigned short dummy5;
+ unsigned short port_dir_clear;
+ unsigned short dummy6;
+ unsigned short port_inen;
+ unsigned short dummy7;
+ unsigned int port_mux;
+};
+
(lowest priority) IVG15 32 *
*/
-#define NR_PERI_INTS 32
+#define NR_PERI_INTS (32 * 3)
/* The ABSTRACT IRQ definitions */
/** the first seven of the following are fixed, the rest you change if you need to **/
#define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
#define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
#define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
-#define IRQ_MXVR BFIN_IRQ(27) /* SPORT3 Error Interrupt */
+#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
#define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
#define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
#define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
-#define IRQ_EPP1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
-#define IRQ_EPP2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
+#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
+#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
-#define IRQ_TMR0 BFIN_IRQ(86) /* Timer 0 Interrupt */
-#define IRQ_TMR1 BFIN_IRQ(87) /* Timer 1 Interrupt */
-#define IRQ_TMR2 BFIN_IRQ(88) /* Timer 2 Interrupt */
-#define IRQ_TMR3 BFIN_IRQ(89) /* Timer 3 Interrupt */
-#define IRQ_TMR4 BFIN_IRQ(90) /* Timer 4 Interrupt */
-#define IRQ_TMR5 BFIN_IRQ(91) /* Timer 5 Interrupt */
-#define IRQ_TMR6 BFIN_IRQ(92) /* Timer 6 Interrupt */
-#define IRQ_TMR7 BFIN_IRQ(93) /* Timer 7 Interrupt */
+#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
+#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
+#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
+#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
+#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
+#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
+#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
+#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
-#define NR_IRQS (IRQ_PH15+1)
+#define NR_IRQS (IRQ_PE15+1)
#else
-#define NR_IRQS (IRQ_UART1_ERROR+1)
+#define NR_IRQS (SYS_IRQS+1)
#endif
#define IVG7 7
#define IVG14 14
#define IVG15 15
-/* IAR0 BIT FIELDS*/
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA_ERROR_POS 4
-#define IRQ_ERROR_POS 8
-#define IRQ_RTC_POS 12
-#define IRQ_PPI_POS 16
-#define IRQ_SPORT0_RX_POS 20
-#define IRQ_SPORT0_TX_POS 24
-#define IRQ_SPORT1_RX_POS 28
+/* IAR0 BIT FIELDS */
+#define IRQ_PLL_WAKEUP_POS 0
+#define IRQ_DMAC0_ERR_POS 4
+#define IRQ_EPPI0_ERR_POS 8
+#define IRQ_SPORT0_ERR_POS 12
+#define IRQ_SPORT1_ERR_POS 16
+#define IRQ_SPI0_ERR_POS 20
+#define IRQ_UART0_ERR_POS 24
+#define IRQ_RTC_POS 28
-/* IAR1 BIT FIELDS*/
-#define IRQ_SPORT1_TX_POS 0
-#define IRQ_TWI_POS 4
-#define IRQ_SPI_POS 8
-#define IRQ_UART0_RX_POS 12
-#define IRQ_UART0_TX_POS 16
-#define IRQ_UART1_RX_POS 20
-#define IRQ_UART1_TX_POS 24
-#define IRQ_CAN_RX_POS 28
+/* IAR1 BIT FIELDS */
+#define IRQ_EPPI0_POS 0
+#define IRQ_SPORT0_RX_POS 4
+#define IRQ_SPORT0_TX_POS 8
+#define IRQ_SPORT1_RX_POS 12
+#define IRQ_SPORT1_TX_POS 16
+#define IRQ_SPI0_POS 20
+#define IRQ_UART0_RX_POS 24
+#define IRQ_UART0_TX_POS 28
-/* IAR2 BIT FIELDS*/
-#define IRQ_CAN_TX_POS 0
-#define IRQ_MAC_RX_POS 4
-#define IRQ_MAC_TX_POS 8
-#define IRQ_TMR0_POS 12
-#define IRQ_TMR1_POS 16
-#define IRQ_TMR2_POS 20
-#define IRQ_TMR3_POS 24
-#define IRQ_TMR4_POS 28
+/* IAR2 BIT FIELDS */
+#define IRQ_TIMER8_POS 0
+#define IRQ_TIMER9_POS 4
+#define IRQ_TIMER10_POS 8
+#define IRQ_PINT0_POS 12
+#define IRQ_PINT1_POS 16
+#define IRQ_MDMAS0_POS 20
+#define IRQ_MDMAS1_POS 24
+#define IRQ_WATCHDOG_POS 28
-/* IAR3 BIT FIELDS*/
-#define IRQ_TMR5_POS 0
-#define IRQ_TMR6_POS 4
-#define IRQ_TMR7_POS 8
-#define IRQ_PROG_INTA_POS 12
-#define IRQ_PORTG_INTB_POS 16
-#define IRQ_MEM_DMA0_POS 20
-#define IRQ_MEM_DMA1_POS 24
-#define IRQ_WATCH_POS 28
+/* IAR3 BIT FIELDS */
+#define IRQ_DMAC1_ERR_POS 0
+#define IRQ_SPORT2_ERR_POS 4
+#define IRQ_SPORT3_ERR_POS 8
+#define IRQ_MXVR_DATA_POS 12
+#define IRQ_SPI1_ERR_POS 16
+#define IRQ_SPI2_ERR_POS 20
+#define IRQ_UART1_ERR_POS 24
+#define IRQ_UART2_ERR_POS 28
-#endif /* _BF537_IRQ_H_ */
+/* IAR4 BIT FILEDS */
+#define IRQ_CAN0_ERR_POS 0
+#define IRQ_SPORT2_RX_POS 4
+#define IRQ_SPORT2_TX_POS 8
+#define IRQ_SPORT3_RX_POS 12
+#define IRQ_SPORT3_TX_POS 16
+#define IRQ_EPPI1_POS 20
+#define IRQ_EPPI2_POS 24
+#define IRQ_SPI1_POS 28
+
+/* IAR5 BIT FIELDS */
+#define IRQ_SPI2_POS 0
+#define IRQ_UART1_RX_POS 4
+#define IRQ_UART1_TX_POS 8
+#define IRQ_ATAPI_RX_POS 12
+#define IRQ_ATAPI_TX_POS 16
+#define IRQ_TWI0_POS 20
+#define IRQ_TWI1_POS 24
+#define IRQ_CAN0_RX_POS 28
+
+/* IAR6 BIT FIELDS */
+#define IRQ_CAN0_TX_POS 0
+#define IRQ_MDMAS2_POS 4
+#define IRQ_MDMAS3_POS 8
+#define IRQ_MXVR_ERR_POS 12
+#define IRQ_MXVR_MSG_POS 16
+#define IRQ_MXVR_PKT_POS 20
+#define IRQ_EPPI1_ERR_POS 24
+#define IRQ_EPPI2_ERR_POS 28
+
+/* IAR7 BIT FIELDS */
+#define IRQ_UART3_ERR_POS 0
+#define IRQ_HOST_ERR_POS 4
+#define IRQ_PIXC_ERR_POS 12
+#define IRQ_NFC_ERR_POS 16
+#define IRQ_ATAPI_ERR_POS 20
+#define IRQ_CAN1_ERR_POS 24
+#define IRQ_HS_DMA_ERR_POS 28
+
+/* IAR8 BIT FIELDS */
+#define IRQ_PIXC_IN0_POS 0
+#define IRQ_PIXC_IN1_POS 4
+#define IRQ_PIXC_OUT_POS 8
+#define IRQ_SDH_POS 12
+#define IRQ_CNT_POS 16
+#define IRQ_KEY_POS 20
+#define IRQ_CAN1_RX_POS 24
+#define IRQ_CAN1_TX_POS 28
+
+/* IAR9 BIT FIELDS */
+#define IRQ_SDH_MASK0_POS 0
+#define IRQ_SDH_MASK1_POS 4
+#define IRQ_USB_INT0_POS 12
+#define IRQ_USB_INT1_POS 16
+#define IRQ_USB_INT2_POS 20
+#define IRQ_USB_DMA_POS 24
+#define IRQ_OTPSEC_POS 28
+
+/* IAR10 BIT FIELDS */
+#define IRQ_TIMER0_POS 24
+#define IRQ_TIMER1_POS 28
+
+/* IAR11 BIT FIELDS */
+#define IRQ_TIMER2_POS 0
+#define IRQ_TIMER3_POS 4
+#define IRQ_TIMER4_POS 8
+#define IRQ_TIMER5_POS 12
+#define IRQ_TIMER6_POS 16
+#define IRQ_TIMER7_POS 20
+#define IRQ_PINT2_POS 24
+#define IRQ_PINT3_POS 28
+
+#endif /* _BF548_IRQ_H_ */
#define CH_IMEM_STREAM1_SRC 34
#define CH_IMEM_STREAM1_DEST 35
+extern int channel2irq(unsigned int channel);
+extern struct dma_register *base_addr[];
+
#endif
projects / mv-sheeva.git / commitdiff