ARMv7: Branch over conditional undefined instructions in vfphw.S

On ARMv7, conditional undefined instructions may generate exceptions
even if the condition is not met. The vfphw.S contains the FPINST and
FPINST2 access instructions which may not be present on processors with
synchronous VFP exceptions.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index a62dcf7098bad660ee65c22cbcf76a0a24677c05..3c73aafe3e0174bdd07f6e65cdcb16cfb52b4276 100644 (file)
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -101,9 +101,12 @@ ENTRY(vfp_support_entry)
        VFPFSTMIA r4, r5                @ save the working registers
        VFPFMRX r5, FPSCR               @ current status
        tst     r1, #FPEXC_EX           @ is there additional state to save?
-       VFPFMRX r6, FPINST, NE          @ FPINST (only if FPEXC.EX is set)
-       tstne   r1, #FPEXC_FP2V         @ is there an FPINST2 to read?
-       VFPFMRX r8, FPINST2, NE         @ FPINST2 if needed (and present)
+       beq     1f
+       VFPFMRX r6, FPINST              @ FPINST (only if FPEXC.EX is set)
+       tst     r1, #FPEXC_FP2V         @ is there an FPINST2 to read?
+       beq     1f
+       VFPFMRX r8, FPINST2             @ FPINST2 if needed (and present)
+1:
        stmia   r4, {r1, r5, r6, r8}    @ save FPEXC, FPSCR, FPINST, FPINST2
                                        @ and point r4 at the word at the
                                        @ start of the register dump
@@ -117,9 +120,12 @@ no_old_VFP_process:
                                        @ FPEXC is in a safe state
        ldmia   r10, {r1, r5, r6, r8}   @ load FPEXC, FPSCR, FPINST, FPINST2
        tst     r1, #FPEXC_EX           @ is there additional state to restore?
-       VFPFMXR FPINST, r6, NE          @ restore FPINST (only if FPEXC.EX is set)
-       tstne   r1, #FPEXC_FP2V         @ is there an FPINST2 to write?
-       VFPFMXR FPINST2, r8, NE         @ FPINST2 if needed (and present)
+       beq     1f
+       VFPFMXR FPINST, r6              @ restore FPINST (only if FPEXC.EX is set)
+       tst     r1, #FPEXC_FP2V         @ is there an FPINST2 to write?
+       beq     1f
+       VFPFMXR FPINST2, r8             @ FPINST2 if needed (and present)
+1:
        VFPFMXR FPSCR, r5               @ restore status
 
 check_for_exception:
@@ -175,9 +181,12 @@ ENTRY(vfp_save_state)
        VFPFSTMIA r0, r2                @ save the working registers
        VFPFMRX r2, FPSCR               @ current status
        tst     r1, #FPEXC_EX           @ is there additional state to save?
-       VFPFMRX r3, FPINST, NE          @ FPINST (only if FPEXC.EX is set)
-       tstne   r1, #FPEXC_FP2V         @ is there an FPINST2 to read?
-       VFPFMRX r12, FPINST2, NE        @ FPINST2 if needed (and present)
+       beq     1f
+       VFPFMRX r3, FPINST              @ FPINST (only if FPEXC.EX is set)
+       tst     r1, #FPEXC_FP2V         @ is there an FPINST2 to read?
+       beq     1f
+       VFPFMRX r12, FPINST2            @ FPINST2 if needed (and present)
+1:
        stmia   r0, {r1, r2, r3, r12}   @ save FPEXC, FPSCR, FPINST, FPINST2
        mov     pc, lr
 ENDPROC(vfp_save_state)