arm: tcc8k: Avoid reading clock register twice

There is no reason why in case of PLL2 the configuration register
should be read twice, while for PLL0/1 using the value previously read
is used. Do the same for PLL2.

Signed-off-by: Oskar Schirmer <oskar@linutronix.de>
Cc: bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
index 7ebcbff4652a7af3e948eb3729837b918bb6da39..a25e3fcb716f9abcda75a893163e3fae10ca41ea 100644 (file)
--- a/arch/arm/mach-tcc8k/clock.c
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -199,7 +199,7 @@ static unsigned long get_rate_pll_div(int pll)
                addr = CKC_BASE + CLKDIVC1_OFFS;
                reg = __raw_readl(addr);
                if (reg & CLKDIVC1_P2E)
-                       div = __raw_readl(addr) & 0x3f;
+                       div = reg & 0x3f;
                break;
        }
        return get_rate_pll(pll) / (div + 1);