In MX6Q/DL, originally GPIO_0 is used as CKO pin function. when SNVS
module is enabled, CKO output stops suddenly.
Both CKO clock config register CCOSR and GPIO_0 IOMUX register value are
not changed. But because ALT7 of GPIO_0 pad is SNVS_VIO_5 function. I
doubt that when SNVS module is enabled, GPIO_0 pad is automatically
changed to SNVS instance by SoC.
Thus we add option for snvs enable/disable.
Signed-off-by: Terry Lv <r65388@freescale.com>
extern char *gp_reg_id;
extern char *soc_reg_id;
extern char *pu_reg_id;
+static int caam_enabled;
extern struct regulator *(*get_cpu_regulator)(void);
extern void (*put_cpu_regulator)(void);
.pixel_clk = "emi_clk",
};
+static int __init caam_setup(char *__unused)
+{
+ caam_enabled = 1;
+ return 1;
+}
+early_param("caam", caam_setup);
+
/*!
* Board specific initialization.
*/
imx6q_add_mipi_csi2(&mipi_csi2_pdata);
imx6q_add_imx_snvs_rtc();
- imx6q_add_imx_caam();
+ if (1 == caam_enabled)
+ imx6q_add_imx_caam();
imx6q_add_imx_i2c(0, &mx6q_sabrelite_i2c_data);
imx6q_add_imx_i2c(1, &mx6q_sabrelite_i2c_data);
static int mag3110_position = 2;
static int max11801_mode = 1;
static int enable_lcd_ldb;
-
+static int caam_enabled;
extern char *gp_reg_id;
extern char *soc_reg_id;
.pixel_clk = "emi_clk",
};
+static int __init caam_setup(char *__unused)
+{
+ caam_enabled = 1;
+ return 1;
+}
+early_param("caam", caam_setup);
+
#define SNVS_LPCR 0x38
static void mx6_snvs_poweroff(void)
{
imx6q_add_mipi_csi2(&mipi_csi2_pdata);
imx6q_add_imx_snvs_rtc();
- imx6q_add_imx_caam();
+ if (1 == caam_enabled)
+ imx6q_add_imx_caam();
if (board_is_mx6_reva()) {
strcpy(mxc_i2c0_board_info[0].type, "wm8958");