ARM: dts: pfla02: PHY reset is active-low

Note that the fec driver code currently hard-codes an active-low
reset, regardless of the flags in the device tree.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 713893702122f58a967f628eaa10ba74605f6f82..69361771274c3090bee841eba18481641eec8218 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -9,6 +9,8 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
        model = "Phytec phyFLEX-i.MX6 Ouad";
        compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
@@ -289,7 +291,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii";
-       phy-reset-gpios = <&gpio3 23 0>;
+       phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
        status = "disabled";
 };