ENGR00318063-11: ARM: imx6: add return check for clock calls

This is a forward porting of commit 580f8c84ae81 (ENGR00318063-11: ARM:
imx6: add return check for clock calls) from imx_3.10.y to imx_3.14.y.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index d1e3f8e68eb5a8c7fea52763345d2655df39c14b..40335998e8d6a88b4da200293fe47273a943a0f2 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -128,7 +128,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        struct device_node *np;
        void __iomem *base;
        int i;
-       int ret;
 
        clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
        clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
@@ -176,13 +175,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
 
        /* Do not bypass PLLs initially */
-       clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]);
-       clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]);
-       clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]);
-       clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]);
-       clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]);
-       clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]);
-       clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]);
+       imx_clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]);
+       imx_clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]);
+       imx_clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]);
+       imx_clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]);
+       imx_clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]);
+       imx_clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]);
+       imx_clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]);
 
        clk[IMX6QDL_CLK_PLL1_SYS]      = imx_clk_gate("pll1_sys",      "pll1_bypass", base + 0x00, 13);
        clk[IMX6QDL_CLK_PLL2_BUS]      = imx_clk_gate("pll2_bus",      "pll2_bypass", base + 0x30, 13);
@@ -484,25 +483,25 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
 
        /* ipu clock initialization */
-       clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
-       clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
-       clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
-       clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
-       clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
-       clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
-       clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
-       clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
        if (cpu_is_imx6dl()) {
-               clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000);
-               clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
-               clk_set_parent(clk[IMX6QDL_CLK_AXI_ALT_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
-               clk_set_parent(clk[IMX6QDL_CLK_AXI_SEL], clk[IMX6QDL_CLK_AXI_ALT_SEL]);
+               imx_clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000);
+               imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
+               imx_clk_set_parent(clk[IMX6QDL_CLK_AXI_ALT_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
+               imx_clk_set_parent(clk[IMX6QDL_CLK_AXI_SEL], clk[IMX6QDL_CLK_AXI_ALT_SEL]);
                /* set epdc/pxp axi clock to 200Mhz */
-               clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
-               clk_set_rate(clk[IMX6QDL_CLK_IPU2], 200000000);
+               imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
+               imx_clk_set_rate(clk[IMX6QDL_CLK_IPU2], 200000000);
        } else if (cpu_is_imx6q()) {
-               clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
-               clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
+               imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
+               imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
        }
 
        /*
@@ -510,39 +509,36 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         * We can not get the 100MHz from the pll2_pfd0_352m.
         * So choose pll2_pfd2_396m as enfc_sel's parent.
         */
-       clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
 
        /* gpu clock initilazation */
-       clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
-       clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 594000000);
-       clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
-       clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
-       clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
+       imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 594000000);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
+       imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
 
        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
-               clk_prepare_enable(clk[clks_init_on[i]]);
+               imx_clk_prepare_enable(clk[clks_init_on[i]]);
 
        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-               clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
-               clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
+               imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
+               imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
        }
 
        /*
         * Let's initially set up CLKO with OSC24M, since this configuration
         * is widely used by imx6q board designs to clock audio codec.
         */
-       ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
-       if (!ret)
-               ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
-       if (ret)
-               pr_warn("failed to set up CLKO: %d\n", ret);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
 
        /* Audio-related clocks configuration */
-       clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
 
        /* All existing boards with PCIe use LVDS1 */
        if (IS_ENABLED(CONFIG_PCI_IMX6))
-               clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF]);
+               imx_clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF]);
 
        /* Set initial power mode */
        imx6q_set_lpm(WAIT_CLOCKED);

diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 75c95981049a5f01dccf4ca9ec95b2fe4ed9b175..b1c04eca284102e5e82718b27582a4d7e1dccb6a 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -189,7 +189,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        struct device_node *np;
        void __iomem *base;
        int i;
-       int ret;
 
        clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
        clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
@@ -228,13 +227,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        clks[IMX6SL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
 
        /* Do not bypass PLLs initially */
-       clk_set_parent(clks[IMX6SL_PLL1_BYPASS], clks[IMX6SL_CLK_PLL1]);
-       clk_set_parent(clks[IMX6SL_PLL2_BYPASS], clks[IMX6SL_CLK_PLL2]);
-       clk_set_parent(clks[IMX6SL_PLL3_BYPASS], clks[IMX6SL_CLK_PLL3]);
-       clk_set_parent(clks[IMX6SL_PLL4_BYPASS], clks[IMX6SL_CLK_PLL4]);
-       clk_set_parent(clks[IMX6SL_PLL5_BYPASS], clks[IMX6SL_CLK_PLL5]);
-       clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]);
-       clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]);
+       imx_clk_set_parent(clks[IMX6SL_PLL1_BYPASS], clks[IMX6SL_CLK_PLL1]);
+       imx_clk_set_parent(clks[IMX6SL_PLL2_BYPASS], clks[IMX6SL_CLK_PLL2]);
+       imx_clk_set_parent(clks[IMX6SL_PLL3_BYPASS], clks[IMX6SL_CLK_PLL3]);
+       imx_clk_set_parent(clks[IMX6SL_PLL4_BYPASS], clks[IMX6SL_CLK_PLL4]);
+       imx_clk_set_parent(clks[IMX6SL_PLL5_BYPASS], clks[IMX6SL_CLK_PLL5]);
+       imx_clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]);
+       imx_clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]);
 
        clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_gate("pll1_sys",      "pll1_bypass", base + 0x00, 13);
        clks[IMX6SL_CLK_PLL2_BUS]      = imx_clk_gate("pll2_bus",      "pll2_bypass", base + 0x30, 13);
@@ -421,32 +420,29 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
 
        /* Ensure the AHB clk is at 132MHz. */
-       ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
-       if (ret)
-               pr_warn("%s: failed to set AHB clock rate %d!\n",
-                       __func__, ret);
+       imx_clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
 
        /*
         * Make sure those always on clocks are enabled to maintain the correct
         * usecount and enabling/disabling of parent PLLs.
         */
        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
-               clk_prepare_enable(clks[clks_init_on[i]]);
+               imx_clk_prepare_enable(clks[clks_init_on[i]]);
 
        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-               clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
-               clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
+               imx_clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
+               imx_clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
        }
 
        /* set perclk to source from OSC 24MHz */
-       clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
+       imx_clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
 
        /* Audio-related clocks configuration */
-       clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
+       imx_clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
 
        /* Configure pxp clocks */
-       clk_set_parent(clks[IMX6SL_CLK_PXP_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
-       clk_set_rate(clks[IMX6SL_CLK_PXP_AXI], 200000000);
+       imx_clk_set_parent(clks[IMX6SL_CLK_PXP_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
+       imx_clk_set_rate(clks[IMX6SL_CLK_PXP_AXI], 200000000);
 
        /* Set initial power mode */
        imx6q_set_lpm(WAIT_CLOCKED);
@@ -455,9 +451,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        mxc_timer_init_dt(np);
 
        /* Initialize Video PLLs to valid frequency (650MHz). */
-       clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO_DIV], 650000000);
+       imx_clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO_DIV], 650000000);
        /* set PLL5 video as lcdif pix parent clock */
-       clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
+       imx_clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
                        clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
 }
 CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);

diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index a747d0b1f5d1bd1a7e57d30a65decef7c62acb18..c4ba60ef3203402aa5d2cbf4f50f0bf203538e52 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -190,13 +190,13 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        clks[IMX6SX_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
 
        /* Do not bypass PLLs initially */
-       clk_set_parent(clks[IMX6SX_PLL1_BYPASS], clks[IMX6SX_CLK_PLL1]);
-       clk_set_parent(clks[IMX6SX_PLL2_BYPASS], clks[IMX6SX_CLK_PLL2]);
-       clk_set_parent(clks[IMX6SX_PLL3_BYPASS], clks[IMX6SX_CLK_PLL3]);
-       clk_set_parent(clks[IMX6SX_PLL4_BYPASS], clks[IMX6SX_CLK_PLL4]);
-       clk_set_parent(clks[IMX6SX_PLL5_BYPASS], clks[IMX6SX_CLK_PLL5]);
-       clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]);
-       clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]);
+       imx_clk_set_parent(clks[IMX6SX_PLL1_BYPASS], clks[IMX6SX_CLK_PLL1]);
+       imx_clk_set_parent(clks[IMX6SX_PLL2_BYPASS], clks[IMX6SX_CLK_PLL2]);
+       imx_clk_set_parent(clks[IMX6SX_PLL3_BYPASS], clks[IMX6SX_CLK_PLL3]);
+       imx_clk_set_parent(clks[IMX6SX_PLL4_BYPASS], clks[IMX6SX_CLK_PLL4]);
+       imx_clk_set_parent(clks[IMX6SX_PLL5_BYPASS], clks[IMX6SX_CLK_PLL5]);
+       imx_clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]);
+       imx_clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]);
 
        clks[IMX6SX_CLK_PLL1_SYS]      = imx_clk_gate("pll1_sys",      "pll1_bypass", base + 0x00, 13);
        clks[IMX6SX_CLK_PLL2_BUS]      = imx_clk_gate("pll2_bus",      "pll2_bypass", base + 0x30, 13);
@@ -520,72 +520,70 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        clk_register_clkdev(clks[IMX6SX_CLK_GPT_3M], "gpt_3m", "imx-gpt.0");
 
        /* set perclk to from OSC */
-       clk_set_parent(clks[IMX6SX_CLK_PERCLK_SEL], clks[IMX6SX_CLK_OSC]);
+       imx_clk_set_parent(clks[IMX6SX_CLK_PERCLK_SEL], clks[IMX6SX_CLK_OSC]);
 
        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
-               clk_prepare_enable(clks[clks_init_on[i]]);
+               imx_clk_prepare_enable(clks[clks_init_on[i]]);
 
        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-               clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
-               clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
+               imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
+               imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
        }
 
        /* Set the default 132MHz for EIM module */
-       clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
-       clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
+       imx_clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
+       imx_clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
 
        /* set parent clock for LCDIF1 pixel clock */
-       clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]);
-       clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]);
+       imx_clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]);
+       imx_clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]);
 
        /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */
-       if (clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M]))
-               pr_err("Failed to set pcie bus parent clk.\n");
-       if (clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI]))
-               pr_err("Failed to set pcie parent clk.\n");
+       imx_clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M]);
+       imx_clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI]);
 
        /*
         * Init enet system AHB clock, set to 200Mhz
         * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
         */
-       clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
-       clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]);
-       clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);
-       clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
-       clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
+       imx_clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
+       imx_clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]);
+       imx_clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);
+       imx_clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
+       imx_clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
 
        /* Audio clocks */
-       clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);
+       imx_clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);
 
-       clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-       clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000);
+       imx_clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+       imx_clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000);
 
-       clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
-       clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000);
+       imx_clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
+       imx_clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000);
 
-       clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-       clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-       clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-       clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000);
-       clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000);
-       clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000);
+       imx_clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+       imx_clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+       imx_clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+       imx_clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000);
+       imx_clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000);
+       imx_clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000);
 
-       clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-       clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000);
+       imx_clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+       imx_clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000);
 
        /* Set parent clock for vadc */
-       clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
+       imx_clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
 
        /* default parent of can_sel clock is invalid, manually set it here */
-       clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]);
+       imx_clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]);
 
        /* Update gpu clock from default 528M to 720M */
-       clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
-       clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
+       imx_clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
+       imx_clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
 
        /* Set the UART parent if needed. */
        if (uart_from_osc)
-               clk_set_parent(clks[IMX6SX_CLK_UART_SEL], clks[IMX6SX_CLK_OSC]);
+               imx_clk_set_parent(clks[IMX6SX_CLK_UART_SEL], clks[IMX6SX_CLK_OSC]);
 
        /* Set initial power mode */
        imx6q_set_lpm(WAIT_CLOCKED);

diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 2e5e1e80a25bb9d978af312056acbd6d7be3809e..ac0b6f0404bc77a99b80dcbcacc2e44d7c666481 100644 (file)
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -54,6 +54,33 @@ static inline struct clk *imx_clk_gate2_shared(const char *name,
                        reg, shift, 0, &imx_ccm_lock, share_count);
 }
 
+static inline void imx_clk_prepare_enable(struct clk *clk)
+{
+       int ret = clk_prepare_enable(clk);
+
+       if (ret)
+               pr_err("failed to prepare and enable clk %s: %d\n",
+                       __clk_get_name(clk), ret);
+}
+
+static inline void imx_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+       int ret = clk_set_parent(clk, parent);
+
+       if (ret)
+               pr_err("failed to set parent of clk %s to %s: %d\n",
+                       __clk_get_name(clk), __clk_get_name(parent), ret);
+}
+
+static inline void imx_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+       int ret = clk_set_rate(clk, rate);
+
+       if (ret)
+               pr_err("failed to set rate of clk %s to %ld: %d\n",
+                       __clk_get_name(clk), rate, ret);
+}
+
 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
                void __iomem *reg, u8 idx);