Merge branch 'master' of git://git.denx.de/u-boot-usb

diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c
index 226ef57eeecd0b4aa8cf15d631d1ae72ce731c2e..6ef663eeb0fb9a91ba351220ee36f35a2926f336 100644 (file)
--- a/board/atum8548/atum8548.c
+++ b/board/atum8548/atum8548.c
@@ -37,10 +37,6 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 long int fixed_sdram(void);
 
 int board_early_init_f (void)
@@ -117,12 +113,6 @@ initdram(int board_type)
        dram_size = fixed_sdram ();
 #endif
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-       /*
-        * Initialize and enable DDR ECC.
-        */
-       ddr_enable_ecc(dram_size);
-#endif
        puts("    DDR: ");
        return dram_size;
 }

diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 6fed4eaf2a5050a084a2b217f3c0854f02f4d258..2b17612b336906cd519a97e7bcba2c2f58e63ec2 100644 (file)
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -41,10 +41,6 @@
 #include "../common/pixis.h"
 #include "../common/sgmii_riser.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 phys_size_t fixed_sdram(void);
 
 int checkboard (void)
@@ -65,20 +61,12 @@ initdram(int board_type)
 
 #ifdef CONFIG_SPD_EEPROM
        dram_size = fsl_ddr_sdram();
-
-       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
-       dram_size *= 0x100000;
 #else
        dram_size = fixed_sdram();
 #endif
+       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+       dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-       /*
-        * Initialize and enable DDR ECC.
-        */
-       ddr_enable_ecc(dram_size);
-#endif
        puts("    DDR: ");
        return dram_size;
 }

diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 545d869fcc93e537bc852549473f3870beaf4b8f..14581abdd8ad20739f6e964bd6885e2cf827e718 100644 (file)
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -38,10 +38,6 @@
 #include "../common/pixis.h"
 #include "../common/sgmii_riser.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 int checkboard (void)
 {
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -77,12 +73,6 @@ initdram(int board_type)
 
        dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-       /*
-        * Initialize and enable DDR ECC.
-        */
-       ddr_enable_ecc(dram_size);
-#endif
        puts("    DDR: ");
        return dram_size;
 }

diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index af5ff42e319e4e85c4c29a01817375932f7c20f9..c562fc9d95524ed80c6dbef12983b66800bc5613 100644 (file)
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -38,10 +38,6 @@
 #include "../common/eeprom.h"
 #include "../common/via.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void local_bus_init(void);
@@ -56,7 +52,6 @@ int checkboard (void)
        uint pci_slot = get_pci_slot ();
 
        uint cpu_board_rev = get_cpu_board_revision ();
-       uint svr;
 
        printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
                get_board_version (), pci_slot);
@@ -69,17 +64,6 @@ int checkboard (void)
         */
        local_bus_init ();
 
-       svr = get_svr();
-
-       /*
-        * Fix CPU2 errata: A core hang possible while executing a
-        * msync instruction and a snoopable transaction from an I/O
-        * master tagged to make quick forward progress is present.
-        * Fixed in Silicon Rev.2.1
-        */
-       if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
-               ecm->eebpcr |= (1 << 16);
-
        /*
         * Hack TSEC 3 and 4 IO voltages.
         */
@@ -118,13 +102,6 @@ initdram(int board_type)
        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
        dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-       /*
-        * Initialize and enable DDR ECC.
-        */
-       ddr_enable_ecc(dram_size);
-#endif
-
        /*
         * SDRAM Initialization
         */
@@ -355,7 +332,7 @@ pci_init_board(void)
                first_free_busno=hose->last_busno+1;
                printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
 #ifdef CONFIG_PCIX_CHECK
-               if (!(gur->pordevsr & PORDEVSR_PCI)) {
+               if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
                        /* PCI-X init */
                        if (CONFIG_SYS_CLK_FREQ < 66000000)
                                printf("PCI-X will only work at 66 MHz\n");

diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 688d8c390f692a15959cae0c1d964afc7ee1ee94..bc93be80fcba278d4ab983fb59e440d5697636d5 100644 (file)
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -99,11 +99,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
        {0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
 };
 
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 void local_bus_init(void);
 void sdram_init(void);
 
@@ -170,13 +165,6 @@ initdram(int board_type)
        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
        dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-       /*
-        * Initialize and enable DDR ECC.
-        */
-       ddr_enable_ecc(dram_size);
-#endif
-
        /*
         * SDRAM Initialization
         */

diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 3a78c98d14db943bf04419e1ed2170d0ff859421..a14db5ad2c4f8bfcf0517fd3f67d63830e86fca0 100644 (file)
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -38,10 +38,6 @@
 #include "../common/pixis.h"
 #include "../common/sgmii_riser.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 long int fixed_sdram(void);
 
 int checkboard (void)
@@ -61,20 +57,12 @@ phys_size_t initdram(int board_type)
 
 #ifdef CONFIG_SPD_EEPROM
        dram_size = fsl_ddr_sdram();
-
-       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
-       dram_size *= 0x100000;
 #else
        dram_size = fixed_sdram();
 #endif
+       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+       dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-       /*
-        * Initialize and enable DDR ECC.
-        */
-       ddr_enable_ecc(dram_size);
-#endif
        puts("    DDR: ");
        return dram_size;
 }

diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 9548ac637de793f3110e4c8e4c8fcfbf03c3537b..8c073cb4bb28a983492471d9c5e056ad4822c4f1 100644 (file)
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -36,10 +36,6 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void local_bus_init(void);
@@ -65,13 +61,6 @@ int checkboard (void)
         */
        local_bus_init ();
 
-       /*
-        * Fix CPU2 errata: A core hang possible while executing a
-        * msync instruction and a snoopable transaction from an I/O
-        * master tagged to make quick forward progress is present.
-        */
-       ecm->eebpcr |= (1 << 16);
-
        /*
         * Hack TSEC 3 and 4 IO voltages.
         */
@@ -114,12 +103,6 @@ initdram(int board_type)
        dram_size = fixed_sdram ();
 #endif
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-       /*
-        * Initialize and enable DDR ECC.
-        */
-       ddr_enable_ecc(dram_size);
-#endif
        /*
         * SDRAM Initialization
         */
@@ -429,7 +412,7 @@ pci_init_board(void)
                first_free_busno=hose->last_busno+1;
                printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
 #ifdef CONFIG_PCIX_CHECK
-               if (!(gur->pordevsr & PORDEVSR_PCI)) {
+               if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
                        /* PCI-X init */
                        if (CONFIG_SYS_CLK_FREQ < 66000000)
                                printf("PCI-X will only work at 66 MHz\n");

diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c
index b91b1eab6ec6d5670047e449f65dc265b8f52140..4591e466b99dcebc377822c2a870387960c99165 100644 (file)
--- a/board/socrates/tlb.c
+++ b/board/socrates/tlb.c
@@ -100,6 +100,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 6, BOOKE_PAGESZ_64M, 1),
 
+#if !defined(CONFIG_SPD_EEPROM)
        /*
         * TLB 7+8:     512M    DDR, cache disabled (needed for memory test)
         * 0x00000000  512M     DDR System memory
@@ -114,6 +115,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 8, BOOKE_PAGESZ_256M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);

diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index 3a828edc1ad2667962fc3145b3fb80d75251b74c..73f1d01bdf23d52c143b06baf34e146456732690 100644 (file)
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -610,7 +610,7 @@ static inline void init_pci1(void)
 
                first_free_busno = hose->last_busno + 1;
 #ifdef CONFIG_PCIX_CHECK
-               if (!(gur->pordevsr & PORDEVSR_PCI)) {
+               if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
                        ushort reg16 =
                                PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
                                PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;

diff --git a/common/env_onenand.c b/common/env_onenand.c
index 3c65b3e4873d3c7566fcc9b4b2a025a1e61ce08b..dbccc791258b7f0b054c5a26377387d2e0a14a9c 100644 (file)
--- a/common/env_onenand.c
+++ b/common/env_onenand.c
@@ -97,6 +97,7 @@ int saveenv(void)
 
        instr.len = CONFIG_ENV_SIZE;
        instr.addr = env_addr;
+       instr.mtd = &onenand_mtd;
        if (onenand_erase(&onenand_mtd, &instr)) {
                printf("OneNAND: erase failed at 0x%08lx\n", env_addr);
                return 1;

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 3a8aef20d31516d69f66fd60c4f9c0d1cd9b1c0f..0b7c60971547074277577165ccf91e5b1627425a 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -132,6 +132,12 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 /* We run cpu_init_early_f in AS = 1 */
 void cpu_init_early_f(void)
 {
+       /* Pointer is writable since we allocated a register for it */
+       gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+       /* Clear initial global data */
+       memset ((void *) gd, 0, sizeof (gd_t));
+
        set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                1, 0, BOOKE_PAGESZ_4K, 0);
@@ -140,24 +146,19 @@ void cpu_init_early_f(void)
 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
        {
                u32 temp;
+               volatile u32 *ccsr_virt =
+                       (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
 
-               set_tlb(0, CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_DEFAULT,
+               set_tlb(0, (u32)ccsr_virt, CONFIG_SYS_CCSRBAR_DEFAULT,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        1, 1, BOOKE_PAGESZ_4K, 0);
 
-               temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT);
-               out_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_PHYS >> 12);
-
+               temp = in_be32(ccsr_virt);
+               out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
                temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
        }
 #endif
 
-       /* Pointer is writable since we allocated a register for it */
-       gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
-       /* Clear initial global data */
-       memset ((void *) gd, 0, sizeof (gd_t));
-
        init_laws();
        invalidate_tlb(0);
        init_tlbs();
@@ -174,6 +175,19 @@ void cpu_init_f (void)
 {
        volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
        extern void m8560_cpm_reset (void);
+#ifdef CONFIG_MPC8548
+       ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+       uint svr = get_svr();
+
+       /*
+        * CPU2 errata workaround: A core hang possible while executing
+        * a msync instruction and a snoopable transaction from an I/O
+        * master tagged to make quick forward progress is present.
+        * Fixed in silicon rev 2.1.
+        */
+       if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
+               out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
+#endif
 
        disable_tlb(14);
        disable_tlb(15);

diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index 112f18c2b8b261e69bbc2c3d31bf2e6a7c72f0c4..787c6eb74c47ddd5163301492efef9e087ad0e86 100644 (file)
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -70,7 +70,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
         */
        pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 
-       if (!(gur->pordevsr & PORDEVSR_PCI)) {
+       if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
                /* PCI-X init */
                if (CONFIG_SYS_CLK_FREQ < 66000000)
                        printf("PCI-X will only work at 66 MHz\n");

diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index 21a16d97e12c5e75ab6dcaf1fef891805a78de2b..f1ad1328658726c5256b5946ca8d5565d273e0b7 100644 (file)
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -475,9 +475,14 @@ phys_size_t fsl_ddr_sdram(void)
                         */
                        memctl_interleaved = 1;
                } else {
-                       printf("Error: memctl interleaving not "
+                       printf("Warning: memctl interleaving not "
                                "properly configured on all controllers\n");
-                       while (1);
+                       memctl_interleaved = 0;
+                       for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+                               info.memctl_opts[i].memctl_interleaving = 0;
+                       debug("Recomputing with memctl_interleaving off.\n");
+                       total_memory = fsl_ddr_compute(&info,
+                                                      STEP_ASSIGN_ADDRESSES);
                }
        }
 

diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 714e88d7fa5e10ca7d7ed647e9c985764e31ec21..af7f73a835ae4011709192da96444d9d0600b5f7 100644 (file)
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -197,10 +197,10 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
         */
        if ((p = getenv("memctl_intlv_ctl")) != NULL) {
                if (pdimm[0].n_ranks == 0) {
-                       printf("There is no rank on CS0. Because only rank on \
-                               CS0 and ranks chip-select interleaved with CS0\
-                               are controller interleaved, force non memory \
-                               controller interleaving\n");
+                       printf("There is no rank on CS0. Because only rank on "
+                               "CS0 and ranks chip-select interleaved with CS0"
+                               " are controller interleaved, force non memory "
+                               "controller interleaving\n");
                        popts->memctl_interleaving = 0;
                } else {
                        popts->memctl_interleaving = 1;
@@ -239,22 +239,22 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
                case FSL_DDR_CS0_CS1:
                        if (pdimm[0].n_ranks != 2) {
                                popts->ba_intlv_ctl = 0;
-                               printf("No enough bank(chip-select) for \
-                                       CS0+CS1, force non-interleaving!\n");
+                               printf("Not enough bank(chip-select) for "
+                                       "CS0+CS1, force non-interleaving!\n");
                        }
                        break;
                case FSL_DDR_CS2_CS3:
                        if (pdimm[1].n_ranks !=2){
                                popts->ba_intlv_ctl = 0;
-                               printf("No enough bank(CS) for CS2+CS3, \
-                                       force non-interleaving!\n");
+                               printf("Not enough bank(CS) for CS2+CS3, "
+                                       "force non-interleaving!\n");
                        }
                        break;
                case FSL_DDR_CS0_CS1_AND_CS2_CS3:
                        if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
                                popts->ba_intlv_ctl = 0;
-                               printf("No enough bank(CS) for CS0+CS1 or \
-                                        CS2+CS3, force non-interleaving!\n");
+                               printf("Not enough bank(CS) for CS0+CS1 or "
+                                       "CS2+CS3, force non-interleaving!\n");
                        }
                        break;
                default:

diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn
index 5ac39e67822ecd29dabd5d2f6a87e41832d40fa7..d8fe0a4a136b2bd5b053a86e98be38c4efc8c9af 100644 (file)
--- a/doc/README.mpc8641hpcn
+++ b/doc/README.mpc8641hpcn
@@ -134,15 +134,15 @@ For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit.
 However, the physical map is altered to reside in 36-bit space, as follows.
 Addresses are no longer mapped with VA == PA.  All accesses from
 software use the VA; the PA is only used for setting up windows
-and mappings. Note that the low 32 bits are the same as the VA above;
-only the top 4 bits vary:
+and mappings. Note that with the exception of PCI MEM and RIO, the low
+ 32 bits are the same as the VA above; only the top 4 bits vary:
 
        Memory Range                    Device          Size
        ------------                    ------          ----
        0x0_0000_0000   0x0_7fff_ffff   DDR             2G
-       0xc_8000_0000   0xc_9fff_ffff   RIO MEM         512M
-       0xc_8000_0000   0xc_9fff_ffff   PCI1/PEX1 MEM   512M
-       0xc_a000_0000   0xc_bfff_ffff   PCI2/PEX2 MEM   512M
+       0xc_0000_0000   0xc_1fff_ffff   RIO MEM         512M
+       0xc_0000_0000   0xc_1fff_ffff   PCI1/PEX1 MEM   512M
+       0xc_2000_0000   0xc_3fff_ffff   PCI2/PEX2 MEM   512M
        0xf_ffe0_0000   0xf_ffef_ffff   CCSR            1M
        0xf_ffdf_0000   0xf_ffdf_7fff   PIXIS           8K
        0xf_ffdf_8000   0xf_ffdf_ffff   CF              8K

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 7625cccec7ebc9455efb87351d7e627b4339a4c0..e57acba0d27e7ce425109410d4399d82b9514e3e 100644 (file)
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -58,7 +58,7 @@ void pciauto_config_init(struct pci_controller *hose);
 int fsl_pci_setup_inbound_windows(struct pci_region *r)
 {
        struct pci_region *rgn_base = r;
-       u64 sz = min((u64)gd->ram_size, 1ull << 32);
+       u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1);
 
        phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
        pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;

diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index cac7bf6bf58e54a492dee4640ff5c27c7c860bf8..51fc5c13b0b2dcc84cecc08fd36fec6e8e5e7171 100644 (file)
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -69,6 +69,14 @@
 #define BR_RES                         ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
 #endif
 
+/* Convert an address into the right format for the BR registers */
+#ifdef CONFIG_PHYS_64BIT
+#define BR_PHYS_ADDR(x)        ((unsigned long)((x & 0x0ffff8000ULL) | \
+                                        ((x & 0x300000000ULL) >> 19)))
+#else
+#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#endif
+
 /* OR - Option Registers
  */
 #define OR0                            0x5004          /* Register offset to immr */

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 75b451d2019aa5eaff7ee025975fcc3886e8a922..e5046bef3217624336838ad10f6a1f8747df11cd 100644 (file)
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1569,6 +1569,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_SGMII3_DIS    0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS    0x04000000
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL   0x38000000
+#define MPC85xx_PORDEVSR_PCI1          0x00800000
 #define MPC85xx_PORDEVSR_IO_SEL                0x00780000
 #define MPC85xx_PORDEVSR_PCI2_ARB      0x00040000
 #define MPC85xx_PORDEVSR_PCI1_ARB      0x00020000
@@ -1647,8 +1648,6 @@ typedef struct ccsr_gur {
        char    res15[61648];   /* 0xe0f30 to 0xefffff */
 } ccsr_gur_t;
 
-#define PORDEVSR_PCI   (0x00800000)    /* PCI Mode */
-
 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
 #define CONFIG_SYS_MPC85xx_GUTS_ADDR   (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
 #define CONFIG_SYS_MPC85xx_ECM_OFFSET  (0x0000)

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index bbdc211c06bd70cecdddd6e9bd16f69f95cc8819..8e82aac7b7ac7c215b30897a8f71dd806e460146 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -193,7 +193,6 @@
 #define CONFIG_SYS_BR1_PRELIM          (CONFIG_SYS_BCSR|0x00000801)    /* Port-size=8bit, MSEL=GPCM */
 #define CONFIG_SYS_OR1_PRELIM          0xFFFFE8F0              /* length 32K */
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000              /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x1000                  /* End of used area in RAM*/

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index f633f24bd59fd4fc2c6a1f9df9740c0f3b397b38..14cbc457159f3962f6a63f9a86be6e9e6f6fbb52 100644 (file)
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -266,7 +266,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #undef CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x1000          /* End of used area in RAM*/

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index fff888abc673b02496b211c4ee56aab94a4af2bc..5a99d5fe7997ee499150cfd473618c17547b12ea 100644 (file)
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -99,7 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE  0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
@@ -231,8 +231,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define PIXIS_VCLKL            0x1A    /* VELA VCLKL register */
 #define CONFIG_SYS_PIXIS_VBOOT_MASK    0xc0
 
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xffd00000      /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_END        0x00004000      /* End of used area in RAM */

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 79a52d9d1d7250362356db68812d2bd6b6153ad5..0b8fe6ad68af0af73ea7ccb2112ec6224c2de8fb 100644 (file)
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -258,7 +258,6 @@
 #define CONFIG_SYS_OR4_PRELIM          0xffffe1f1
 #define CONFIG_SYS_BCSR                (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */

diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 46a141a2c077c32ea58b9d89c013c3a98c3f0df4..21cf965ab38bc47365b2a17986cda5afdbb46da8 100644 (file)
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -161,7 +161,6 @@
 #define CONFIG_SYS_OR4_PRELIM          0xffffe1f1
 #define CONFIG_SYS_BCSR                (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0x40000000      /* Initial RAM address  */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */

diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 7ada8a222b991c54cc7760da6c561ba0bf1987ee..eaa737b88e27788dcfe1962446dd391bfa9fa4f6 100644 (file)
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -281,7 +281,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x4000      /* End of used area in RAM */

diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index cdbbea60d66c0ad17adada714a93f7ac97d16b14..b31c2bb371f9b81b85b7b56eb9994f7392f8d3c1 100644 (file)
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -97,7 +97,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE  0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
@@ -207,8 +207,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VCFGEN1_MASK     (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
 
 
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK      1
 #define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_END       0x00004000      /* End of used area in RAM */

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 083afba9a3073f27bc2f3b721425832970701cda..7a7e5a1457007659109cb11ca5d9f9aefe1b417b 100644 (file)
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -100,7 +100,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL                 /* possible DLL fix needed */
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE  0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
@@ -303,7 +303,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */

diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index f9419ccd0f90b205d81d283660b91beeae041835..40b40ed3af2e4d06499a9f15fdbf6ff39d6e9b31 100644 (file)
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -279,7 +279,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x4000      /* End of used area in RAM */

diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index f67d48963604b879dffc334d9326242b4b4ecb49..2b5b2c106464fbdc56a9efa5e1f097bc7da04452 100644 (file)
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -254,7 +254,6 @@
 #define CONFIG_SYS_OR4_PRELIM          0xffffe1f1
 #define CONFIG_SYS_BCSR                (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */

diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index ab3e6d69482e115967d04edf86f0f0cd8afa7677..8bdec65b7cdb8cc0423d0c11d14f61b333a21a1b 100644 (file)
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -92,7 +92,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL                 /* possible DLL fix needed */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
 
 #define CONFIG_MEM_INIT_VALUE  0xDeadBeef
 
@@ -265,7 +265,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BR5_PRELIM   0xf8010801
 #define CONFIG_SYS_OR5_PRELIM   0xffff69f7
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x4000      /* End of used area in RAM */

diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index c3693b85659a1a9bd67dbe25a72fd3a829abda0e..9a66ca810288e1e538cf03db04e443816adf8ed1 100644 (file)
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -99,6 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE  0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
@@ -114,22 +115,22 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define SPD_EEPROM_ADDRESS2    0x52    /* CTLR 1 DIMM 0 */
 
 /* These are used when DDR doesn't use SPD.  */
-#define CONFIG_SYS_SDRAM_SIZE          256             /* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS        0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG      0x80010102      /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3        0x00000000
-#define CONFIG_SYS_DDR_TIMING_0        0x00260802
-#define CONFIG_SYS_DDR_TIMING_1        0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2        0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1          0x00480432
+#define CONFIG_SYS_SDRAM_SIZE          512             /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS                0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG      0x80010202      /* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3                0x00020000
+#define CONFIG_SYS_DDR_TIMING_0                0x00260802
+#define CONFIG_SYS_DDR_TIMING_1                0x626b2634
+#define CONFIG_SYS_DDR_TIMING_2                0x062874cf
+#define CONFIG_SYS_DDR_MODE_1          0x00440462
 #define CONFIG_SYS_DDR_MODE_2          0x00000000
-#define CONFIG_SYS_DDR_INTERVAL        0x06180100
+#define CONFIG_SYS_DDR_INTERVAL                0x0c300100
 #define CONFIG_SYS_DDR_DATA_INIT       0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL        0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL        0x00000000
+#define CONFIG_SYS_DDR_CLK_CTRL                0x00800000
+#define CONFIG_SYS_DDR_OCD_CTRL                0x00000000
 #define CONFIG_SYS_DDR_OCD_STATUS      0x00000000
-#define CONFIG_SYS_DDR_CONTROL         0xC3008000      /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2        0x04400010
+#define CONFIG_SYS_DDR_CONTROL         0xc3000008      /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2                0x24400000
 
 #define CONFIG_SYS_DDR_ERR_INT_EN      0x0000000d
 #define CONFIG_SYS_DDR_ERR_DIS         0x00000000
@@ -248,8 +249,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
                                        | PIXIS_VCFGEN1_TSEC3SER \
                                        | PIXIS_VCFGEN1_TSEC4SER)
 
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xffd00000      /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_END        0x00004000      /* End of used area in RAM */

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index f2fe4a6cf985f4ac8a275c97e587023f723f6351..27517e5b1fbe4f9c0a3355c94050bdc0fc2ea4fb 100644 (file)
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -81,6 +81,9 @@
 #define CONFIG_SYS_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
 #define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH   0x0
+
 #define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
 #define CONFIG_SYS_PCIE2_ADDR          (CONFIG_SYS_CCSRBAR+0x9000)
@@ -206,7 +209,6 @@
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
@@ -388,6 +390,17 @@
 #define CONFIG_SYS_IBAT3L      (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT3U      CONFIG_SYS_DBAT3U
 
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+                                      | BATL_PP_RW | BATL_CACHEINHIBIT \
+                                      | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+                                      | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+                                      | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
 /*
  * BAT4                32M     Cache-inhibited, guarded
  * 0xe200_0000 1M      PCI-Express 2 I/O

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 69b4c4410d7b682e52aa0b42efd2f49987cea9b2..5a832961c2d1526c9c1f6252f299631f21909ef6 100644 (file)
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -186,17 +186,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_FLASH_BASE_PHYS     (CONFIG_SYS_FLASH_BASE \
                                         | CONFIG_SYS_PHYS_ADDR_HIGH)
 
-
 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
 
-/* Convert an address into the right format for the BR registers */
-#ifdef CONFIG_PHYS_64BIT
-#define BR_PHYS_ADDR(x)        ((unsigned long)((x & 0x0ffff8000ULL) | \
-                                        ((x & 0x300000000ULL) >> 19)))
-#else
-#define BR_PHYS_ADDR(x) (x & 0xffff8000)
-#endif
-
 #define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
                                 | 0x00001001)  /* port size 16bit */
 #define CONFIG_SYS_OR0_PRELIM  0xff806ff7      /* 8MB Boot Flash area*/
@@ -268,7 +259,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR       0x0fd00000      /* Initial RAM address */

diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index bc2d8253b0f87c5d340676ec78589643dfe7f250..4ecf8068ecf33cfdf27f24fce2813de4730a3437 100644 (file)
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -130,7 +130,6 @@
 #define CONFIG_SYS_MONITOR_BASE        TEXT_BASE
 #undef CONFIG_SYS_RAMBOOT
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x1000          /* End of used area in RAM*/

diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index c3a7f816f929ae40fb3886dd592254da770d3eb3..1cc80ad214612d371e6028835cac58fd0dcdbb4b 100644 (file)
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -161,7 +161,6 @@
 #define CONFIG_SYS_LBC_MRTPR           0x20000000    /* LB refresh timer prescal*/
 
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */

diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index b3bcf23c5cd721e8a856c57f9d9f576eec5fd238..698ad2d9111a53d84015ea1c2313012935823bc3 100644 (file)
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -164,7 +164,6 @@
 #define CONFIG_SYS_LBC_MRTPR           0x20000000    /* LB refresh timer prescal*/
 
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */

diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 48c9339802bc3948d026068ce495bfcd252f402f..2853fba0652ea09ff50382d51a57aada20221307 100644 (file)
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -186,7 +186,6 @@
 #define CONFIG_SYS_BCSR                ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
 /* the size of CS5 needs to be >= 16M for TLB and LAW setups */
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0x70000000      /* Initial RAM address  */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 2961a1b2a0f67910a9af699beec0ff664b975be1..796030d0607e7685fbb5c94d33eb539ed84ddef4 100644 (file)
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -171,7 +171,6 @@ extern int tqm834x_num_flash_banks;
 #undef  CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0x20000000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x1000          /* End of used area in RAM*/

diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 2d4048a92835fc1cec8f095cac68a2982adcde80..300f49079df73fb72b136bac9beac7eb23296032 100644 (file)
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -234,7 +234,6 @@
 #define CONFIG_SYS_LBC_LSRT            0x20000000      /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR           0x20000000      /* LB refresh timer presc.*/
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       (CONFIG_SYS_CCSRBAR \
                                 + 0x04010000)  /* Initial RAM address  */

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 174149b616a8cdabc6096037b9081e9de58e1736..0603e3c8a4b462aef464c519e27be44ec1ec460a 100644 (file)
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -162,7 +162,6 @@
 #undef  CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000              /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x1000                  /* End of used area in RAM*/

diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index aefd30a1ede2869ba0277b6b01c9c4156e205550..5ce4dac5e595cdbcfb0f3b3bd37d8e91f8e0929f 100644 (file)
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -280,7 +280,6 @@
                                | CONFIG_SYS_LBC_LSDMR_RFEN             \
                                )
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */

diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 43012754d287c0ef5106b179baffb488d145152d..e1d3a52b5e4edc993f53becc8d46a8327ed5ef09 100644 (file)
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -180,7 +180,6 @@
 #define CONFIG_SYS_BCSR                ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
 /* the size of CS5 needs to be >= 16M for TLB and LAW setups */
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0x70000000      /* Initial RAM address  */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */

diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 45d81792e06f89533c7e8d87414b4fcbedf93324..001294575822baa9e8fb81c31a5bcc6d80ace346 100644 (file)
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -104,6 +104,9 @@
 #define CONFIG_SYS_CCSRBAR             0xf8000000      /* relocated CCSRBAR */
 #define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH   0x0
+
 #define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCI2_ADDR           (CONFIG_SYS_CCSRBAR+0x9000)
 
@@ -241,7 +244,6 @@
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR       0x0fd00000      /* Initial RAM address */
@@ -433,6 +435,17 @@
 #define CONFIG_SYS_IBAT3L      (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT3U      CONFIG_SYS_DBAT3U
 
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+                                      | BATL_PP_RW | BATL_CACHEINHIBIT \
+                                      | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+                                      | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+                                      | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
 /*
  * BAT4         32M    Cache-inhibited, guarded
  * 0xe200_0000  16M    PCI-Express 1 I/O

diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index c67db8f25d9f73ab230002e78e00eca5bf02c68c..e89b5a3fb0ee57bf0c24343c2970d416994bec5e 100644 (file)
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -167,7 +167,6 @@
 #define CONFIG_SYS_LBC_LSRT            0x20000000    /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR           0x20000000    /* LB refresh timer presc.*/
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address  */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End used area in RAM */

diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 2188e5401b34b1e31bc87cd1736efc4cb5d544b4..a0f2ed0daf13cd8ccc23bc4c250846d2651405b7 100644 (file)
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -151,7 +151,6 @@
 #define CONFIG_SYS_LBC_LSDMR_4         0x1861b723
 #define CONFIG_SYS_LBC_LSDMR_5         0x4061b723
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */

diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index b0bd0508bb7702fbc944404c26d81b9c432bfe30..f0990c6799b2310da4113628038e549b6f9554a7 100644 (file)
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -164,7 +164,6 @@
 #define CONFIG_SYS_LBC_LSDMR_4         0x1861b723
 #define CONFIG_SYS_LBC_LSDMR_5         0x4061b723
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */