[NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */
[NISTC_AO_STATUS2_REG] = { 0x10c, 2 },
[NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */
- [G_HW_Save_Register(0)] = { 0x110, 4 },
- [G_HW_Save_Register(1)] = { 0x114, 4 },
+ [NISTC_G0_HW_SAVE_REG] = { 0x110, 4 },
+ [NISTC_G1_HW_SAVE_REG] = { 0x114, 4 },
[G_Save_Register(0)] = { 0x118, 4 },
[G_Save_Register(1)] = { 0x11c, 4 },
[AO_UI_Save_Registers] = { 0x120, 4 },
[NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 },
[NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 },
[NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 },
- [NITIO_G0_HW_SAVE] = { G_HW_Save_Register(0), 4 },
- [NITIO_G1_HW_SAVE] = { G_HW_Save_Register(1), 4 },
+ [NITIO_G0_HW_SAVE] = { NISTC_G0_HW_SAVE_REG, 4 },
+ [NITIO_G1_HW_SAVE] = { NISTC_G1_HW_SAVE_REG, 4 },
[NITIO_G0_SW_SAVE] = { G_Save_Register(0), 4 },
[NITIO_G1_SW_SAVE] = { G_Save_Register(1), 4 },
[NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 },
#define NISTC_DIO_IN_REG 7
+#define NISTC_G0_HW_SAVE_REG 8
+#define NISTC_G1_HW_SAVE_REG 10
+
#define AI_SI_Save_Registers 64
#define AI_SC_Save_Registers 66
#define AO_BC_Save_Registers 18
#define AO_UC_Save_Registers 20
-#define G_HW_Save_Register(a) (8+(a)*2)
-#define G_HW_Save_Register_High(a) (8+(a)*2)
-#define G_HW_Save_Register_Low(a) (9+(a)*2)
#define G_Save_Register(a) (12+(a)*2)
#define G_Save_Register_High(a) (12+(a)*2)
#define G_Save_Register_Low(a) (13+(a)*2)