NULL, NULL, NULL, "gpio1_7"),
_AM33XX_MUXENTRY(GPMC_AD8, 0,
"gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
- NULL, NULL, NULL, "gpio0_22"),
+ "ehrpwm2a", "pr1_mii_mt0_clk", NULL, "gpio0_22"),
_AM33XX_MUXENTRY(GPMC_AD9, 0,
"gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
- "ehrpwm2B", NULL, NULL, "gpio0_23"),
+ "ehrpwm2B", "pr1_mii0_col", NULL, "gpio0_23"),
_AM33XX_MUXENTRY(GPMC_AD10, 0,
"gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
- NULL, NULL, NULL, "gpio0_26"),
+ "ehrpwm2_tripzone_input", "pr1_mii0_txen", NULL, "gpio0_26"),
_AM33XX_MUXENTRY(GPMC_AD11, 0,
"gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
- NULL, NULL, NULL, "gpio0_27"),
+ "ehrpwm0_synco", "pr1_mii0_txd3", NULL, "gpio0_27"),
_AM33XX_MUXENTRY(GPMC_AD12, 0,
"gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
- NULL, NULL, NULL, "gpio1_12"),
+ "eqep2a_in", "pr1_mii0_txd2", "pr1_pru0_pru_r30_14", "gpio1_12"),
_AM33XX_MUXENTRY(GPMC_AD13, 0,
"gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
- NULL, NULL, NULL, "gpio1_13"),
+ "eqep2b_in", "pr1_mii0_txd1", "pr1_pru0_pru_r30_15", "gpio1_13"),
_AM33XX_MUXENTRY(GPMC_AD14, 0,
"gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",
- NULL, NULL, NULL, "gpio1_14"),
+ "eqep2_index", "pr1_mii0_txd0", "pr1_pru0_pru_r31_14", "gpio1_14"),
_AM33XX_MUXENTRY(GPMC_AD15, 0,
"gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
- NULL, NULL, NULL, "gpio1_15"),
+ "eqep2_strobe", "pr1_ecap0_ecap_capin_apwm_o", "pr1_pru0_pru_r31_15", "gpio1_15"),
_AM33XX_MUXENTRY(GPMC_A0, 0,
"gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
- NULL, NULL, NULL, "gpio1_16"),
+ "gpmc_a16","pr1_mii_mt1_clk", "ehrpwm1_tripzone_input", "gpio1_16"),
_AM33XX_MUXENTRY(GPMC_A1, 0,
"gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
- NULL, NULL, NULL, "gpio1_17"),
+ "gpmc_a17", "pr1_mii1_txd3", "ehrpwm0_synco", "gpio1_17"),
_AM33XX_MUXENTRY(GPMC_A2, 0,
"gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
- NULL, NULL, NULL, "gpio1_18"),
+ "gpmc_a18", "pr1_mii1_txd2", "ehrpwm1a", "gpio1_18"),
_AM33XX_MUXENTRY(GPMC_A3, 0,
"gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
- NULL, NULL, NULL, "gpio1_19"),
+ "gpmc_a19", "pr1_mii1_txd1", "ehrpwm1b", "gpio1_19"),
_AM33XX_MUXENTRY(GPMC_A4, 0,
"gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
- "gpmc_a20", NULL, NULL, "gpio1_20"),
+ "gpmc_a20", "pr1_mii1_txd0", "eqep1a_in", "gpio1_20"),
_AM33XX_MUXENTRY(GPMC_A5, 0,
"gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
- "gpmc_a21", NULL, NULL, "gpio1_21"),
+ "gpmc_a21", "pr1_mii1_rxd3", "eqep1b_in", "gpio1_21"),
_AM33XX_MUXENTRY(GPMC_A6, 0,
"gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
- "gpmc_a22", NULL, NULL, "gpio1_22"),
+ "gpmc_a22", "pr1_mii1_rxd2", "eqep1_index", "gpio1_22"),
_AM33XX_MUXENTRY(GPMC_A7, 0,
"gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
- NULL, NULL, NULL, "gpio1_23"),
+ "gpmc_a23", "pr1_mii1_rxd1", "eqep1_strobe", "gpio1_23"),
_AM33XX_MUXENTRY(GPMC_A8, 0,
"gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
- NULL, NULL, "mcasp0_aclkx", "gpio1_24"),
+ "gpmc_a24", "pr1_mii1_rxd0", "mcasp0_aclkx", "gpio1_24"),
_AM33XX_MUXENTRY(GPMC_A9, 0,
"gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
- NULL, NULL, "mcasp0_fsx", "gpio1_25"),
+ "gpmc_a25", "pr1_mii_mr1_clk", "mcasp0_fsx", "gpio1_25"),
_AM33XX_MUXENTRY(GPMC_A10, 0,
"gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1",
- NULL, NULL, "mcasp0_axr0", "gpio1_26"),
+ "gpmc_a26", "pr1_mii1_rxdv", "mcasp0_axr0", "gpio1_26"),
_AM33XX_MUXENTRY(GPMC_A11, 0,
"gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0",
- NULL, NULL, "mcasp0_axr1", "gpio1_27"),
+ "gpmc_a27", "pr1_mii1_rxer", "mcasp0_axr1", "gpio1_27"),
_AM33XX_MUXENTRY(GPMC_WAIT0, 0,
- "gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv",
- "mmc1_sdcd", NULL, NULL, "gpio0_30"),
+ "gpmc_wait0", "mii2_crs", "gpmc_csn4", "rmii2_crs_dv",
+ "mmc1_sdcd", "pr1_mii1_col", "uart4_rxd", "gpio0_30"),
_AM33XX_MUXENTRY(GPMC_WPN, 0,
- "gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr",
- "mmc2_sdcd", NULL, NULL, "gpio0_31"),
+ "gpmc_wpn", "mii2_rxerr", "gpmc_csn5", "rmii2_rxerr",
+ "mmc2_sdcd", "pr1_mii1_txen", "uart4_txd", "gpio0_31"),
_AM33XX_MUXENTRY(GPMC_BEN1, 0,
- "gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
- NULL, NULL, "mcasp0_aclkr", "gpio1_28"),
+ "gpmc_ben1", "mii2_col", "gpmc_csn6", "mmc2_dat3",
+ "gpmc_dir", "pr1_mii1_rxlink", "mcasp0_aclkr", "gpio1_28"),
_AM33XX_MUXENTRY(GPMC_CSN0, 0,
"gpmc_csn0", NULL, NULL, NULL,
NULL, NULL, NULL, "gpio1_29"),
_AM33XX_MUXENTRY(GPMC_CSN1, 0,
- "gpmc_csn1", NULL, "mmc1_clk", NULL,
- NULL, NULL, NULL, "gpio1_30"),
+ "gpmc_csn1", "gpmc_clk", "mmc1_clk", "pr1_edio_data_in6",
+ "pr1_edio_data_out6", "pr1_pru1_pru_r30_12", "pr1_pru1_pru_r31_12", "gpio1_30"),
_AM33XX_MUXENTRY(GPMC_CSN2, 0,
- "gpmc_csn2", NULL, "mmc1_cmd", NULL,
- NULL, NULL, NULL, "gpio1_31"),
+ "gpmc_csn2", "gpmc_be1n", "mmc1_cmd", "pr1_edio_data_in7",
+ "pr1_edio_data_out7", "pr1_pru1_pru_r30_13", "pr1_pru1_pru_r31_13", "gpio1_31"),
_AM33XX_MUXENTRY(GPMC_CSN3, 0,
"gpmc_csn3", NULL, NULL, "mmc2_cmd",
- NULL, NULL, NULL, "gpio2_0"),
+ "pr1_mii0_crs", "pr1_mdio_data", "emu4", "gpio2_0"),
_AM33XX_MUXENTRY(GPMC_CLK, 0,
- "gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk",
- NULL, NULL, "mcasp0_fsr", "gpio2_1"),
+ "gpmc_clk", "lcd_memory_clk_mux", "gpmc_wait1", "mmc2_clk",
+ "pr1_mii1_crs", "pr1_mdio_mdclk", "mcasp0_fsr", "gpio2_1"),
_AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
- "gpmc_advn_ale", NULL, NULL, NULL,
+ "gpmc_advn_ale", NULL, "timer4", NULL,
NULL, NULL, NULL, "gpio2_2"),
_AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
- "gpmc_oen_ren", NULL, NULL, NULL,
+ "gpmc_oen_ren", NULL, "timer7", NULL,
NULL, NULL, NULL, "gpio2_3"),
_AM33XX_MUXENTRY(GPMC_WEN, 0,
- "gpmc_wen", NULL, NULL, NULL,
+ "gpmc_wen", NULL, "timer6", NULL,
NULL, NULL, NULL, "gpio2_4"),
_AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
- "gpmc_ben0_cle", NULL, NULL, NULL,
+ "gpmc_ben0_cle", NULL, "timer5", NULL,
NULL, NULL, NULL, "gpio2_5"),
_AM33XX_MUXENTRY(LCD_DATA0, 0,
- "lcd_data0", "gpmc_a0", NULL, NULL,
- NULL, NULL, NULL, "gpio2_6"),
+ "lcd_data0", "gpmc_a0", "pr1_mii_mt0_clk2", "ehrpwm2a",
+ NULL, "pr1_pru1_pru_r30_02", "pr1_pru1_pru_r31_0", "gpio2_6"),
_AM33XX_MUXENTRY(LCD_DATA1, 0,
- "lcd_data1", "gpmc_a1", NULL, NULL,
- NULL, NULL, NULL, "gpio2_7"),
+ "lcd_data1", "gpmc_a1", "pr1_mii0_txen", "ehrpwm2b",
+ NULL, "pr1_pru1_pru_r30_1", "pr1_pru1_pru_r31_1", "gpio2_7"),
_AM33XX_MUXENTRY(LCD_DATA2, 0,
- "lcd_data2", "gpmc_a2", NULL, NULL,
- NULL, NULL, NULL, "gpio2_8"),
+ "lcd_data2", "gpmc_a2", "pr1_mii0_txd3", "ehrpwm2_tripzone_input",
+ NULL, "pr1_mii0_txd3", "ehrpwm2_tripzone_input", "gpio2_8"),
_AM33XX_MUXENTRY(LCD_DATA3, 0,
- "lcd_data3", "gpmc_a3", NULL, NULL,
- NULL, NULL, NULL, "gpio2_9"),
+ "lcd_data3", "gpmc_a3", "pr1_mii0_txd2", "ehrpwm0_synco",
+ NULL, "pr1_pru1_pru_r30_3", "pr1_pru1_pru_r31_3", "gpio2_9"),
_AM33XX_MUXENTRY(LCD_DATA4, 0,
- "lcd_data4", "gpmc_a4", NULL, NULL,
- NULL, NULL, NULL, "gpio2_10"),
+ "lcd_data4", "gpmc_a4", "pr1_mii0_txd1", "eqep2a_in",
+ NULL, "pr1_pru1_pru_r30_4", "pr1_pru1_pru_r31_4", "gpio2_10"),
_AM33XX_MUXENTRY(LCD_DATA5, 0,
- "lcd_data5", "gpmc_a5", NULL, NULL,
- NULL, NULL, NULL, "gpio2_11"),
+ "lcd_data5", "gpmc_a5", "pr1_mii0_txd0", "eqep2b_in",
+ NULL, "pr1_pru1_pru_r30_5", "pr1_pru1_pru_r31_5", "gpio2_11"),
_AM33XX_MUXENTRY(LCD_DATA6, 0,
- "lcd_data6", "gpmc_a6", NULL, NULL,
- NULL, NULL, NULL, "gpio2_12"),
+ "lcd_data6", "gpmc_a6", "pr1_edio_data_in6", "eqep2_index",
+ "pr1_edio_data_out6", "pr1_pru1_pru_r30_6", "pr1_pru1_pru_r31_6", "gpio2_12"),
_AM33XX_MUXENTRY(LCD_DATA7, 0,
- "lcd_data7", "gpmc_a7", NULL, NULL,
- NULL, NULL, NULL, "gpio2_13"),
+ "lcd_data7", "gpmc_a7", "pr1_edio_data_in7", "eqep2_strobe",
+ "pr1_edio_data_out7", "pr1_pru1_pru_r30_7", "pr1_pru1_pru_r31_7", "gpio2_13"),
_AM33XX_MUXENTRY(LCD_DATA8, 0,
- "lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
- NULL, NULL, "uart2_ctsn", "gpio2_14"),
+ "lcd_data8", "gpmc_a12", "ehrpwm1_tripzone_input", "mcasp0_aclkx",
+ "uart5_txd", "pr1_mii0_rxd3", "uart2_ctsn", "gpio2_14"),
_AM33XX_MUXENTRY(LCD_DATA9, 0,
- "lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
- NULL, NULL, "uart2_rtsn", "gpio2_15"),
+ "lcd_data9", "gpmc_a13", "ehrpwm0_synco", "mcasp0_fsx",
+ "uart5_rxd", "pr1_mii0_rxd2", "uart2_rtsn", "gpio2_15"),
_AM33XX_MUXENTRY(LCD_DATA10, 0,
- "lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
- NULL, NULL, NULL, "gpio2_16"),
+ "lcd_data10", "gpmc_a14", "ehrpwm1a", "mcasp0_axr0",
+ NULL, "pr1_mii0_rxd1,uart3_ctsn", "gpio2_16"),
_AM33XX_MUXENTRY(LCD_DATA11, 0,
- "lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",
- "mcasp0_axr2", NULL, NULL, "gpio2_17"),
+ "lcd_data11", "gpmc_a15", "ehrpwm1b", "mcasp0_ahclkr",
+ "mcasp0_axr2", "pr1_mii0_rxd0", "uart3_rtsn", "gpio2_17"),
_AM33XX_MUXENTRY(LCD_DATA12, 0,
- "lcd_data12", "gpmc_a16", NULL, "mcasp0_aclkr",
- "mcasp0_axr2", NULL, NULL, "gpio0_8"),
+ "lcd_data12", "gpmc_a16", "eqep1a_in", "mcasp0_aclkr",
+ "mcasp0_axr2", "pr1_mii0_rxlink", "uart4_ctsn", "gpio0_8"),
_AM33XX_MUXENTRY(LCD_DATA13, 0,
- "lcd_data13", "gpmc_a17", NULL, "mcasp0_fsr",
- "mcasp0_axr3", NULL, NULL, "gpio0_9"),
+ "lcd_data13", "gpmc_a17", "eqep1b_in", "mcasp0_fsr",
+ "mcasp0_axr3", "pr1_mii0_rxer", "uart4_rtsn", "gpio0_9"),
_AM33XX_MUXENTRY(LCD_DATA14, 0,
- "lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1",
- NULL, NULL, NULL, "gpio0_10"),
+ "lcd_data14", "gpmc_a18", "eqep1_index", "mcasp0_axr1",
+ "uart5_rxd", "pr1_mii_mr0_clk", "uart5_ctsn", "gpio0_10"),
_AM33XX_MUXENTRY(LCD_DATA15, 0,
- "lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",
- "mcasp0_axr3", NULL, NULL, "gpio0_11"),
+ "lcd_data15", "gpmc_a19", "eqep1_strobe", "mcasp0_ahclkx",
+ "mcasp0_axr3", "pr1_mii0_rxdv", "uart5_rtsn", "gpio0_11"),
_AM33XX_MUXENTRY(LCD_VSYNC, 0,
- "lcd_vsync", NULL, NULL, NULL,
- NULL, NULL, NULL, "gpio2_22"),
+ "lcd_vsync", "gpmc_a8", NULL, "pr1_edio_data_in2",
+ "pr1_edio_data_out2", "pr1_pru1_pru_r30_8", "pr1_pru1_pru_r31_8", "gpio2_22"),
_AM33XX_MUXENTRY(LCD_HSYNC, 0,
- "lcd_hsync", NULL, NULL, NULL,
- NULL, NULL, NULL, "gpio2_23"),
+ "lcd_hsync", "gpmc_a9", NULL, "pr1_edio_data_in3",
+ "pr1_edio_data_out3", "pr1_pru1_pru_r30_9", "pr1_pru1_pru_r31_9", "gpio2_23"),
_AM33XX_MUXENTRY(LCD_PCLK, 0,
- "lcd_pclk", NULL, NULL, NULL,
- NULL, NULL, NULL, "gpio2_24"),
+ "lcd_pclk", "gpmc_a10", "pr1_mii0_crs", "pr1_edio_data_in4",
+ "pr1_edio_data_out4", "pr1_pru1_pru_r30_10", "pr1_pru1_pru_r31_10", "gpio2_24"),
_AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
- "lcd_ac_bias_en", NULL, NULL, NULL,
- NULL, NULL, NULL, "gpio2_25"),
+ "lcd_ac_bias_en", "gpmc_a11", "pr1_mii1_crs", "pr1_edio_data_in5",
+ "pr1_edio_data_out5", "pr1_pru1_pru_r30_11", "pr1_pru1_pru_r31_11", "gpio2_25"),
_AM33XX_MUXENTRY(MMC0_DAT3, 0,
- "mmc0_dat3", NULL, NULL, NULL,
- NULL, NULL, NULL, "gpio2_26"),
+ "mmc0_dat3", "gpmc_a20", "uart4_ctsn", "timer5",
+ "uart1_dcdn", "pr1_pru0_pru_r30_8", "pr1_pru0_pru_r31_8", "gpio2_26"),
_AM33XX_MUXENTRY(MMC0_DAT2, 0,
- "mmc0_dat2", NULL, NULL, NULL,
- NULL, NULL, NULL, "gpio2_27"),
+ "mmc0_dat2", "gpmc_a21", "uart4_rtsn", "timer6",
+ "uart1_dsrn", "pr1_pru0_pru_r30_9", "pr1_pru0_pru_r31_9", "gpio2_27"),
_AM33XX_MUXENTRY(MMC0_DAT1, 0,
- "mmc0_dat1", NULL, NULL, NULL,
- NULL, NULL, NULL, "gpio2_28"),
+ "mmc0_dat1", "gpmc_a22", "uart5_ctsn", "uart3_rxd",
+ "uart1_dtrn", "pr1_pru0_pru_r30_10", "pr1_pru0_pru_r31_10", "gpio2_28"),
_AM33XX_MUXENTRY(MMC0_DAT0, 0,
"mmc0_dat0", "gpmc_a23", "uart5_rtsn", "uart3_txd",
- "uart1_rin", NULL, NULL, "gpio2_29"),
+ "uart1_rin", "pr1_pru0_pru_r30_11", "pr1_pru0_pru_r31_11", "gpio2_29"),
_AM33XX_MUXENTRY(MMC0_CLK, 0,
"mmc0_clk", "gpmc_a24", "uart3_ctsn", "uart2_rxd",
- "dcan1_tx", "pr1_pru0_pru_r30_12", "pr1_pru0_pru_r31_12", "gpio2_30"),
+ "d_can1_tx", "pr1_pru0_pru_r30_12", "pr1_pru0_pru_r31_12", "gpio2_30"),
_AM33XX_MUXENTRY(MMC0_CMD, 0,
- "mmc0_cmd", NULL, NULL, NULL,
- NULL, NULL, NULL, "gpio2_31"),
+ "mmc0_cmd", "gpmc_a25", "uart3_rtsn", "uart2_txd",
+ "d_can1_rx", "pr1_pru0_pru_r30_13", "pr1_pru0_pru_r31_13", "gpio2_31"),
_AM33XX_MUXENTRY(MII1_COL, 0,
- "mii1_col", "rmii2_refclk", "spi1_sclk", "uart5_rxd",
+ "gmii1_col", "rmii2_refclk", "spi1_sclk", "uart5_rxd",
"mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"),
_AM33XX_MUXENTRY(MII1_CRS, 0,
- "mii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda",
- "mcasp1_aclkx", NULL, NULL, "gpio3_1"),
+ "gmii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda",
+ "mcasp1_aclkx", "uart5_ctsn", "uart2_rxd", "gpio3_1"),
_AM33XX_MUXENTRY(MII1_RXERR, 0,
- "mii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl",
- "mcasp1_fsx", NULL, NULL, "gpio3_2"),
+ "gmii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl",
+ "mcasp1_fsx", "uart5_rtsn", "uart2_txd", "gpio3_2"),
_AM33XX_MUXENTRY(MII1_TXEN, 0,
- "mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,
- "mcasp1_axr0", NULL, "mmc2_cmd", "gpio3_3"),
+ "gmii1_txen", "rmii1_txen", "rgmii1_tctl", "timer4",
+ "mcasp1_axr0", "eqep0_index", "mmc2_cmd", "gpio3_3"),
_AM33XX_MUXENTRY(MII1_RXDV, 0,
- "mii1_rxdv", NULL, "rgmii1_rctl", "uart5_txd",
+ "gmii1_rxdv", "lcd_memory_clk", "rgmii1_rctl", "uart5_txd",
"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", "gpio3_4"),
_AM33XX_MUXENTRY(MII1_TXD3, 0,
- "mii1_txd3", "dcan0_tx", "rgmii1_td3", "uart4_rxd",
+ "gmii1_txd3", "d_can0_tx", "rgmii1_td3", "uart4_rxd",
"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", "gpio0_16"),
_AM33XX_MUXENTRY(MII1_TXD2, 0,
- "mii1_txd2", "dcan0_rx", "rgmii1_td2", "uart4_txd",
+ "gmii1_txd2", "d_can0_rx", "rgmii1_td2", "uart4_txd",
"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", "gpio0_17"),
_AM33XX_MUXENTRY(MII1_TXD1, 0,
- "mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
- "mcasp1_axr1", NULL, "mmc1_cmd", "gpio0_21"),
+ "gmii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
+ "mcasp1_axr1", "eqep0a_in", "mmc1_cmd", "gpio0_21"),
_AM33XX_MUXENTRY(MII1_TXD0, 0,
- "mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
- "mcasp1_aclkr", NULL, "mmc1_clk", "gpio0_28"),
+ "gmii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
+ "mcasp1_aclkr", "eqep0b_in", "mmc1_clk", "gpio0_28"),
_AM33XX_MUXENTRY(MII1_TXCLK, 0,
- "mii1_txclk", "uart2_rxd", "rgmii1_tclk", "mmc0_dat7",
+ "gmii1_txclk", "uart2_rxd", "rgmii1_tclk", "mmc0_dat7",
"mmc1_dat0", "uart1_dcdn", "mcasp0_aclkx", "gpio3_9"),
_AM33XX_MUXENTRY(MII1_RXCLK, 0,
- "mii1_rxclk", "uart2_txd", "rgmii1_rclk", "mmc0_dat6",
+ "gmii1_rxclk", "uart2_txd", "rgmii1_rclk", "mmc0_dat6",
"mmc1_dat1", "uart1_dsrn", "mcasp0_fsx", "gpio3_10"),
_AM33XX_MUXENTRY(MII1_RXD3, 0,
- "mii1_rxd3", NULL, "rgmii1_rd3", "mmc0_dat5",
- "mmc1_dat2", NULL, "mcasp0_axr0", "gpio2_18"),
+ "gmii1_rxd3", "uart3_rxd", "rgmii1_rd3", "mmc0_dat5",
+ "mmc1_dat2", "uart1_dtrn", "mcasp0_axr0", "gpio2_18"),
_AM33XX_MUXENTRY(MII1_RXD2, 0,
- "mii1_rxd2", NULL, "rgmii1_rd2", "mmc0_dat4",
- "mmc1_dat3", NULL, "mcasp0_axr1", "gpio2_19"),
+ "gmii1_rxd2", "uart3_txd", "rgmii1_rd2", "mmc0_dat4",
+ "mmc1_dat3", "uart1_rin", "mcasp0_axr1", "gpio2_19"),
_AM33XX_MUXENTRY(MII1_RXD1, 0,
- "mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",
- "mcasp1_fsr", NULL, "mmc2_clk", "gpio2_20"),
+ "gmii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",
+ "mcasp1_fsr", "eqep0_strobe", "mmc2_clk", "gpio2_20"),
_AM33XX_MUXENTRY(MII1_RXD0, 0,
- "mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
+ "gmii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
"mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", "gpio2_21"),
_AM33XX_MUXENTRY(MII1_REFCLK, 0,
- "rmii1_refclk", NULL, "spi1_cs0", NULL,
+ "rmii1_refclk", "xdma_event_intr2", "spi1_cs0", "uart5_txd",
"mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", "gpio0_29"),
_AM33XX_MUXENTRY(MDIO_DATA, 0,
- "mdio_data", NULL, NULL, NULL,
+ "mdio_data", "timer6", "uart5_rxd", "uart3_ctsn",
"mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", "gpio0_0"),
_AM33XX_MUXENTRY(MDIO_CLK, 0,
- "mdio_clk", NULL, NULL, NULL,
+ "mdio_clk", "timer5", "uart5_txd", "uart3_rtsn",
"mmc0_sdwp", "mmc1_clk", "mmc2_clk", "gpio0_1"),
_AM33XX_MUXENTRY(SPI0_SCLK, 0,
- "spi0_sclk", "uart2_rxd", "i2c2_sda", NULL,
- NULL, NULL, NULL, "gpio0_2"),
+ "spi0_sclk", "uart2_rxd", "i2c2_sda", "ehrpwm0a",
+ "pr1_uart0_cts_n", "pr1_edio_sof", "emu2", "gpio0_2"),
_AM33XX_MUXENTRY(SPI0_D0, 0,
- "spi0_d0", "uart2_txd", "i2c2_scl", NULL,
- NULL, NULL, NULL, "gpio0_3"),
+ "spi0_d0", "uart2_txd", "i2c2_scl", "ehrpwm0b",
+ "pr1_uart0_rts_n", "pr1_edio_latch_in", "emu3", "gpio0_3"),
_AM33XX_MUXENTRY(SPI0_D1, 0,
- "spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL,
- NULL, NULL, NULL, "gpio0_4"),
+ "spi0_d1", "mmc1_sdwp", "i2c1_sda", "ehrpwm0_tripzone_input",
+ "pr1_uart0_rxd", "pr1_edio_data_in0", "pr1_edio_data_out0", "gpio0_4"),
_AM33XX_MUXENTRY(SPI0_CS0, 0,
- "spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL,
- NULL, NULL, NULL, "gpio0_5"),
+ "spi0_cs0", "mmc2_sdwp", "i2c1_scl", "ehrpwm0_synci",
+ "pr1_uart0_txd", "pr1_edio_data_in1", "pr1_edio_data_out1", "gpio0_5"),
_AM33XX_MUXENTRY(SPI0_CS1, 0,
- "spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",
- NULL, "mmc0_sdcd", NULL, "gpio0_6"),
+ "spi0_cs1", "uart3_rxd", "ecap1_in_pwm1_out", "mmc0_pow",
+ "xdma_event_intr2", "mmc0_sdcd", "emu4", "gpio0_6"),
_AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
- "ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL,
- "spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"),
+ "ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", "pr1_ecap0_ecap_capin_apwm_o",
+ "spi1_sclk", "mmc0_sdwp", "xdma_event_intr2", "gpio0_7"),
_AM33XX_MUXENTRY(UART0_CTSN, 0,
- "uart0_ctsn", NULL, "d_can1_tx", "i2c1_sda",
- "spi1_d0", NULL, NULL, "gpio1_8"),
+ "uart0_ctsn", "uart4_rxd", "d_can1_tx", "i2c1_sda",
+ "spi1_d0", "timer7", "pr1_edc_sync0_out", "gpio1_8"),
_AM33XX_MUXENTRY(UART0_RTSN, 0,
- "uart0_rtsn", NULL, "d_can1_rx", "i2c1_scl",
- "spi1_d1", "spi1_cs0", NULL, "gpio1_9"),
+ "uart0_rtsn", "uart4_txd", "d_can1_rx", "i2c1_scl",
+ "spi1_d1", "spi1_cs0", "pr1_edc_sync1_out", "gpio1_9"),
_AM33XX_MUXENTRY(UART0_RXD, 0,
"uart0_rxd", "spi1_cs0", "d_can0_tx", "i2c2_sda",
- NULL, NULL, NULL, "gpio1_10"),
+ "ecap2_in_pwm2_out", "pr1_pru1_pru_r30_14", "pr1_pru1_pru_r31_14", "gpio1_10"),
_AM33XX_MUXENTRY(UART0_TXD, 0,
"uart0_txd", "spi1_cs1", "d_can0_rx", "i2c2_scl",
- NULL, NULL, NULL, "gpio1_11"),
+ "ecap1_in_pwm1_out", "pr1_pru1_pru_r30_15", "pr1_pru1_pru_r31_15", "gpio1_11"),
_AM33XX_MUXENTRY(UART1_CTSN, 0,
- "uart1_ctsn", NULL, NULL, "i2c2_sda",
- "spi1_cs0", NULL, NULL, "gpio0_12"),
+ "uart1_ctsn", "timer6", "d_can0_tx", "i2c2_sda",
+ "spi1_cs0", "pr1_uart0_cts_n", "pr1_edc_latch0_in", "gpio0_12"),
_AM33XX_MUXENTRY(UART1_RTSN, 0,
- "uart1_rtsn", NULL, NULL, "i2c2_scl",
- "spi1_cs1", NULL, NULL, "gpio0_13"),
+ "uart1_rtsn", "timer5", "d_can0_rx", "i2c2_scl",
+ "spi1_cs1", "pr1_uart0_rts_n", "pr1_edc_latch1_in", "gpio0_13"),
_AM33XX_MUXENTRY(UART1_RXD, 0,
- "uart1_rxd", "mmc1_sdwp", NULL, "i2c1_sda",
- NULL, "pr1_uart0_rxd_mux1", NULL, "gpio0_14"),
+ "uart1_rxd", "mmc1_sdwp", "d_can1_tx", "i2c1_sda",
+ NULL, "pr1_uart0_rxd_mux1", "pr1_pru1_pru_r31_16", "gpio0_14"),
_AM33XX_MUXENTRY(UART1_TXD, 0,
- "uart1_txd", "mmc2_sdwp", NULL, "i2c1_scl",
- NULL, "pr1_uart0_txd_mux1", NULL, "gpio0_15"),
+ "uart1_txd", "mmc2_sdwp", "d_can1_rx", "i2c1_scl",
+ NULL, "pr1_uart0_txd_mux1", "pr1_pru0_pru_r31_16", "gpio0_15"),
_AM33XX_MUXENTRY(I2C0_SDA, 0,
- "i2c0_sda", NULL, NULL, NULL,
+ "i2c0_sda", "timer4", "uart2_ctsn", "ecap2_in_pwm2_out",
NULL, NULL, NULL, "gpio3_5"),
_AM33XX_MUXENTRY(I2C0_SCL, 0,
- "i2c0_scl", NULL, NULL, NULL,
+ "i2c0_scl", "timer7", "uart2_rtsn", "ecap1_in_pwm1_out",
NULL, NULL, NULL, "gpio3_6"),
_AM33XX_MUXENTRY(MCASP0_ACLKX, 0,
"mcasp0_aclkx", "ehrpwm0a", NULL, "spi1_sclk",
- "mmc0_sdcd", NULL, NULL, "gpio3_14"),
+ "mmc0_sdcd", "pr1_pru0_pru_r30_0", "pr1_pru0_pru_r31_0", "gpio3_14"),
_AM33XX_MUXENTRY(MCASP0_FSX, 0,
- "mcasp0_fsx", NULL, NULL, "spi1_d0",
- "mmc1_sdcd", NULL, NULL, "gpio3_15"),
+ "mcasp0_fsx", "ehrpwm0b", NULL, "spi1_d0",
+ "mmc1_sdcd", "pr1_pru0_pru_r30_1", "pr1_pru0_pru_r31_1", "gpio3_15"),
_AM33XX_MUXENTRY(MCASP0_AXR0, 0,
- "mcasp0_axr0", NULL, NULL, "spi1_d1",
- "mmc2_sdcd", NULL, NULL, "gpio3_16"),
+ "mcasp0_axr0", "ehrpwm0_tripzone_input", NULL, "spi1_d1",
+ "mmc2_sdcd", "pr1_pru0_pru_r30_2", "pr1_pru0_pru_r31_2", "gpio3_16"),
_AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
- "mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0",
- "ecap2_in_pwm2_out", NULL, NULL, "gpio3_17"),
+ "mcasp0_ahclkr", "ehrpwm0_synci", "mcasp0_axr2", "spi1_cs0",
+ "ecap2_in_pwm2_out", "pr1_pru0_pru_r30_3", "pr1_pru0_pru_r31_3", "gpio3_17"),
_AM33XX_MUXENTRY(MCASP0_ACLKR, 0,
- "mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx",
- "mmc0_sdwp", NULL, NULL, "gpio3_18"),
+ "mcasp0_aclkr", "eqep0a_in", "mcasp0_axr2", "mcasp1_aclkx",
+ "mmc0_sdwp", "pr1_pru0_pru_r30_4", "pr1_pru0_pru_r31_4", "gpio3_18"),
_AM33XX_MUXENTRY(MCASP0_FSR, 0,
- "mcasp0_fsr", NULL, "mcasp0_axr3", "mcasp1_fsx",
- NULL, "pr1_pru0_pru_r30_5", NULL, "gpio3_19"),
+ "mcasp0_fsr", "eqep0b_in", "mcasp0_axr3", "mcasp1_fsx",
+ "emu2", "pr1_pru0_pru_r30_5", "pr1_pru0_pru_r31_5", "gpio3_19"),
_AM33XX_MUXENTRY(MCASP0_AXR1, 0,
- "mcasp0_axr1", NULL, NULL, "mcasp1_axr0",
- NULL, NULL, NULL, "gpio3_20"),
+ "mcasp0_axr1", "eqep0_index", NULL, "mcasp1_axr0",
+ "emu3", "pr1_pru0_pru_r30_6", "pr1_pru0_pru_r31_6", "gpio3_20"),
_AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,
- "mcasp0_ahclkx", NULL, "mcasp0_axr3", "mcasp1_axr1",
- NULL, NULL, NULL, "gpio3_21"),
+ "mcasp0_ahclkx", "eqep0_strobe", "mcasp0_axr3", "mcasp1_axr1",
+ "emu4", "pr1_pru0_pru_r30_7", "pr1_pru0_pru_r31_7", "gpio3_21"),
_AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
- "xdma_event_intr0", NULL, NULL, "clkout1",
- "spi1_cs1", NULL, NULL, "gpio0_19"),
+ "xdma_event_intr0", NULL, "timer4", "clkout1",
+ "spi1_cs1", "pr1_pru1_pru_r31_16", "emu2", "gpio0_19"),
_AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,
- "xdma_event_intr1", NULL, NULL, "clkout2",
- NULL, NULL, NULL, "gpio0_20"),
+ "xdma_event_intr1", NULL, "tclkin", "clkout2",
+ "timer7", "pr1_pru0_pru_r31_16", "emu3", "gpio0_20"),
_AM33XX_MUXENTRY(WARMRSTN, 0,
"warmrstn", NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(PWRONRSTN, 0,
+ "porz", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
_AM33XX_MUXENTRY(NMIN, 0,
"nmin", NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(XTALIN, 0,
+ "osc0_in", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(XTALOUT, 0,
+ "osc0_out", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
_AM33XX_MUXENTRY(TMS, 0,
"tms", NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_AM33XX_MUXENTRY(EMU1, 0,
"emu1", NULL, NULL, NULL,
NULL, NULL, NULL, "gpio3_8"),
+ _AM33XX_MUXENTRY(RTC_XTALIN, 0,
+ "osc1_in", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(RTC_XTALOUT, 0,
+ "osc1_out", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
_AM33XX_MUXENTRY(RTC_PWRONRSTN, 0,
"rtc_pwronrstn", NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_AM33XX_MUXENTRY(RTC_KALDO_ENN, 0,
"rtc_kaldo_enn", NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(USB0_DM, 0,
+ "usb0_dm", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(USB0_DP, 0,
+ "usb0_dp", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(USB0_CE, 0,
+ "usb0_ce", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(USB0_ID, 0,
+ "usb0_id", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(USB0_VBUS, 0,
+ "usb0_vbus", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
_AM33XX_MUXENTRY(USB0_DRVVBUS, 0,
"usb0_drvvbus", NULL, NULL, NULL,
NULL, NULL, NULL, "gpio0_18"),
+ _AM33XX_MUXENTRY(USB1_DM, 0,
+ "usb0_dm", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(USB1_DP, 0,
+ "usb0_dp", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(USB1_CE, 0,
+ "usb0_ce", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(USB1_ID, 0,
+ "usb0_id", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(USB1_VBUS, 0,
+ "usb0_vbus", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
_AM33XX_MUXENTRY(USB1_DRVVBUS, 0,
"usb1_drvvbus", NULL, NULL, NULL,
NULL, NULL, NULL, "gpio3_13"),
projects / karo-tx-linux.git / commitdiff