Merge git://git.denx.de/u-boot-socfpga

diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 546560979bd97809dd550c1f31437ab23c7f979e..9eb5a2209c63b721ec5bc7fd773572703ef368be 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -89,7 +89,7 @@
                #size-cells = <1>;
                compatible = "n25q00";
                reg = <0>;      /* chip select */
-               spi-max-frequency = <50000000>;
+               spi-max-frequency = <100000000>;
                m25p,fast-read;
                page-size = <256>;
                block-size = <16>; /* 2^16, 64KB */

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 8e59578f374b7f799a36a3998b4f874beddd5d5d..666a2ef8dfc7d5599aaa21a8d3bc6c39aa96e8d2 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -69,9 +69,9 @@ struct socfpga_reset_manager {
 #define RSTMGR_UART0           RSTMGR_DEFINE(1, 16)
 #define RSTMGR_SPIM0           RSTMGR_DEFINE(1, 18)
 #define RSTMGR_SPIM1           RSTMGR_DEFINE(1, 19)
-#define RSTMGR_QSPI            RSTMGR_DEFINE(0, 5)
-#define RSTMGR_SDMMC           RSTMGR_DEFINE(0, 22)
-#define RSTMGR_DMA             RSTMGR_DEFINE(0, 28)
+#define RSTMGR_QSPI            RSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC           RSTMGR_DEFINE(1, 22)
+#define RSTMGR_DMA             RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR             RSTMGR_DEFINE(1, 29)
 
 /* Create a human-readable reference to SoCFPGA reset. */

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 34a0f46a1ae0d5de7a43270acc9b87025d63950d..4f7fd5253220882c7074ac62bdcb5e4461a48b07 100644 (file)
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -37,9 +37,8 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz)
 }
 
 /* Calibration sequence to determine the read data capture delay register */
-static int spi_calibration(struct udevice *bus)
+static int spi_calibration(struct udevice *bus, uint hz)
 {
-       struct cadence_spi_platdata *plat = bus->platdata;
        struct cadence_spi_priv *priv = dev_get_priv(bus);
        void *base = priv->regbase;
        u8 opcode_rdid = 0x9F;
@@ -64,7 +63,7 @@ static int spi_calibration(struct udevice *bus)
        }
 
        /* use back the intended clock and find low range */
-       cadence_spi_write_speed(bus, plat->max_hz);
+       cadence_spi_write_speed(bus, hz);
        for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
                /* Disable QSPI */
                cadence_qspi_apb_controller_disable(base);
@@ -111,7 +110,7 @@ static int spi_calibration(struct udevice *bus)
              (range_hi + range_lo) / 2, range_lo, range_hi);
 
        /* just to ensure we do once only when speed or chip select change */
-       priv->qspi_calibrated_hz = plat->max_hz;
+       priv->qspi_calibrated_hz = hz;
        priv->qspi_calibrated_cs = spi_chip_select(bus);
 
        return 0;
@@ -123,17 +122,25 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
        struct cadence_spi_priv *priv = dev_get_priv(bus);
        int err;
 
+       if (hz > plat->max_hz)
+               hz = plat->max_hz;
+
        /* Disable QSPI */
        cadence_qspi_apb_controller_disable(priv->regbase);
 
-       cadence_spi_write_speed(bus, hz);
-
-       /* Calibration required for different SCLK speed or chip select */
-       if (priv->qspi_calibrated_hz != plat->max_hz ||
+       /*
+        * Calibration required for different current SCLK speed, requested
+        * SCLK speed or chip select
+        */
+       if (priv->previous_hz != hz ||
+           priv->qspi_calibrated_hz != hz ||
            priv->qspi_calibrated_cs != spi_chip_select(bus)) {
-               err = spi_calibration(bus);
+               err = spi_calibration(bus, hz);
                if (err)
                        return err;
+
+               /* prevent calibration run when same as previous request */
+               priv->previous_hz = hz;
        }
 
        /* Enable QSPI */
@@ -291,10 +298,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
        plat->regbase = (void *)data[0];
        plat->ahbbase = (void *)data[2];
 
-       /* Use 500KHz as a suitable default */
-       plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
-                                     500000);
-
        /* All other paramters are embedded in the child node */
        subnode = fdt_first_subnode(blob, node);
        if (subnode < 0) {
@@ -302,6 +305,10 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
                return -ENODEV;
        }
 
+       /* Use 500 KHz as a suitable default */
+       plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency",
+                                      500000);
+
        /* Read other parameters from DT */
        plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
        plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);

diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 98e57aa5bccceaedff06f0a9d7819db36bd3fb20..2912e36a53f7601f1d1251a1888c922ab6a7532c 100644 (file)
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -38,6 +38,7 @@ struct cadence_spi_priv {
        int             qspi_is_init;
        unsigned int    qspi_calibrated_hz;
        unsigned int    qspi_calibrated_cs;
+       unsigned int    previous_hz;
 };
 
 /* Functions call declaration */

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 9fcc7a1e19997cbf729df718c268e8141b22d625..0e36664dca4aed281222a97388089049e1f10ae7 100644 (file)
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -489,6 +489,19 @@ int fdtdec_get_pci_bar32(const void *blob, int node,
 s32 fdtdec_get_int(const void *blob, int node, const char *prop_name,
                s32 default_val);
 
+/**
+ * Unsigned version of fdtdec_get_int. The property must have at least
+ * 4 bytes of data. The value of the first cell is returned.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param prop_name    name of property to find
+ * @param default_val  default value to return if the property is not found
+ * @return unsigned integer value, if found, or default_val if not
+ */
+unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name,
+                       unsigned int default_val);
+
 /**
  * Get a variable-sized number from a property
  *

diff --git a/lib/fdtdec_common.c b/lib/fdtdec_common.c
index 757931a9cb25119b3283b12bc985310310dae4d0..63b704a3d719b178c79da4068a477aded2c80e9f 100644 (file)
--- a/lib/fdtdec_common.c
+++ b/lib/fdtdec_common.c
@@ -36,3 +36,21 @@ int fdtdec_get_int(const void *blob, int node, const char *prop_name,
        debug("(not found)\n");
        return default_val;
 }
+
+unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name,
+                       unsigned int default_val)
+{
+       const int *cell;
+       int len;
+
+       debug("%s: %s: ", __func__, prop_name);
+       cell = fdt_getprop(blob, node, prop_name, &len);
+       if (cell && len >= sizeof(unsigned int)) {
+               unsigned int val = fdt32_to_cpu(cell[0]);
+
+               debug("%#x (%d)\n", val, val);
+               return val;
+       }
+       debug("(not found)\n");
+       return default_val;
+}